1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2015-2020
5 #ifndef _TXGBE_ETHDEV_H_
6 #define _TXGBE_ETHDEV_H_
8 #include "base/txgbe.h"
9 #include "txgbe_ptypes.h"
11 /* need update link, bit flag */
12 #define TXGBE_FLAG_NEED_LINK_UPDATE (uint32_t)(1 << 0)
13 #define TXGBE_FLAG_MAILBOX (uint32_t)(1 << 1)
14 #define TXGBE_FLAG_PHY_INTERRUPT (uint32_t)(1 << 2)
15 #define TXGBE_FLAG_MACSEC (uint32_t)(1 << 3)
16 #define TXGBE_FLAG_NEED_LINK_CONFIG (uint32_t)(1 << 4)
19 * Defines that were not part of txgbe_type.h as they are not used by the
22 #define TXGBE_VFTA_SIZE 128
23 #define TXGBE_VLAN_TAG_SIZE 4
24 #define TXGBE_HKEY_MAX_INDEX 10
25 /*Default value of Max Rx Queue*/
26 #define TXGBE_MAX_RX_QUEUE_NUM 128
27 #define TXGBE_VMDQ_DCB_NB_QUEUES TXGBE_MAX_RX_QUEUE_NUM
30 #define NBBY 8 /* number of bits in a byte */
32 #define TXGBE_HWSTRIP_BITMAP_SIZE \
33 (TXGBE_MAX_RX_QUEUE_NUM / (sizeof(uint32_t) * NBBY))
35 #define TXGBE_QUEUE_ITR_INTERVAL_DEFAULT 500 /* 500us */
37 #define TXGBE_MAX_QUEUE_NUM_PER_VF 8
39 #define TXGBE_RSS_OFFLOAD_ALL ( \
41 ETH_RSS_NONFRAG_IPV4_TCP | \
42 ETH_RSS_NONFRAG_IPV4_UDP | \
44 ETH_RSS_NONFRAG_IPV6_TCP | \
45 ETH_RSS_NONFRAG_IPV6_UDP | \
47 ETH_RSS_IPV6_TCP_EX | \
50 #define TXGBE_MISC_VEC_ID RTE_INTR_VEC_ZERO_OFFSET
51 #define TXGBE_RX_VEC_START RTE_INTR_VEC_RXTX_OFFSET
53 /* structure for interrupt relative data */
54 struct txgbe_interrupt {
57 /* to save original mask during delayed handler */
58 uint32_t mask_misc_orig;
62 #define TXGBE_NB_STAT_MAPPING 32
63 #define QSM_REG_NB_BITS_PER_QMAP_FIELD 8
64 #define NB_QMAP_FIELDS_PER_QSM_REG 4
65 #define QMAP_FIELD_RESERVED_BITS_MASK 0x0f
66 struct txgbe_stat_mappings {
67 uint32_t tqsm[TXGBE_NB_STAT_MAPPING];
68 uint32_t rqsm[TXGBE_NB_STAT_MAPPING];
72 uint32_t vfta[TXGBE_VFTA_SIZE];
75 struct txgbe_hwstrip {
76 uint32_t bitmap[TXGBE_HWSTRIP_BITMAP_SIZE];
80 * VF data which used by PF host only
82 #define TXGBE_MAX_VF_MC_ENTRIES 30
84 struct txgbe_uta_info {
85 uint8_t uc_filter_type;
87 uint32_t uta_shadow[TXGBE_MAX_UTA];
90 #define TXGBE_MAX_MIRROR_RULES 4 /* Maximum nb. of mirror rules. */
92 struct txgbe_mirror_info {
93 struct rte_eth_mirror_conf mr_conf[TXGBE_MAX_MIRROR_RULES];
94 /* store PF mirror rules configuration */
97 struct txgbe_vf_info {
98 uint8_t vf_mac_addresses[RTE_ETHER_ADDR_LEN];
99 uint16_t vf_mc_hashes[TXGBE_MAX_VF_MC_ENTRIES];
100 uint16_t num_vf_mc_hashes;
102 uint16_t tx_rate[TXGBE_MAX_QUEUE_NUM_PER_VF];
105 uint16_t switch_domain_id;
110 struct txgbe_ethertype_filter {
115 * If this filter is added by configuration,
116 * it should not be removed.
122 * Structure to store filters' info.
124 struct txgbe_filter_info {
125 uint8_t ethertype_mask; /* Bit mask for every used ethertype filter */
126 /* store used ethertype filters*/
127 struct txgbe_ethertype_filter ethertype_filters[TXGBE_ETF_ID_MAX];
131 * Structure to store private data for each driver instance (for each port).
133 struct txgbe_adapter {
135 struct txgbe_hw_stats stats;
136 struct txgbe_interrupt intr;
137 struct txgbe_stat_mappings stat_mappings;
138 struct txgbe_vfta shadow_vfta;
139 struct txgbe_hwstrip hwstrip;
140 struct txgbe_mirror_info mr_data;
141 struct txgbe_vf_info *vfdata;
142 struct txgbe_uta_info uta_info;
143 struct txgbe_filter_info filter;
144 bool rx_bulk_alloc_allowed;
145 /* For RSS reta table update */
146 uint8_t rss_reta_updated;
149 #define TXGBE_DEV_ADAPTER(dev) \
150 ((struct txgbe_adapter *)(dev)->data->dev_private)
152 #define TXGBE_DEV_HW(dev) \
153 (&((struct txgbe_adapter *)(dev)->data->dev_private)->hw)
155 #define TXGBE_DEV_STATS(dev) \
156 (&((struct txgbe_adapter *)(dev)->data->dev_private)->stats)
158 #define TXGBE_DEV_INTR(dev) \
159 (&((struct txgbe_adapter *)(dev)->data->dev_private)->intr)
161 #define TXGBE_DEV_STAT_MAPPINGS(dev) \
162 (&((struct txgbe_adapter *)(dev)->data->dev_private)->stat_mappings)
164 #define TXGBE_DEV_VFTA(dev) \
165 (&((struct txgbe_adapter *)(dev)->data->dev_private)->shadow_vfta)
167 #define TXGBE_DEV_HWSTRIP(dev) \
168 (&((struct txgbe_adapter *)(dev)->data->dev_private)->hwstrip)
170 #define TXGBE_DEV_VFDATA(dev) \
171 (&((struct txgbe_adapter *)(dev)->data->dev_private)->vfdata)
173 #define TXGBE_DEV_MR_INFO(dev) \
174 (&((struct txgbe_adapter *)(dev)->data->dev_private)->mr_data)
176 #define TXGBE_DEV_UTA_INFO(dev) \
177 (&((struct txgbe_adapter *)(dev)->data->dev_private)->uta_info)
179 #define TXGBE_DEV_FILTER(dev) \
180 (&((struct txgbe_adapter *)(dev)->data->dev_private)->filter)
183 * RX/TX function prototypes
185 void txgbe_dev_clear_queues(struct rte_eth_dev *dev);
187 void txgbe_dev_free_queues(struct rte_eth_dev *dev);
189 void txgbe_dev_rx_queue_release(void *rxq);
191 void txgbe_dev_tx_queue_release(void *txq);
193 int txgbe_dev_rx_queue_setup(struct rte_eth_dev *dev, uint16_t rx_queue_id,
194 uint16_t nb_rx_desc, unsigned int socket_id,
195 const struct rte_eth_rxconf *rx_conf,
196 struct rte_mempool *mb_pool);
198 int txgbe_dev_tx_queue_setup(struct rte_eth_dev *dev, uint16_t tx_queue_id,
199 uint16_t nb_tx_desc, unsigned int socket_id,
200 const struct rte_eth_txconf *tx_conf);
202 int txgbe_dev_rx_init(struct rte_eth_dev *dev);
204 void txgbe_dev_tx_init(struct rte_eth_dev *dev);
206 int txgbe_dev_rxtx_start(struct rte_eth_dev *dev);
208 void txgbe_dev_save_rx_queue(struct txgbe_hw *hw, uint16_t rx_queue_id);
209 void txgbe_dev_store_rx_queue(struct txgbe_hw *hw, uint16_t rx_queue_id);
210 void txgbe_dev_save_tx_queue(struct txgbe_hw *hw, uint16_t tx_queue_id);
211 void txgbe_dev_store_tx_queue(struct txgbe_hw *hw, uint16_t tx_queue_id);
213 int txgbe_dev_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id);
215 int txgbe_dev_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id);
217 int txgbe_dev_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id);
219 int txgbe_dev_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id);
221 void txgbe_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
222 struct rte_eth_rxq_info *qinfo);
224 void txgbe_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
225 struct rte_eth_txq_info *qinfo);
227 uint16_t txgbe_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
230 uint16_t txgbe_recv_pkts_bulk_alloc(void *rx_queue, struct rte_mbuf **rx_pkts,
233 uint16_t txgbe_recv_pkts_lro_single_alloc(void *rx_queue,
234 struct rte_mbuf **rx_pkts, uint16_t nb_pkts);
235 uint16_t txgbe_recv_pkts_lro_bulk_alloc(void *rx_queue,
236 struct rte_mbuf **rx_pkts, uint16_t nb_pkts);
238 uint16_t txgbe_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
241 uint16_t txgbe_xmit_pkts_simple(void *tx_queue, struct rte_mbuf **tx_pkts,
244 uint16_t txgbe_prep_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
247 int txgbe_dev_rss_hash_update(struct rte_eth_dev *dev,
248 struct rte_eth_rss_conf *rss_conf);
250 int txgbe_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
251 struct rte_eth_rss_conf *rss_conf);
253 bool txgbe_rss_update_sp(enum txgbe_mac_type mac_type);
255 void txgbe_set_ivar_map(struct txgbe_hw *hw, int8_t direction,
256 uint8_t queue, uint8_t msix_vector);
259 txgbe_dev_link_update_share(struct rte_eth_dev *dev,
260 int wait_to_complete);
261 void txgbe_pf_host_init(struct rte_eth_dev *eth_dev);
263 void txgbe_pf_host_uninit(struct rte_eth_dev *eth_dev);
265 void txgbe_pf_mbx_process(struct rte_eth_dev *eth_dev);
267 int txgbe_pf_host_configure(struct rte_eth_dev *eth_dev);
269 uint32_t txgbe_convert_vm_rx_mask_to_val(uint16_t rx_mask, uint32_t orig_val);
271 int txgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
272 uint16_t tx_rate, uint64_t q_msk);
273 int txgbe_set_queue_rate_limit(struct rte_eth_dev *dev, uint16_t queue_idx,
276 txgbe_ethertype_filter_lookup(struct txgbe_filter_info *filter_info,
281 for (i = 0; i < TXGBE_ETF_ID_MAX; i++) {
282 if (filter_info->ethertype_filters[i].ethertype == ethertype &&
283 (filter_info->ethertype_mask & (1 << i)))
290 txgbe_ethertype_filter_insert(struct txgbe_filter_info *filter_info,
291 struct txgbe_ethertype_filter *ethertype_filter)
295 for (i = 0; i < TXGBE_ETF_ID_MAX; i++) {
296 if (filter_info->ethertype_mask & (1 << i))
299 filter_info->ethertype_mask |= 1 << i;
300 filter_info->ethertype_filters[i].ethertype =
301 ethertype_filter->ethertype;
302 filter_info->ethertype_filters[i].etqf =
303 ethertype_filter->etqf;
304 filter_info->ethertype_filters[i].etqs =
305 ethertype_filter->etqs;
306 filter_info->ethertype_filters[i].conf =
307 ethertype_filter->conf;
310 return (i < TXGBE_ETF_ID_MAX ? i : -1);
314 #define TXGBE_LINK_DOWN_CHECK_TIMEOUT 4000 /* ms */
315 #define TXGBE_LINK_UP_CHECK_TIMEOUT 1000 /* ms */
316 #define TXGBE_VMDQ_NUM_UC_MAC 4096 /* Maximum nb. of UC MAC addr. */
319 * Default values for RX/TX configuration
321 #define TXGBE_DEFAULT_RX_FREE_THRESH 32
322 #define TXGBE_DEFAULT_RX_PTHRESH 8
323 #define TXGBE_DEFAULT_RX_HTHRESH 8
324 #define TXGBE_DEFAULT_RX_WTHRESH 0
326 #define TXGBE_DEFAULT_TX_FREE_THRESH 32
327 #define TXGBE_DEFAULT_TX_PTHRESH 32
328 #define TXGBE_DEFAULT_TX_HTHRESH 0
329 #define TXGBE_DEFAULT_TX_WTHRESH 0
331 /* store statistics names and its offset in stats structure */
332 struct rte_txgbe_xstats_name_off {
333 char name[RTE_ETH_XSTATS_NAME_SIZE];
337 const uint32_t *txgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev);
338 int txgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
339 struct rte_ether_addr *mc_addr_set,
340 uint32_t nb_mc_addr);
341 int txgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
342 struct rte_eth_rss_reta_entry64 *reta_conf,
344 int txgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
345 struct rte_eth_rss_reta_entry64 *reta_conf,
347 void txgbe_dev_setup_link_alarm_handler(void *param);
348 void txgbe_read_stats_registers(struct txgbe_hw *hw,
349 struct txgbe_hw_stats *hw_stats);
351 void txgbe_vlan_hw_filter_enable(struct rte_eth_dev *dev);
352 void txgbe_vlan_hw_filter_disable(struct rte_eth_dev *dev);
353 void txgbe_vlan_hw_strip_config(struct rte_eth_dev *dev);
354 void txgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev,
355 uint16_t queue, bool on);
356 void txgbe_config_vlan_strip_on_all_queues(struct rte_eth_dev *dev,
359 #endif /* _TXGBE_ETHDEV_H_ */