1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2015-2020
5 #ifndef _TXGBE_ETHDEV_H_
6 #define _TXGBE_ETHDEV_H_
10 #include "base/txgbe.h"
11 #include "txgbe_ptypes.h"
12 #ifdef RTE_LIB_SECURITY
13 #include "txgbe_ipsec.h"
16 #include <rte_flow_driver.h>
18 #include <rte_ethdev.h>
19 #include <rte_ethdev_core.h>
21 #include <rte_hash_crc.h>
22 #include <rte_bus_pci.h>
23 #include <rte_tm_driver.h>
25 /* need update link, bit flag */
26 #define TXGBE_FLAG_NEED_LINK_UPDATE (uint32_t)(1 << 0)
27 #define TXGBE_FLAG_MAILBOX (uint32_t)(1 << 1)
28 #define TXGBE_FLAG_PHY_INTERRUPT (uint32_t)(1 << 2)
29 #define TXGBE_FLAG_MACSEC (uint32_t)(1 << 3)
30 #define TXGBE_FLAG_NEED_LINK_CONFIG (uint32_t)(1 << 4)
33 * Defines that were not part of txgbe_type.h as they are not used by the
36 #define TXGBE_VFTA_SIZE 128
37 #define TXGBE_VLAN_TAG_SIZE 4
38 #define TXGBE_HKEY_MAX_INDEX 10
39 /*Default value of Max Rx Queue*/
40 #define TXGBE_MAX_RX_QUEUE_NUM 128
41 #define TXGBE_VMDQ_DCB_NB_QUEUES TXGBE_MAX_RX_QUEUE_NUM
44 #define NBBY 8 /* number of bits in a byte */
46 #define TXGBE_HWSTRIP_BITMAP_SIZE \
47 (TXGBE_MAX_RX_QUEUE_NUM / (sizeof(uint32_t) * NBBY))
49 #define TXGBE_QUEUE_ITR_INTERVAL_DEFAULT 500 /* 500us */
51 #define TXGBE_MAX_QUEUE_NUM_PER_VF 8
53 #define TXGBE_5TUPLE_MAX_PRI 7
54 #define TXGBE_5TUPLE_MIN_PRI 1
56 #define TXGBE_RSS_OFFLOAD_ALL ( \
58 ETH_RSS_NONFRAG_IPV4_TCP | \
59 ETH_RSS_NONFRAG_IPV4_UDP | \
61 ETH_RSS_NONFRAG_IPV6_TCP | \
62 ETH_RSS_NONFRAG_IPV6_UDP | \
64 ETH_RSS_IPV6_TCP_EX | \
67 #define TXGBE_MISC_VEC_ID RTE_INTR_VEC_ZERO_OFFSET
68 #define TXGBE_RX_VEC_START RTE_INTR_VEC_RXTX_OFFSET
70 #define TXGBE_MAX_FDIR_FILTER_NUM (1024 * 32)
71 #define TXGBE_MAX_L2_TN_FILTER_NUM 128
74 * Information about the fdir mode.
76 struct txgbe_hw_fdir_mask {
77 uint16_t vlan_tci_mask;
78 uint32_t src_ipv4_mask;
79 uint32_t dst_ipv4_mask;
80 uint16_t src_ipv6_mask;
81 uint16_t dst_ipv6_mask;
82 uint16_t src_port_mask;
83 uint16_t dst_port_mask;
84 uint16_t flex_bytes_mask;
85 uint8_t mac_addr_byte_mask;
86 uint32_t tunnel_id_mask;
87 uint8_t tunnel_type_mask;
90 struct txgbe_fdir_filter {
91 TAILQ_ENTRY(txgbe_fdir_filter) entries;
92 struct txgbe_atr_input input; /* key of fdir filter*/
93 uint32_t fdirflags; /* drop or forward */
94 uint32_t fdirhash; /* hash value for fdir */
95 uint8_t queue; /* assigned rx queue */
98 /* list of fdir filters */
99 TAILQ_HEAD(txgbe_fdir_filter_list, txgbe_fdir_filter);
101 struct txgbe_fdir_rule {
102 struct txgbe_hw_fdir_mask mask;
103 struct txgbe_atr_input input; /* key of fdir filter */
104 bool b_spec; /* If TRUE, input, fdirflags, queue have meaning. */
105 bool b_mask; /* If TRUE, mask has meaning. */
106 enum rte_fdir_mode mode; /* IP, MAC VLAN, Tunnel */
107 uint32_t fdirflags; /* drop or forward */
108 uint32_t soft_id; /* an unique value for this rule */
109 uint8_t queue; /* assigned rx queue */
110 uint8_t flex_bytes_offset;
113 struct txgbe_hw_fdir_info {
114 struct txgbe_hw_fdir_mask mask;
115 uint8_t flex_bytes_offset;
124 struct txgbe_fdir_filter_list fdir_list; /* filter list*/
125 /* store the pointers of the filters, index is the hash value. */
126 struct txgbe_fdir_filter **hash_map;
127 struct rte_hash *hash_handle; /* cuckoo hash handler */
128 bool mask_added; /* If already got mask from consistent filter */
131 struct txgbe_rte_flow_rss_conf {
132 struct rte_flow_action_rss conf; /**< RSS parameters. */
133 uint8_t key[TXGBE_HKEY_MAX_INDEX * sizeof(uint32_t)]; /* Hash key. */
134 uint16_t queue[TXGBE_MAX_RX_QUEUE_NUM]; /**< Queues indices to use. */
137 /* structure for interrupt relative data */
138 struct txgbe_interrupt {
141 /* to save original mask during delayed handler */
142 uint32_t mask_misc_orig;
146 #define TXGBE_NB_STAT_MAPPING 32
147 #define QSM_REG_NB_BITS_PER_QMAP_FIELD 8
148 #define NB_QMAP_FIELDS_PER_QSM_REG 4
149 #define QMAP_FIELD_RESERVED_BITS_MASK 0x0f
150 struct txgbe_stat_mappings {
151 uint32_t tqsm[TXGBE_NB_STAT_MAPPING];
152 uint32_t rqsm[TXGBE_NB_STAT_MAPPING];
156 uint32_t vfta[TXGBE_VFTA_SIZE];
159 struct txgbe_hwstrip {
160 uint32_t bitmap[TXGBE_HWSTRIP_BITMAP_SIZE];
164 * VF data which used by PF host only
166 #define TXGBE_MAX_VF_MC_ENTRIES 30
168 struct txgbe_uta_info {
169 uint8_t uc_filter_type;
171 uint32_t uta_shadow[TXGBE_MAX_UTA];
174 #define TXGBE_MAX_MIRROR_RULES 4 /* Maximum nb. of mirror rules. */
176 struct txgbe_mirror_info {
177 struct rte_eth_mirror_conf mr_conf[TXGBE_MAX_MIRROR_RULES];
178 /* store PF mirror rules configuration */
181 struct txgbe_vf_info {
182 uint8_t vf_mac_addresses[RTE_ETHER_ADDR_LEN];
183 uint16_t vf_mc_hashes[TXGBE_MAX_VF_MC_ENTRIES];
184 uint16_t num_vf_mc_hashes;
186 uint16_t tx_rate[TXGBE_MAX_QUEUE_NUM_PER_VF];
189 uint16_t switch_domain_id;
194 TAILQ_HEAD(txgbe_5tuple_filter_list, txgbe_5tuple_filter);
196 struct txgbe_5tuple_filter_info {
201 enum txgbe_5tuple_protocol proto; /* l4 protocol. */
202 uint8_t priority; /* seven levels (001b-111b), 111b is highest,
203 * used when more than one filter matches.
205 uint8_t dst_ip_mask:1, /* if mask is 1b, do not compare dst ip. */
206 src_ip_mask:1, /* if mask is 1b, do not compare src ip. */
207 dst_port_mask:1, /* if mask is 1b, do not compare dst port. */
208 src_port_mask:1, /* if mask is 1b, do not compare src port. */
209 proto_mask:1; /* if mask is 1b, do not compare protocol. */
212 /* 5tuple filter structure */
213 struct txgbe_5tuple_filter {
214 TAILQ_ENTRY(txgbe_5tuple_filter) entries;
215 uint16_t index; /* the index of 5tuple filter */
216 struct txgbe_5tuple_filter_info filter_info;
217 uint16_t queue; /* rx queue assigned to */
220 #define TXGBE_5TUPLE_ARRAY_SIZE \
221 (RTE_ALIGN(TXGBE_MAX_FTQF_FILTERS, (sizeof(uint32_t) * NBBY)) / \
222 (sizeof(uint32_t) * NBBY))
224 struct txgbe_ethertype_filter {
229 * If this filter is added by configuration,
230 * it should not be removed.
236 * Structure to store filters' info.
238 struct txgbe_filter_info {
239 uint8_t ethertype_mask; /* Bit mask for every used ethertype filter */
240 /* store used ethertype filters*/
241 struct txgbe_ethertype_filter ethertype_filters[TXGBE_ETF_ID_MAX];
242 /* Bit mask for every used 5tuple filter */
243 uint32_t fivetuple_mask[TXGBE_5TUPLE_ARRAY_SIZE];
244 struct txgbe_5tuple_filter_list fivetuple_list;
245 /* store the SYN filter info */
247 /* store the rss filter info */
248 struct txgbe_rte_flow_rss_conf rss_info;
251 struct txgbe_l2_tn_key {
252 enum rte_eth_tunnel_type l2_tn_type;
256 struct txgbe_l2_tn_filter {
257 TAILQ_ENTRY(txgbe_l2_tn_filter) entries;
258 struct txgbe_l2_tn_key key;
262 TAILQ_HEAD(txgbe_l2_tn_filter_list, txgbe_l2_tn_filter);
264 struct txgbe_l2_tn_info {
265 struct txgbe_l2_tn_filter_list l2_tn_list;
266 struct txgbe_l2_tn_filter **hash_map;
267 struct rte_hash *hash_handle;
268 bool e_tag_en; /* e-tag enabled */
269 bool e_tag_fwd_en; /* e-tag based forwarding enabled */
270 uint16_t e_tag_ether_type; /* ether type for e-tag */
274 enum rte_filter_type filter_type;
278 /* The configuration of bandwidth */
279 struct txgbe_bw_conf {
280 uint8_t tc_num; /* Number of TCs. */
283 /* Struct to store Traffic Manager shaper profile. */
284 struct txgbe_tm_shaper_profile {
285 TAILQ_ENTRY(txgbe_tm_shaper_profile) node;
286 uint32_t shaper_profile_id;
287 uint32_t reference_count;
288 struct rte_tm_shaper_params profile;
291 TAILQ_HEAD(txgbe_shaper_profile_list, txgbe_tm_shaper_profile);
293 /* node type of Traffic Manager */
294 enum txgbe_tm_node_type {
295 TXGBE_TM_NODE_TYPE_PORT,
296 TXGBE_TM_NODE_TYPE_TC,
297 TXGBE_TM_NODE_TYPE_QUEUE,
298 TXGBE_TM_NODE_TYPE_MAX,
301 /* Struct to store Traffic Manager node configuration. */
302 struct txgbe_tm_node {
303 TAILQ_ENTRY(txgbe_tm_node) node;
307 uint32_t reference_count;
309 struct txgbe_tm_node *parent;
310 struct txgbe_tm_shaper_profile *shaper_profile;
311 struct rte_tm_node_params params;
314 TAILQ_HEAD(txgbe_tm_node_list, txgbe_tm_node);
316 /* The configuration of Traffic Manager */
317 struct txgbe_tm_conf {
318 struct txgbe_shaper_profile_list shaper_profile_list;
319 struct txgbe_tm_node *root; /* root node - port */
320 struct txgbe_tm_node_list tc_list; /* node list for all the TCs */
321 struct txgbe_tm_node_list queue_list; /* node list for all the queues */
323 * The number of added TC nodes.
324 * It should be no more than the TC number of this port.
328 * The number of added queue nodes.
329 * It should be no more than the queue number of this port.
331 uint32_t nb_queue_node;
333 * This flag is used to check if APP can change the TM node
335 * When it's true, means the configuration is applied to HW,
336 * APP should not change the configuration.
337 * As we don't support on-the-fly configuration, when starting
338 * the port, APP should call the hierarchy_commit API to set this
339 * flag to true. When stopping the port, this flag should be set
346 * Structure to store private data for each driver instance (for each port).
348 struct txgbe_adapter {
350 struct txgbe_hw_stats stats;
351 struct txgbe_hw_fdir_info fdir;
352 struct txgbe_interrupt intr;
353 struct txgbe_stat_mappings stat_mappings;
354 struct txgbe_vfta shadow_vfta;
355 struct txgbe_hwstrip hwstrip;
356 struct txgbe_dcb_config dcb_config;
357 struct txgbe_mirror_info mr_data;
358 struct txgbe_vf_info *vfdata;
359 struct txgbe_uta_info uta_info;
360 struct txgbe_filter_info filter;
361 struct txgbe_l2_tn_info l2_tn;
362 struct txgbe_bw_conf bw_conf;
363 #ifdef RTE_LIB_SECURITY
364 struct txgbe_ipsec ipsec;
366 bool rx_bulk_alloc_allowed;
367 struct rte_timecounter systime_tc;
368 struct rte_timecounter rx_tstamp_tc;
369 struct rte_timecounter tx_tstamp_tc;
370 struct txgbe_tm_conf tm_conf;
372 /* For RSS reta table update */
373 uint8_t rss_reta_updated;
376 #define TXGBE_DEV_ADAPTER(dev) \
377 ((struct txgbe_adapter *)(dev)->data->dev_private)
379 #define TXGBE_DEV_HW(dev) \
380 (&((struct txgbe_adapter *)(dev)->data->dev_private)->hw)
382 #define TXGBE_DEV_STATS(dev) \
383 (&((struct txgbe_adapter *)(dev)->data->dev_private)->stats)
385 #define TXGBE_DEV_INTR(dev) \
386 (&((struct txgbe_adapter *)(dev)->data->dev_private)->intr)
388 #define TXGBE_DEV_FDIR(dev) \
389 (&((struct txgbe_adapter *)(dev)->data->dev_private)->fdir)
391 #define TXGBE_DEV_STAT_MAPPINGS(dev) \
392 (&((struct txgbe_adapter *)(dev)->data->dev_private)->stat_mappings)
394 #define TXGBE_DEV_VFTA(dev) \
395 (&((struct txgbe_adapter *)(dev)->data->dev_private)->shadow_vfta)
397 #define TXGBE_DEV_HWSTRIP(dev) \
398 (&((struct txgbe_adapter *)(dev)->data->dev_private)->hwstrip)
400 #define TXGBE_DEV_DCB_CONFIG(dev) \
401 (&((struct txgbe_adapter *)(dev)->data->dev_private)->dcb_config)
403 #define TXGBE_DEV_VFDATA(dev) \
404 (&((struct txgbe_adapter *)(dev)->data->dev_private)->vfdata)
406 #define TXGBE_DEV_MR_INFO(dev) \
407 (&((struct txgbe_adapter *)(dev)->data->dev_private)->mr_data)
409 #define TXGBE_DEV_UTA_INFO(dev) \
410 (&((struct txgbe_adapter *)(dev)->data->dev_private)->uta_info)
412 #define TXGBE_DEV_FILTER(dev) \
413 (&((struct txgbe_adapter *)(dev)->data->dev_private)->filter)
415 #define TXGBE_DEV_L2_TN(dev) \
416 (&((struct txgbe_adapter *)(dev)->data->dev_private)->l2_tn)
418 #define TXGBE_DEV_BW_CONF(dev) \
419 (&((struct txgbe_adapter *)(dev)->data->dev_private)->bw_conf)
421 #define TXGBE_DEV_TM_CONF(dev) \
422 (&((struct txgbe_adapter *)(dev)->data->dev_private)->tm_conf)
424 #define TXGBE_DEV_IPSEC(dev) \
425 (&((struct txgbe_adapter *)(dev)->data->dev_private)->ipsec)
428 * RX/TX function prototypes
430 void txgbe_dev_clear_queues(struct rte_eth_dev *dev);
432 void txgbe_dev_free_queues(struct rte_eth_dev *dev);
434 void txgbe_dev_rx_queue_release(void *rxq);
436 void txgbe_dev_tx_queue_release(void *txq);
438 int txgbe_dev_rx_queue_setup(struct rte_eth_dev *dev, uint16_t rx_queue_id,
439 uint16_t nb_rx_desc, unsigned int socket_id,
440 const struct rte_eth_rxconf *rx_conf,
441 struct rte_mempool *mb_pool);
443 int txgbe_dev_tx_queue_setup(struct rte_eth_dev *dev, uint16_t tx_queue_id,
444 uint16_t nb_tx_desc, unsigned int socket_id,
445 const struct rte_eth_txconf *tx_conf);
447 uint32_t txgbe_dev_rx_queue_count(struct rte_eth_dev *dev,
448 uint16_t rx_queue_id);
450 int txgbe_dev_rx_descriptor_status(void *rx_queue, uint16_t offset);
451 int txgbe_dev_tx_descriptor_status(void *tx_queue, uint16_t offset);
453 int txgbe_dev_rx_init(struct rte_eth_dev *dev);
455 void txgbe_dev_tx_init(struct rte_eth_dev *dev);
457 int txgbe_dev_rxtx_start(struct rte_eth_dev *dev);
459 void txgbe_dev_save_rx_queue(struct txgbe_hw *hw, uint16_t rx_queue_id);
460 void txgbe_dev_store_rx_queue(struct txgbe_hw *hw, uint16_t rx_queue_id);
461 void txgbe_dev_save_tx_queue(struct txgbe_hw *hw, uint16_t tx_queue_id);
462 void txgbe_dev_store_tx_queue(struct txgbe_hw *hw, uint16_t tx_queue_id);
464 int txgbe_dev_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id);
466 int txgbe_dev_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id);
468 int txgbe_dev_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id);
470 int txgbe_dev_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id);
472 void txgbe_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
473 struct rte_eth_rxq_info *qinfo);
475 void txgbe_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
476 struct rte_eth_txq_info *qinfo);
478 uint16_t txgbe_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
481 uint16_t txgbe_recv_pkts_bulk_alloc(void *rx_queue, struct rte_mbuf **rx_pkts,
484 uint16_t txgbe_recv_pkts_lro_single_alloc(void *rx_queue,
485 struct rte_mbuf **rx_pkts, uint16_t nb_pkts);
486 uint16_t txgbe_recv_pkts_lro_bulk_alloc(void *rx_queue,
487 struct rte_mbuf **rx_pkts, uint16_t nb_pkts);
489 uint16_t txgbe_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
492 uint16_t txgbe_xmit_pkts_simple(void *tx_queue, struct rte_mbuf **tx_pkts,
495 uint16_t txgbe_prep_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
498 int txgbe_dev_rss_hash_update(struct rte_eth_dev *dev,
499 struct rte_eth_rss_conf *rss_conf);
501 int txgbe_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
502 struct rte_eth_rss_conf *rss_conf);
504 bool txgbe_rss_update_sp(enum txgbe_mac_type mac_type);
506 int txgbe_add_del_ntuple_filter(struct rte_eth_dev *dev,
507 struct rte_eth_ntuple_filter *filter,
509 int txgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
510 struct rte_eth_ethertype_filter *filter,
512 int txgbe_syn_filter_set(struct rte_eth_dev *dev,
513 struct rte_eth_syn_filter *filter,
517 * l2 tunnel configuration.
519 struct txgbe_l2_tunnel_conf {
520 enum rte_eth_tunnel_type l2_tunnel_type;
521 uint16_t ether_type; /* ether type in l2 header */
522 uint32_t tunnel_id; /* port tag id for e-tag */
523 uint16_t vf_id; /* VF id for tag insertion */
524 uint32_t pool; /* destination pool for tag based forwarding */
528 txgbe_dev_l2_tunnel_filter_add(struct rte_eth_dev *dev,
529 struct txgbe_l2_tunnel_conf *l2_tunnel,
532 txgbe_dev_l2_tunnel_filter_del(struct rte_eth_dev *dev,
533 struct txgbe_l2_tunnel_conf *l2_tunnel);
534 void txgbe_filterlist_init(void);
535 void txgbe_filterlist_flush(void);
537 void txgbe_set_ivar_map(struct txgbe_hw *hw, int8_t direction,
538 uint8_t queue, uint8_t msix_vector);
541 * Flow director function prototypes
543 int txgbe_fdir_configure(struct rte_eth_dev *dev);
544 int txgbe_fdir_set_input_mask(struct rte_eth_dev *dev);
545 int txgbe_fdir_set_flexbytes_offset(struct rte_eth_dev *dev,
547 int txgbe_fdir_filter_program(struct rte_eth_dev *dev,
548 struct txgbe_fdir_rule *rule,
549 bool del, bool update);
551 void txgbe_configure_pb(struct rte_eth_dev *dev);
552 void txgbe_configure_port(struct rte_eth_dev *dev);
553 void txgbe_configure_dcb(struct rte_eth_dev *dev);
556 txgbe_dev_link_update_share(struct rte_eth_dev *dev,
557 int wait_to_complete);
558 int txgbe_pf_host_init(struct rte_eth_dev *eth_dev);
560 void txgbe_pf_host_uninit(struct rte_eth_dev *eth_dev);
562 void txgbe_pf_mbx_process(struct rte_eth_dev *eth_dev);
564 int txgbe_pf_host_configure(struct rte_eth_dev *eth_dev);
566 uint32_t txgbe_convert_vm_rx_mask_to_val(uint16_t rx_mask, uint32_t orig_val);
568 void txgbe_fdir_filter_restore(struct rte_eth_dev *dev);
569 int txgbe_clear_all_fdir_filter(struct rte_eth_dev *dev);
571 extern const struct rte_flow_ops txgbe_flow_ops;
573 void txgbe_clear_all_ethertype_filter(struct rte_eth_dev *dev);
574 void txgbe_clear_all_ntuple_filter(struct rte_eth_dev *dev);
575 void txgbe_clear_syn_filter(struct rte_eth_dev *dev);
576 int txgbe_clear_all_l2_tn_filter(struct rte_eth_dev *dev);
578 int txgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
579 uint16_t tx_rate, uint64_t q_msk);
580 int txgbe_tm_ops_get(struct rte_eth_dev *dev, void *ops);
581 void txgbe_tm_conf_init(struct rte_eth_dev *dev);
582 void txgbe_tm_conf_uninit(struct rte_eth_dev *dev);
583 int txgbe_set_queue_rate_limit(struct rte_eth_dev *dev, uint16_t queue_idx,
585 int txgbe_rss_conf_init(struct txgbe_rte_flow_rss_conf *out,
586 const struct rte_flow_action_rss *in);
587 int txgbe_action_rss_same(const struct rte_flow_action_rss *comp,
588 const struct rte_flow_action_rss *with);
589 int txgbe_config_rss_filter(struct rte_eth_dev *dev,
590 struct txgbe_rte_flow_rss_conf *conf, bool add);
593 txgbe_ethertype_filter_lookup(struct txgbe_filter_info *filter_info,
598 for (i = 0; i < TXGBE_ETF_ID_MAX; i++) {
599 if (filter_info->ethertype_filters[i].ethertype == ethertype &&
600 (filter_info->ethertype_mask & (1 << i)))
607 txgbe_ethertype_filter_insert(struct txgbe_filter_info *filter_info,
608 struct txgbe_ethertype_filter *ethertype_filter)
612 for (i = 0; i < TXGBE_ETF_ID_MAX; i++) {
613 if (filter_info->ethertype_mask & (1 << i))
616 filter_info->ethertype_mask |= 1 << i;
617 filter_info->ethertype_filters[i].ethertype =
618 ethertype_filter->ethertype;
619 filter_info->ethertype_filters[i].etqf =
620 ethertype_filter->etqf;
621 filter_info->ethertype_filters[i].etqs =
622 ethertype_filter->etqs;
623 filter_info->ethertype_filters[i].conf =
624 ethertype_filter->conf;
627 return (i < TXGBE_ETF_ID_MAX ? i : -1);
631 txgbe_ethertype_filter_remove(struct txgbe_filter_info *filter_info,
634 if (idx >= TXGBE_ETF_ID_MAX)
636 filter_info->ethertype_mask &= ~(1 << idx);
637 filter_info->ethertype_filters[idx].ethertype = 0;
638 filter_info->ethertype_filters[idx].etqf = 0;
639 filter_info->ethertype_filters[idx].etqs = 0;
640 filter_info->ethertype_filters[idx].etqs = FALSE;
644 #ifdef RTE_LIB_SECURITY
645 int txgbe_ipsec_ctx_create(struct rte_eth_dev *dev);
648 /* High threshold controlling when to start sending XOFF frames. */
649 #define TXGBE_FC_XOFF_HITH 128 /*KB*/
650 /* Low threshold controlling when to start sending XON frames. */
651 #define TXGBE_FC_XON_LOTH 64 /*KB*/
653 /* Timer value included in XOFF frames. */
654 #define TXGBE_FC_PAUSE_TIME 0x680
656 #define TXGBE_LINK_DOWN_CHECK_TIMEOUT 4000 /* ms */
657 #define TXGBE_LINK_UP_CHECK_TIMEOUT 1000 /* ms */
658 #define TXGBE_VMDQ_NUM_UC_MAC 4096 /* Maximum nb. of UC MAC addr. */
661 * Default values for RX/TX configuration
663 #define TXGBE_DEFAULT_RX_FREE_THRESH 32
664 #define TXGBE_DEFAULT_RX_PTHRESH 8
665 #define TXGBE_DEFAULT_RX_HTHRESH 8
666 #define TXGBE_DEFAULT_RX_WTHRESH 0
668 #define TXGBE_DEFAULT_TX_FREE_THRESH 32
669 #define TXGBE_DEFAULT_TX_PTHRESH 32
670 #define TXGBE_DEFAULT_TX_HTHRESH 0
671 #define TXGBE_DEFAULT_TX_WTHRESH 0
673 /* Additional timesync values. */
674 #define NSEC_PER_SEC 1000000000L
675 #define TXGBE_INCVAL_10GB 0xCCCCCC
676 #define TXGBE_INCVAL_1GB 0x800000
677 #define TXGBE_INCVAL_100 0xA00000
678 #define TXGBE_INCVAL_10 0xC7F380
679 #define TXGBE_INCVAL_FPGA 0x800000
680 #define TXGBE_INCVAL_SHIFT_10GB 20
681 #define TXGBE_INCVAL_SHIFT_1GB 18
682 #define TXGBE_INCVAL_SHIFT_100 15
683 #define TXGBE_INCVAL_SHIFT_10 12
684 #define TXGBE_INCVAL_SHIFT_FPGA 17
686 #define TXGBE_CYCLECOUNTER_MASK 0xffffffffffffffffULL
688 /* store statistics names and its offset in stats structure */
689 struct rte_txgbe_xstats_name_off {
690 char name[RTE_ETH_XSTATS_NAME_SIZE];
694 const uint32_t *txgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev);
695 int txgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
696 struct rte_ether_addr *mc_addr_set,
697 uint32_t nb_mc_addr);
698 int txgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
699 struct rte_eth_rss_reta_entry64 *reta_conf,
701 int txgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
702 struct rte_eth_rss_reta_entry64 *reta_conf,
704 void txgbe_dev_setup_link_alarm_handler(void *param);
705 void txgbe_read_stats_registers(struct txgbe_hw *hw,
706 struct txgbe_hw_stats *hw_stats);
708 void txgbe_vlan_hw_filter_enable(struct rte_eth_dev *dev);
709 void txgbe_vlan_hw_filter_disable(struct rte_eth_dev *dev);
710 void txgbe_vlan_hw_strip_config(struct rte_eth_dev *dev);
711 void txgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev,
712 uint16_t queue, bool on);
713 void txgbe_config_vlan_strip_on_all_queues(struct rte_eth_dev *dev,
716 #endif /* _TXGBE_ETHDEV_H_ */