1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2015-2020 Beijing WangXun Technology Co., Ltd.
3 * Copyright(c) 2010-2017 Intel Corporation
6 #ifndef _TXGBE_ETHDEV_H_
7 #define _TXGBE_ETHDEV_H_
11 #include "base/txgbe.h"
12 #include "txgbe_ptypes.h"
13 #ifdef RTE_LIB_SECURITY
14 #include "txgbe_ipsec.h"
17 #include <rte_flow_driver.h>
19 #include <rte_ethdev.h>
20 #include <rte_ethdev_core.h>
22 #include <rte_hash_crc.h>
23 #include <rte_bus_pci.h>
24 #include <rte_tm_driver.h>
26 /* need update link, bit flag */
27 #define TXGBE_FLAG_NEED_LINK_UPDATE (uint32_t)(1 << 0)
28 #define TXGBE_FLAG_MAILBOX (uint32_t)(1 << 1)
29 #define TXGBE_FLAG_PHY_INTERRUPT (uint32_t)(1 << 2)
30 #define TXGBE_FLAG_MACSEC (uint32_t)(1 << 3)
31 #define TXGBE_FLAG_NEED_LINK_CONFIG (uint32_t)(1 << 4)
32 #define TXGBE_FLAG_NEED_AN_CONFIG (uint32_t)(1 << 5)
35 * Defines that were not part of txgbe_type.h as they are not used by the
38 #define TXGBE_VFTA_SIZE 128
39 #define TXGBE_VLAN_TAG_SIZE 4
40 #define TXGBE_HKEY_MAX_INDEX 10
41 /*Default value of Max Rx Queue*/
42 #define TXGBE_MAX_RX_QUEUE_NUM 128
43 #define TXGBE_VMDQ_DCB_NB_QUEUES TXGBE_MAX_RX_QUEUE_NUM
46 #define NBBY 8 /* number of bits in a byte */
48 #define TXGBE_HWSTRIP_BITMAP_SIZE \
49 (TXGBE_MAX_RX_QUEUE_NUM / (sizeof(uint32_t) * NBBY))
51 #define TXGBE_QUEUE_ITR_INTERVAL_DEFAULT 500 /* 500us */
53 #define TXGBE_MAX_QUEUE_NUM_PER_VF 8
55 #define TXGBE_5TUPLE_MAX_PRI 7
56 #define TXGBE_5TUPLE_MIN_PRI 1
58 #define TXGBE_RSS_OFFLOAD_ALL ( \
60 ETH_RSS_NONFRAG_IPV4_TCP | \
61 ETH_RSS_NONFRAG_IPV4_UDP | \
63 ETH_RSS_NONFRAG_IPV6_TCP | \
64 ETH_RSS_NONFRAG_IPV6_UDP | \
66 ETH_RSS_IPV6_TCP_EX | \
69 #define TXGBE_MISC_VEC_ID RTE_INTR_VEC_ZERO_OFFSET
70 #define TXGBE_RX_VEC_START RTE_INTR_VEC_RXTX_OFFSET
72 #define TXGBE_MAX_FDIR_FILTER_NUM (1024 * 32)
73 #define TXGBE_MAX_L2_TN_FILTER_NUM 128
76 * Information about the fdir mode.
78 struct txgbe_hw_fdir_mask {
79 uint16_t vlan_tci_mask;
80 uint32_t src_ipv4_mask;
81 uint32_t dst_ipv4_mask;
82 uint16_t src_ipv6_mask;
83 uint16_t dst_ipv6_mask;
84 uint16_t src_port_mask;
85 uint16_t dst_port_mask;
86 uint16_t flex_bytes_mask;
87 uint8_t mac_addr_byte_mask;
88 uint32_t tunnel_id_mask;
89 uint8_t tunnel_type_mask;
92 struct txgbe_fdir_filter {
93 TAILQ_ENTRY(txgbe_fdir_filter) entries;
94 struct txgbe_atr_input input; /* key of fdir filter*/
95 uint32_t fdirflags; /* drop or forward */
96 uint32_t fdirhash; /* hash value for fdir */
97 uint8_t queue; /* assigned rx queue */
100 /* list of fdir filters */
101 TAILQ_HEAD(txgbe_fdir_filter_list, txgbe_fdir_filter);
103 struct txgbe_fdir_rule {
104 struct txgbe_hw_fdir_mask mask;
105 struct txgbe_atr_input input; /* key of fdir filter */
106 bool b_spec; /* If TRUE, input, fdirflags, queue have meaning. */
107 bool b_mask; /* If TRUE, mask has meaning. */
108 enum rte_fdir_mode mode; /* IP, MAC VLAN, Tunnel */
109 uint32_t fdirflags; /* drop or forward */
110 uint32_t soft_id; /* an unique value for this rule */
111 uint8_t queue; /* assigned rx queue */
112 uint8_t flex_bytes_offset;
115 struct txgbe_hw_fdir_info {
116 struct txgbe_hw_fdir_mask mask;
117 uint8_t flex_bytes_offset;
126 struct txgbe_fdir_filter_list fdir_list; /* filter list*/
127 /* store the pointers of the filters, index is the hash value. */
128 struct txgbe_fdir_filter **hash_map;
129 struct rte_hash *hash_handle; /* cuckoo hash handler */
130 bool mask_added; /* If already got mask from consistent filter */
133 struct txgbe_rte_flow_rss_conf {
134 struct rte_flow_action_rss conf; /**< RSS parameters. */
135 uint8_t key[TXGBE_HKEY_MAX_INDEX * sizeof(uint32_t)]; /* Hash key. */
136 uint16_t queue[TXGBE_MAX_RX_QUEUE_NUM]; /**< Queues indices to use. */
139 /* structure for interrupt relative data */
140 struct txgbe_interrupt {
143 uint32_t mask_misc_orig; /* save mask during delayed handler */
145 uint64_t mask_orig; /* save mask during delayed handler */
148 #define TXGBE_NB_STAT_MAPPING 32
149 #define QSM_REG_NB_BITS_PER_QMAP_FIELD 8
150 #define NB_QMAP_FIELDS_PER_QSM_REG 4
151 #define QMAP_FIELD_RESERVED_BITS_MASK 0x0f
152 struct txgbe_stat_mappings {
153 uint32_t tqsm[TXGBE_NB_STAT_MAPPING];
154 uint32_t rqsm[TXGBE_NB_STAT_MAPPING];
158 uint32_t vfta[TXGBE_VFTA_SIZE];
161 struct txgbe_hwstrip {
162 uint32_t bitmap[TXGBE_HWSTRIP_BITMAP_SIZE];
166 * VF data which used by PF host only
168 #define TXGBE_MAX_VF_MC_ENTRIES 30
170 struct txgbe_uta_info {
171 uint8_t uc_filter_type;
173 uint32_t uta_shadow[TXGBE_MAX_UTA];
176 struct txgbe_vf_info {
177 uint8_t vf_mac_addresses[RTE_ETHER_ADDR_LEN];
178 uint16_t vf_mc_hashes[TXGBE_MAX_VF_MC_ENTRIES];
179 uint16_t num_vf_mc_hashes;
181 uint16_t tx_rate[TXGBE_MAX_QUEUE_NUM_PER_VF];
184 uint16_t switch_domain_id;
189 TAILQ_HEAD(txgbe_5tuple_filter_list, txgbe_5tuple_filter);
191 struct txgbe_5tuple_filter_info {
196 enum txgbe_5tuple_protocol proto; /* l4 protocol. */
197 uint8_t priority; /* seven levels (001b-111b), 111b is highest,
198 * used when more than one filter matches.
200 uint8_t dst_ip_mask:1, /* if mask is 1b, do not compare dst ip. */
201 src_ip_mask:1, /* if mask is 1b, do not compare src ip. */
202 dst_port_mask:1, /* if mask is 1b, do not compare dst port. */
203 src_port_mask:1, /* if mask is 1b, do not compare src port. */
204 proto_mask:1; /* if mask is 1b, do not compare protocol. */
207 /* 5tuple filter structure */
208 struct txgbe_5tuple_filter {
209 TAILQ_ENTRY(txgbe_5tuple_filter) entries;
210 uint16_t index; /* the index of 5tuple filter */
211 struct txgbe_5tuple_filter_info filter_info;
212 uint16_t queue; /* rx queue assigned to */
215 #define TXGBE_5TUPLE_ARRAY_SIZE \
216 (RTE_ALIGN(TXGBE_MAX_FTQF_FILTERS, (sizeof(uint32_t) * NBBY)) / \
217 (sizeof(uint32_t) * NBBY))
219 struct txgbe_ethertype_filter {
224 * If this filter is added by configuration,
225 * it should not be removed.
231 * Structure to store filters' info.
233 struct txgbe_filter_info {
234 uint8_t ethertype_mask; /* Bit mask for every used ethertype filter */
235 /* store used ethertype filters*/
236 struct txgbe_ethertype_filter ethertype_filters[TXGBE_ETF_ID_MAX];
237 /* Bit mask for every used 5tuple filter */
238 uint32_t fivetuple_mask[TXGBE_5TUPLE_ARRAY_SIZE];
239 struct txgbe_5tuple_filter_list fivetuple_list;
240 /* store the SYN filter info */
242 /* store the rss filter info */
243 struct txgbe_rte_flow_rss_conf rss_info;
246 struct txgbe_l2_tn_key {
247 enum rte_eth_tunnel_type l2_tn_type;
251 struct txgbe_l2_tn_filter {
252 TAILQ_ENTRY(txgbe_l2_tn_filter) entries;
253 struct txgbe_l2_tn_key key;
257 TAILQ_HEAD(txgbe_l2_tn_filter_list, txgbe_l2_tn_filter);
259 struct txgbe_l2_tn_info {
260 struct txgbe_l2_tn_filter_list l2_tn_list;
261 struct txgbe_l2_tn_filter **hash_map;
262 struct rte_hash *hash_handle;
263 bool e_tag_en; /* e-tag enabled */
264 bool e_tag_fwd_en; /* e-tag based forwarding enabled */
265 uint16_t e_tag_ether_type; /* ether type for e-tag */
269 enum rte_filter_type filter_type;
273 /* The configuration of bandwidth */
274 struct txgbe_bw_conf {
275 uint8_t tc_num; /* Number of TCs. */
278 /* Struct to store Traffic Manager shaper profile. */
279 struct txgbe_tm_shaper_profile {
280 TAILQ_ENTRY(txgbe_tm_shaper_profile) node;
281 uint32_t shaper_profile_id;
282 uint32_t reference_count;
283 struct rte_tm_shaper_params profile;
286 TAILQ_HEAD(txgbe_shaper_profile_list, txgbe_tm_shaper_profile);
288 /* node type of Traffic Manager */
289 enum txgbe_tm_node_type {
290 TXGBE_TM_NODE_TYPE_PORT,
291 TXGBE_TM_NODE_TYPE_TC,
292 TXGBE_TM_NODE_TYPE_QUEUE,
293 TXGBE_TM_NODE_TYPE_MAX,
296 /* Struct to store Traffic Manager node configuration. */
297 struct txgbe_tm_node {
298 TAILQ_ENTRY(txgbe_tm_node) node;
302 uint32_t reference_count;
304 struct txgbe_tm_node *parent;
305 struct txgbe_tm_shaper_profile *shaper_profile;
306 struct rte_tm_node_params params;
309 TAILQ_HEAD(txgbe_tm_node_list, txgbe_tm_node);
311 /* The configuration of Traffic Manager */
312 struct txgbe_tm_conf {
313 struct txgbe_shaper_profile_list shaper_profile_list;
314 struct txgbe_tm_node *root; /* root node - port */
315 struct txgbe_tm_node_list tc_list; /* node list for all the TCs */
316 struct txgbe_tm_node_list queue_list; /* node list for all the queues */
318 * The number of added TC nodes.
319 * It should be no more than the TC number of this port.
323 * The number of added queue nodes.
324 * It should be no more than the queue number of this port.
326 uint32_t nb_queue_node;
328 * This flag is used to check if APP can change the TM node
330 * When it's true, means the configuration is applied to HW,
331 * APP should not change the configuration.
332 * As we don't support on-the-fly configuration, when starting
333 * the port, APP should call the hierarchy_commit API to set this
334 * flag to true. When stopping the port, this flag should be set
341 * Structure to store private data for each driver instance (for each port).
343 struct txgbe_adapter {
345 struct txgbe_hw_stats stats;
346 struct txgbe_hw_fdir_info fdir;
347 struct txgbe_interrupt intr;
348 struct txgbe_stat_mappings stat_mappings;
349 struct txgbe_vfta shadow_vfta;
350 struct txgbe_hwstrip hwstrip;
351 struct txgbe_dcb_config dcb_config;
352 struct txgbe_vf_info *vfdata;
353 struct txgbe_uta_info uta_info;
354 struct txgbe_filter_info filter;
355 struct txgbe_l2_tn_info l2_tn;
356 struct txgbe_bw_conf bw_conf;
357 #ifdef RTE_LIB_SECURITY
358 struct txgbe_ipsec ipsec;
360 bool rx_bulk_alloc_allowed;
361 struct rte_timecounter systime_tc;
362 struct rte_timecounter rx_tstamp_tc;
363 struct rte_timecounter tx_tstamp_tc;
364 struct txgbe_tm_conf tm_conf;
366 /* For RSS reta table update */
367 uint8_t rss_reta_updated;
370 #define TXGBE_DEV_ADAPTER(dev) \
371 ((struct txgbe_adapter *)(dev)->data->dev_private)
373 #define TXGBE_DEV_HW(dev) \
374 (&((struct txgbe_adapter *)(dev)->data->dev_private)->hw)
376 #define TXGBE_DEV_STATS(dev) \
377 (&((struct txgbe_adapter *)(dev)->data->dev_private)->stats)
379 #define TXGBE_DEV_INTR(dev) \
380 (&((struct txgbe_adapter *)(dev)->data->dev_private)->intr)
382 #define TXGBE_DEV_FDIR(dev) \
383 (&((struct txgbe_adapter *)(dev)->data->dev_private)->fdir)
385 #define TXGBE_DEV_STAT_MAPPINGS(dev) \
386 (&((struct txgbe_adapter *)(dev)->data->dev_private)->stat_mappings)
388 #define TXGBE_DEV_VFTA(dev) \
389 (&((struct txgbe_adapter *)(dev)->data->dev_private)->shadow_vfta)
391 #define TXGBE_DEV_HWSTRIP(dev) \
392 (&((struct txgbe_adapter *)(dev)->data->dev_private)->hwstrip)
394 #define TXGBE_DEV_DCB_CONFIG(dev) \
395 (&((struct txgbe_adapter *)(dev)->data->dev_private)->dcb_config)
397 #define TXGBE_DEV_VFDATA(dev) \
398 (&((struct txgbe_adapter *)(dev)->data->dev_private)->vfdata)
400 #define TXGBE_DEV_MR_INFO(dev) \
401 (&((struct txgbe_adapter *)(dev)->data->dev_private)->mr_data)
403 #define TXGBE_DEV_UTA_INFO(dev) \
404 (&((struct txgbe_adapter *)(dev)->data->dev_private)->uta_info)
406 #define TXGBE_DEV_FILTER(dev) \
407 (&((struct txgbe_adapter *)(dev)->data->dev_private)->filter)
409 #define TXGBE_DEV_L2_TN(dev) \
410 (&((struct txgbe_adapter *)(dev)->data->dev_private)->l2_tn)
412 #define TXGBE_DEV_BW_CONF(dev) \
413 (&((struct txgbe_adapter *)(dev)->data->dev_private)->bw_conf)
415 #define TXGBE_DEV_TM_CONF(dev) \
416 (&((struct txgbe_adapter *)(dev)->data->dev_private)->tm_conf)
418 #define TXGBE_DEV_IPSEC(dev) \
419 (&((struct txgbe_adapter *)(dev)->data->dev_private)->ipsec)
422 * RX/TX function prototypes
424 void txgbe_dev_clear_queues(struct rte_eth_dev *dev);
426 void txgbe_dev_free_queues(struct rte_eth_dev *dev);
428 void txgbe_dev_rx_queue_release(struct rte_eth_dev *dev, uint16_t qid);
430 void txgbe_dev_tx_queue_release(struct rte_eth_dev *dev, uint16_t qid);
432 int txgbe_dev_rx_queue_setup(struct rte_eth_dev *dev, uint16_t rx_queue_id,
433 uint16_t nb_rx_desc, unsigned int socket_id,
434 const struct rte_eth_rxconf *rx_conf,
435 struct rte_mempool *mb_pool);
437 int txgbe_dev_tx_queue_setup(struct rte_eth_dev *dev, uint16_t tx_queue_id,
438 uint16_t nb_tx_desc, unsigned int socket_id,
439 const struct rte_eth_txconf *tx_conf);
441 uint32_t txgbe_dev_rx_queue_count(void *rx_queue);
443 int txgbe_dev_rx_descriptor_status(void *rx_queue, uint16_t offset);
444 int txgbe_dev_tx_descriptor_status(void *tx_queue, uint16_t offset);
446 int txgbe_dev_rx_init(struct rte_eth_dev *dev);
448 void txgbe_dev_tx_init(struct rte_eth_dev *dev);
450 int txgbe_dev_rxtx_start(struct rte_eth_dev *dev);
452 void txgbe_dev_save_rx_queue(struct txgbe_hw *hw, uint16_t rx_queue_id);
453 void txgbe_dev_store_rx_queue(struct txgbe_hw *hw, uint16_t rx_queue_id);
454 void txgbe_dev_save_tx_queue(struct txgbe_hw *hw, uint16_t tx_queue_id);
455 void txgbe_dev_store_tx_queue(struct txgbe_hw *hw, uint16_t tx_queue_id);
457 int txgbe_dev_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id);
459 int txgbe_dev_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id);
461 int txgbe_dev_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id);
463 int txgbe_dev_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id);
465 void txgbe_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
466 struct rte_eth_rxq_info *qinfo);
468 void txgbe_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
469 struct rte_eth_txq_info *qinfo);
471 int txgbevf_dev_rx_init(struct rte_eth_dev *dev);
473 void txgbevf_dev_tx_init(struct rte_eth_dev *dev);
475 void txgbevf_dev_rxtx_start(struct rte_eth_dev *dev);
477 uint16_t txgbe_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
480 uint16_t txgbe_recv_pkts_bulk_alloc(void *rx_queue, struct rte_mbuf **rx_pkts,
483 uint16_t txgbe_recv_pkts_lro_single_alloc(void *rx_queue,
484 struct rte_mbuf **rx_pkts, uint16_t nb_pkts);
485 uint16_t txgbe_recv_pkts_lro_bulk_alloc(void *rx_queue,
486 struct rte_mbuf **rx_pkts, uint16_t nb_pkts);
488 uint16_t txgbe_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
491 uint16_t txgbe_xmit_pkts_simple(void *tx_queue, struct rte_mbuf **tx_pkts,
494 uint16_t txgbe_prep_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
497 int txgbe_dev_rss_hash_update(struct rte_eth_dev *dev,
498 struct rte_eth_rss_conf *rss_conf);
500 int txgbe_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
501 struct rte_eth_rss_conf *rss_conf);
503 bool txgbe_rss_update_sp(enum txgbe_mac_type mac_type);
505 int txgbe_add_del_ntuple_filter(struct rte_eth_dev *dev,
506 struct rte_eth_ntuple_filter *filter,
508 int txgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
509 struct rte_eth_ethertype_filter *filter,
511 int txgbe_syn_filter_set(struct rte_eth_dev *dev,
512 struct rte_eth_syn_filter *filter,
516 * l2 tunnel configuration.
518 struct txgbe_l2_tunnel_conf {
519 enum rte_eth_tunnel_type l2_tunnel_type;
520 uint16_t ether_type; /* ether type in l2 header */
521 uint32_t tunnel_id; /* port tag id for e-tag */
522 uint16_t vf_id; /* VF id for tag insertion */
523 uint32_t pool; /* destination pool for tag based forwarding */
527 txgbe_dev_l2_tunnel_filter_add(struct rte_eth_dev *dev,
528 struct txgbe_l2_tunnel_conf *l2_tunnel,
531 txgbe_dev_l2_tunnel_filter_del(struct rte_eth_dev *dev,
532 struct txgbe_l2_tunnel_conf *l2_tunnel);
533 void txgbe_filterlist_init(void);
534 void txgbe_filterlist_flush(void);
536 void txgbe_set_ivar_map(struct txgbe_hw *hw, int8_t direction,
537 uint8_t queue, uint8_t msix_vector);
540 * Flow director function prototypes
542 int txgbe_fdir_configure(struct rte_eth_dev *dev);
543 int txgbe_fdir_set_input_mask(struct rte_eth_dev *dev);
544 int txgbe_fdir_set_flexbytes_offset(struct rte_eth_dev *dev,
546 int txgbe_fdir_filter_program(struct rte_eth_dev *dev,
547 struct txgbe_fdir_rule *rule,
548 bool del, bool update);
550 void txgbe_configure_pb(struct rte_eth_dev *dev);
551 void txgbe_configure_port(struct rte_eth_dev *dev);
552 void txgbe_configure_dcb(struct rte_eth_dev *dev);
555 txgbe_dev_link_update_share(struct rte_eth_dev *dev,
556 int wait_to_complete);
557 int txgbe_pf_host_init(struct rte_eth_dev *eth_dev);
559 void txgbe_pf_host_uninit(struct rte_eth_dev *eth_dev);
561 void txgbe_pf_mbx_process(struct rte_eth_dev *eth_dev);
563 int txgbe_pf_host_configure(struct rte_eth_dev *eth_dev);
565 uint32_t txgbe_convert_vm_rx_mask_to_val(uint16_t rx_mask, uint32_t orig_val);
567 void txgbe_fdir_filter_restore(struct rte_eth_dev *dev);
568 int txgbe_clear_all_fdir_filter(struct rte_eth_dev *dev);
570 extern const struct rte_flow_ops txgbe_flow_ops;
572 void txgbe_clear_all_ethertype_filter(struct rte_eth_dev *dev);
573 void txgbe_clear_all_ntuple_filter(struct rte_eth_dev *dev);
574 void txgbe_clear_syn_filter(struct rte_eth_dev *dev);
575 int txgbe_clear_all_l2_tn_filter(struct rte_eth_dev *dev);
577 int txgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
578 uint16_t tx_rate, uint64_t q_msk);
579 int txgbe_tm_ops_get(struct rte_eth_dev *dev, void *ops);
580 void txgbe_tm_conf_init(struct rte_eth_dev *dev);
581 void txgbe_tm_conf_uninit(struct rte_eth_dev *dev);
582 int txgbe_set_queue_rate_limit(struct rte_eth_dev *dev, uint16_t queue_idx,
584 int txgbe_rss_conf_init(struct txgbe_rte_flow_rss_conf *out,
585 const struct rte_flow_action_rss *in);
586 int txgbe_action_rss_same(const struct rte_flow_action_rss *comp,
587 const struct rte_flow_action_rss *with);
588 int txgbe_config_rss_filter(struct rte_eth_dev *dev,
589 struct txgbe_rte_flow_rss_conf *conf, bool add);
592 txgbe_ethertype_filter_lookup(struct txgbe_filter_info *filter_info,
597 for (i = 0; i < TXGBE_ETF_ID_MAX; i++) {
598 if (filter_info->ethertype_filters[i].ethertype == ethertype &&
599 (filter_info->ethertype_mask & (1 << i)))
606 txgbe_ethertype_filter_insert(struct txgbe_filter_info *filter_info,
607 struct txgbe_ethertype_filter *ethertype_filter)
611 for (i = 0; i < TXGBE_ETF_ID_MAX; i++) {
612 if (filter_info->ethertype_mask & (1 << i))
615 filter_info->ethertype_mask |= 1 << i;
616 filter_info->ethertype_filters[i].ethertype =
617 ethertype_filter->ethertype;
618 filter_info->ethertype_filters[i].etqf =
619 ethertype_filter->etqf;
620 filter_info->ethertype_filters[i].etqs =
621 ethertype_filter->etqs;
622 filter_info->ethertype_filters[i].conf =
623 ethertype_filter->conf;
626 return (i < TXGBE_ETF_ID_MAX ? i : -1);
630 txgbe_ethertype_filter_remove(struct txgbe_filter_info *filter_info,
633 if (idx >= TXGBE_ETF_ID_MAX)
635 filter_info->ethertype_mask &= ~(1 << idx);
636 filter_info->ethertype_filters[idx].ethertype = 0;
637 filter_info->ethertype_filters[idx].etqf = 0;
638 filter_info->ethertype_filters[idx].etqs = 0;
639 filter_info->ethertype_filters[idx].etqs = FALSE;
643 #ifdef RTE_LIB_SECURITY
644 int txgbe_ipsec_ctx_create(struct rte_eth_dev *dev);
647 /* High threshold controlling when to start sending XOFF frames. */
648 #define TXGBE_FC_XOFF_HITH 128 /*KB*/
649 /* Low threshold controlling when to start sending XON frames. */
650 #define TXGBE_FC_XON_LOTH 64 /*KB*/
652 /* Timer value included in XOFF frames. */
653 #define TXGBE_FC_PAUSE_TIME 0x680
655 #define TXGBE_LINK_DOWN_CHECK_TIMEOUT 4000 /* ms */
656 #define TXGBE_LINK_UP_CHECK_TIMEOUT 1000 /* ms */
657 #define TXGBE_VMDQ_NUM_UC_MAC 4096 /* Maximum nb. of UC MAC addr. */
660 * Default values for RX/TX configuration
662 #define TXGBE_DEFAULT_RX_FREE_THRESH 32
663 #define TXGBE_DEFAULT_RX_PTHRESH 8
664 #define TXGBE_DEFAULT_RX_HTHRESH 8
665 #define TXGBE_DEFAULT_RX_WTHRESH 0
667 #define TXGBE_DEFAULT_TX_FREE_THRESH 32
668 #define TXGBE_DEFAULT_TX_PTHRESH 32
669 #define TXGBE_DEFAULT_TX_HTHRESH 0
670 #define TXGBE_DEFAULT_TX_WTHRESH 0
672 /* Additional timesync values. */
673 #define NSEC_PER_SEC 1000000000L
674 #define TXGBE_INCVAL_10GB 0xCCCCCC
675 #define TXGBE_INCVAL_1GB 0x800000
676 #define TXGBE_INCVAL_100 0xA00000
677 #define TXGBE_INCVAL_10 0xC7F380
678 #define TXGBE_INCVAL_FPGA 0x800000
679 #define TXGBE_INCVAL_SHIFT_10GB 20
680 #define TXGBE_INCVAL_SHIFT_1GB 18
681 #define TXGBE_INCVAL_SHIFT_100 15
682 #define TXGBE_INCVAL_SHIFT_10 12
683 #define TXGBE_INCVAL_SHIFT_FPGA 17
685 #define TXGBE_CYCLECOUNTER_MASK 0xffffffffffffffffULL
687 /* store statistics names and its offset in stats structure */
688 struct rte_txgbe_xstats_name_off {
689 char name[RTE_ETH_XSTATS_NAME_SIZE];
693 const uint32_t *txgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev);
694 int txgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
695 struct rte_ether_addr *mc_addr_set,
696 uint32_t nb_mc_addr);
697 int txgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
698 struct rte_eth_rss_reta_entry64 *reta_conf,
700 int txgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
701 struct rte_eth_rss_reta_entry64 *reta_conf,
703 void txgbe_dev_setup_link_alarm_handler(void *param);
704 void txgbe_read_stats_registers(struct txgbe_hw *hw,
705 struct txgbe_hw_stats *hw_stats);
707 void txgbe_vlan_hw_filter_enable(struct rte_eth_dev *dev);
708 void txgbe_vlan_hw_filter_disable(struct rte_eth_dev *dev);
709 void txgbe_vlan_hw_strip_config(struct rte_eth_dev *dev);
710 void txgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev,
711 uint16_t queue, bool on);
712 void txgbe_config_vlan_strip_on_all_queues(struct rte_eth_dev *dev,
715 #endif /* _TXGBE_ETHDEV_H_ */