1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2015-2020
8 /*****************************************************************************
10 *****************************************************************************/
11 struct txgbe_rx_desc {
27 } qw0; /* also as r.pkt_addr */
42 } qw1; /* also as r.hdr_addr */
45 /* @txgbe_rx_desc.qw0 */
46 #define TXGBE_RXD_PKTADDR(rxd, v) \
47 (((volatile __le64 *)(rxd))[0] = cpu_to_le64(v))
49 /* @txgbe_rx_desc.qw1 */
50 #define TXGBE_RXD_HDRADDR(rxd, v) \
51 (((volatile __le64 *)(rxd))[1] = cpu_to_le64(v))
54 * Transmit Data Descriptor (TXGBE_TXD_TYP=DATA)
56 struct txgbe_tx_desc {
57 __le64 qw0; /* r.buffer_addr , w.reserved */
58 __le32 dw2; /* r.cmd_type_len, w.nxtseq_seed */
59 __le32 dw3; /* r.olinfo_status, w.status */
62 #define RTE_PMD_TXGBE_TX_MAX_BURST 32
63 #define RTE_PMD_TXGBE_RX_MAX_BURST 32
65 #define RX_RING_SZ ((TXGBE_RING_DESC_MAX + RTE_PMD_TXGBE_RX_MAX_BURST) * \
66 sizeof(struct txgbe_rx_desc))
68 #define TXGBE_PTID_MASK 0xFF
70 #define RTE_TXGBE_REGISTER_POLL_WAIT_10_MS 10
71 #define RTE_TXGBE_WAIT_100_US 100
73 #define TXGBE_TX_MAX_SEG 40
76 * Structure associated with each descriptor of the RX ring of a RX queue.
78 struct txgbe_rx_entry {
79 struct rte_mbuf *mbuf; /**< mbuf associated with RX descriptor. */
82 struct txgbe_scattered_rx_entry {
83 struct rte_mbuf *fbuf; /**< First segment of the fragmented packet. */
87 * Structure associated with each descriptor of the TX ring of a TX queue.
89 struct txgbe_tx_entry {
90 struct rte_mbuf *mbuf; /**< mbuf associated with TX desc, if any. */
91 uint16_t next_id; /**< Index of next descriptor in ring. */
92 uint16_t last_id; /**< Index of last scattered descriptor. */
96 * Structure associated with each descriptor of the TX ring of a TX queue.
98 struct txgbe_tx_entry_v {
99 struct rte_mbuf *mbuf; /**< mbuf associated with TX desc, if any. */
103 * Structure associated with each RX queue.
105 struct txgbe_rx_queue {
106 struct rte_mempool *mb_pool; /**< mbuf pool to populate RX ring. */
107 volatile struct txgbe_rx_desc *rx_ring; /**< RX ring virtual address. */
108 uint64_t rx_ring_phys_addr; /**< RX ring DMA address. */
109 volatile uint32_t *rdt_reg_addr; /**< RDT register address. */
110 volatile uint32_t *rdh_reg_addr; /**< RDH register address. */
111 struct txgbe_rx_entry *sw_ring; /**< address of RX software ring. */
112 /**< address of scattered Rx software ring. */
113 struct txgbe_scattered_rx_entry *sw_sc_ring;
114 struct rte_mbuf *pkt_first_seg; /**< First segment of current packet. */
115 struct rte_mbuf *pkt_last_seg; /**< Last segment of current packet. */
116 uint16_t nb_rx_desc; /**< number of RX descriptors. */
117 uint16_t rx_tail; /**< current value of RDT register. */
118 uint16_t nb_rx_hold; /**< number of held free RX desc. */
119 uint16_t rx_nb_avail; /**< nr of staged pkts ready to ret to app */
120 uint16_t rx_next_avail; /**< idx of next staged pkt to ret to app */
121 uint16_t rx_free_trigger; /**< triggers rx buffer allocation */
122 uint16_t rx_free_thresh; /**< max free RX desc to hold. */
123 uint16_t queue_id; /**< RX queue index. */
124 uint16_t reg_idx; /**< RX queue register index. */
125 /**< Packet type mask for different NICs. */
126 uint16_t pkt_type_mask;
127 uint16_t port_id; /**< Device port identifier. */
128 uint8_t crc_len; /**< 0 if CRC stripped, 4 otherwise. */
129 uint8_t drop_en; /**< If not 0, set SRRCTL.Drop_En. */
130 uint8_t rx_deferred_start; /**< not in global dev start. */
131 uint64_t offloads; /**< Rx offloads with DEV_RX_OFFLOAD_* */
132 /** need to alloc dummy mbuf, for wraparound when scanning hw ring */
133 struct rte_mbuf fake_mbuf;
134 /** hold packets to return to application */
135 struct rte_mbuf *rx_stage[RTE_PMD_TXGBE_RX_MAX_BURST * 2];
139 * Structure associated with each TX queue.
141 struct txgbe_tx_queue {
142 /** TX ring virtual address. */
143 volatile struct txgbe_tx_desc *tx_ring;
144 uint64_t tx_ring_phys_addr; /**< TX ring DMA address. */
146 /**< address of SW ring for scalar PMD. */
147 struct txgbe_tx_entry *sw_ring;
148 /**< address of SW ring for vector PMD */
149 struct txgbe_tx_entry_v *sw_ring_v;
151 volatile uint32_t *tdt_reg_addr; /**< Address of TDT register. */
152 volatile uint32_t *tdc_reg_addr; /**< Address of TDC register. */
153 uint16_t nb_tx_desc; /**< number of TX descriptors. */
154 uint16_t tx_tail; /**< current value of TDT reg. */
155 /**< Start freeing TX buffers if there are less free descriptors than
158 uint16_t tx_free_thresh;
159 uint16_t queue_id; /**< TX queue index. */
160 uint16_t reg_idx; /**< TX queue register index. */
161 uint16_t port_id; /**< Device port identifier. */
162 uint8_t pthresh; /**< Prefetch threshold register. */
163 uint8_t hthresh; /**< Host threshold register. */
164 uint8_t wthresh; /**< Write-back threshold reg. */
165 uint64_t offloads; /**< Tx offload flags of DEV_TX_OFFLOAD_* */
166 const struct txgbe_txq_ops *ops; /**< txq ops */
167 uint8_t tx_deferred_start; /**< not in global dev start. */
170 struct txgbe_txq_ops {
171 void (*release_mbufs)(struct txgbe_tx_queue *txq);
172 void (*free_swring)(struct txgbe_tx_queue *txq);
173 void (*reset)(struct txgbe_tx_queue *txq);
176 /* Takes an ethdev and a queue and sets up the tx function to be used based on
177 * the queue parameters. Used in tx_queue_setup by primary process and then
178 * in dev_init by secondary process when attaching to an existing ethdev.
180 void txgbe_set_tx_function(struct rte_eth_dev *dev, struct txgbe_tx_queue *txq);
182 void txgbe_set_rx_function(struct rte_eth_dev *dev);
184 uint64_t txgbe_get_tx_port_offloads(struct rte_eth_dev *dev);
185 uint64_t txgbe_get_rx_queue_offloads(struct rte_eth_dev *dev);
186 uint64_t txgbe_get_rx_port_offloads(struct rte_eth_dev *dev);
187 uint64_t txgbe_get_tx_queue_offloads(struct rte_eth_dev *dev);
189 #endif /* _TXGBE_RXTX_H_ */