1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2015-2020
8 /*****************************************************************************
10 *****************************************************************************/
11 struct txgbe_rx_desc {
27 } qw0; /* also as r.pkt_addr */
42 } qw1; /* also as r.hdr_addr */
45 /* @txgbe_rx_desc.qw0 */
46 #define TXGBE_RXD_PKTADDR(rxd, v) \
47 (((volatile __le64 *)(rxd))[0] = cpu_to_le64(v))
49 /* @txgbe_rx_desc.qw1 */
50 #define TXGBE_RXD_HDRADDR(rxd, v) \
51 (((volatile __le64 *)(rxd))[1] = cpu_to_le64(v))
53 /*****************************************************************************
55 *****************************************************************************/
57 * Transmit Context Descriptor (TXGBE_TXD_TYP=CTXT)
59 struct txgbe_tx_ctx_desc {
60 __le32 dw0; /* w.vlan_macip_lens */
61 __le32 dw1; /* w.seqnum_seed */
62 __le32 dw2; /* w.type_tucmd_mlhl */
63 __le32 dw3; /* w.mss_l4len_idx */
66 /* @txgbe_tx_ctx_desc.dw0 */
67 #define TXGBE_TXD_IPLEN(v) LS(v, 0, 0x1FF) /* ip/fcoe header end */
68 #define TXGBE_TXD_MACLEN(v) LS(v, 9, 0x7F) /* desc mac len */
69 #define TXGBE_TXD_VLAN(v) LS(v, 16, 0xFFFF) /* vlan tag */
71 /* @txgbe_tx_ctx_desc.dw1 */
72 /*** bit 0-31, when TXGBE_TXD_DTYP_FCOE=0 ***/
73 #define TXGBE_TXD_IPSEC_SAIDX(v) LS(v, 0, 0x3FF) /* ipsec SA index */
74 #define TXGBE_TXD_ETYPE(v) LS(v, 11, 0x1) /* tunnel type */
75 #define TXGBE_TXD_ETYPE_UDP LS(0, 11, 0x1)
76 #define TXGBE_TXD_ETYPE_GRE LS(1, 11, 0x1)
77 #define TXGBE_TXD_EIPLEN(v) LS(v, 12, 0x7F) /* tunnel ip header */
78 #define TXGBE_TXD_DTYP_FCOE MS(16, 0x1) /* FCoE/IP descriptor */
79 #define TXGBE_TXD_ETUNLEN(v) LS(v, 21, 0xFF) /* tunnel header */
80 #define TXGBE_TXD_DECTTL(v) LS(v, 29, 0xF) /* decrease ip TTL */
81 /*** bit 0-31, when TXGBE_TXD_DTYP_FCOE=1 ***/
82 #define TXGBE_TXD_FCOEF_EOF_MASK MS(10, 0x3) /* FC EOF index */
83 #define TXGBE_TXD_FCOEF_EOF_N LS(0, 10, 0x3) /* EOFn */
84 #define TXGBE_TXD_FCOEF_EOF_T LS(1, 10, 0x3) /* EOFt */
85 #define TXGBE_TXD_FCOEF_EOF_NI LS(2, 10, 0x3) /* EOFni */
86 #define TXGBE_TXD_FCOEF_EOF_A LS(3, 10, 0x3) /* EOFa */
87 #define TXGBE_TXD_FCOEF_SOF MS(12, 0x1) /* FC SOF index */
88 #define TXGBE_TXD_FCOEF_PARINC MS(13, 0x1) /* Rel_Off in F_CTL */
89 #define TXGBE_TXD_FCOEF_ORIE MS(14, 0x1) /* orientation end */
90 #define TXGBE_TXD_FCOEF_ORIS MS(15, 0x1) /* orientation start */
92 /* @txgbe_tx_ctx_desc.dw2 */
93 #define TXGBE_TXD_IPSEC_ESPLEN(v) LS(v, 1, 0x1FF) /* ipsec ESP length */
94 #define TXGBE_TXD_SNAP MS(10, 0x1) /* SNAP indication */
95 #define TXGBE_TXD_TPID_SEL(v) LS(v, 11, 0x7) /* vlan tag index */
96 #define TXGBE_TXD_IPSEC_ESP MS(14, 0x1) /* ipsec type: esp=1 ah=0 */
97 #define TXGBE_TXD_IPSEC_ESPENC MS(15, 0x1) /* ESP encrypt */
98 #define TXGBE_TXD_CTXT MS(20, 0x1) /* context descriptor */
99 #define TXGBE_TXD_PTID(v) LS(v, 24, 0xFF) /* packet type */
100 /* @txgbe_tx_ctx_desc.dw3 */
101 #define TXGBE_TXD_DD MS(0, 0x1) /* descriptor done */
102 #define TXGBE_TXD_IDX(v) LS(v, 4, 0x1) /* ctxt desc index */
103 #define TXGBE_TXD_L4LEN(v) LS(v, 8, 0xFF) /* l4 header length */
104 #define TXGBE_TXD_MSS(v) LS(v, 16, 0xFFFF) /* l4 MSS */
107 * Transmit Data Descriptor (TXGBE_TXD_TYP=DATA)
109 struct txgbe_tx_desc {
110 __le64 qw0; /* r.buffer_addr , w.reserved */
111 __le32 dw2; /* r.cmd_type_len, w.nxtseq_seed */
112 __le32 dw3; /* r.olinfo_status, w.status */
114 /* @txgbe_tx_desc.qw0 */
116 /* @txgbe_tx_desc.dw2 */
117 #define TXGBE_TXD_DATLEN(v) ((0xFFFF & (v))) /* data buffer length */
118 #define TXGBE_TXD_1588 ((0x1) << 19) /* IEEE1588 time stamp */
119 #define TXGBE_TXD_DATA ((0x0) << 20) /* data descriptor */
120 #define TXGBE_TXD_EOP ((0x1) << 24) /* End of Packet */
121 #define TXGBE_TXD_FCS ((0x1) << 25) /* Insert FCS */
122 #define TXGBE_TXD_LINKSEC ((0x1) << 26) /* Insert LinkSec */
123 #define TXGBE_TXD_ECU ((0x1) << 28) /* forward to ECU */
124 #define TXGBE_TXD_CNTAG ((0x1) << 29) /* insert CN tag */
125 #define TXGBE_TXD_VLE ((0x1) << 30) /* insert VLAN tag */
126 #define TXGBE_TXD_TSE ((0x1) << 31) /* transmit segmentation */
128 #define TXGBE_TXD_FLAGS (TXGBE_TXD_FCS | TXGBE_TXD_EOP)
130 /* @txgbe_tx_desc.dw3 */
131 #define TXGBE_TXD_DD_UNUSED TXGBE_TXD_DD
132 #define TXGBE_TXD_IDX_UNUSED(v) TXGBE_TXD_IDX(v)
133 #define TXGBE_TXD_CC ((0x1) << 7) /* check context */
134 #define TXGBE_TXD_IPSEC ((0x1) << 8) /* request ipsec offload */
135 #define TXGBE_TXD_L4CS ((0x1) << 9) /* insert TCP/UDP/SCTP csum */
136 #define TXGBE_TXD_IPCS ((0x1) << 10) /* insert IPv4 csum */
137 #define TXGBE_TXD_EIPCS ((0x1) << 11) /* insert outer IP csum */
138 #define TXGBE_TXD_MNGFLT ((0x1) << 12) /* enable management filter */
139 #define TXGBE_TXD_PAYLEN(v) ((0x7FFFF & (v)) << 13) /* payload length */
141 #define RTE_PMD_TXGBE_TX_MAX_BURST 32
142 #define RTE_PMD_TXGBE_RX_MAX_BURST 32
143 #define RTE_TXGBE_TX_MAX_FREE_BUF_SZ 64
145 #define RX_RING_SZ ((TXGBE_RING_DESC_MAX + RTE_PMD_TXGBE_RX_MAX_BURST) * \
146 sizeof(struct txgbe_rx_desc))
148 #define RTE_TXGBE_REGISTER_POLL_WAIT_10_MS 10
149 #define RTE_TXGBE_WAIT_100_US 100
151 #define TXGBE_TX_MAX_SEG 40
154 * Structure associated with each descriptor of the RX ring of a RX queue.
156 struct txgbe_rx_entry {
157 struct rte_mbuf *mbuf; /**< mbuf associated with RX descriptor. */
160 struct txgbe_scattered_rx_entry {
161 struct rte_mbuf *fbuf; /**< First segment of the fragmented packet. */
165 * Structure associated with each descriptor of the TX ring of a TX queue.
167 struct txgbe_tx_entry {
168 struct rte_mbuf *mbuf; /**< mbuf associated with TX desc, if any. */
169 uint16_t next_id; /**< Index of next descriptor in ring. */
170 uint16_t last_id; /**< Index of last scattered descriptor. */
174 * Structure associated with each descriptor of the TX ring of a TX queue.
176 struct txgbe_tx_entry_v {
177 struct rte_mbuf *mbuf; /**< mbuf associated with TX desc, if any. */
181 * Structure associated with each RX queue.
183 struct txgbe_rx_queue {
184 struct rte_mempool *mb_pool; /**< mbuf pool to populate RX ring. */
185 volatile struct txgbe_rx_desc *rx_ring; /**< RX ring virtual address. */
186 uint64_t rx_ring_phys_addr; /**< RX ring DMA address. */
187 volatile uint32_t *rdt_reg_addr; /**< RDT register address. */
188 volatile uint32_t *rdh_reg_addr; /**< RDH register address. */
189 struct txgbe_rx_entry *sw_ring; /**< address of RX software ring. */
190 /**< address of scattered Rx software ring. */
191 struct txgbe_scattered_rx_entry *sw_sc_ring;
192 struct rte_mbuf *pkt_first_seg; /**< First segment of current packet. */
193 struct rte_mbuf *pkt_last_seg; /**< Last segment of current packet. */
194 uint16_t nb_rx_desc; /**< number of RX descriptors. */
195 uint16_t rx_tail; /**< current value of RDT register. */
196 uint16_t nb_rx_hold; /**< number of held free RX desc. */
197 uint16_t rx_nb_avail; /**< nr of staged pkts ready to ret to app */
198 uint16_t rx_next_avail; /**< idx of next staged pkt to ret to app */
199 uint16_t rx_free_trigger; /**< triggers rx buffer allocation */
200 uint16_t rx_free_thresh; /**< max free RX desc to hold. */
201 uint16_t queue_id; /**< RX queue index. */
202 uint16_t reg_idx; /**< RX queue register index. */
203 /**< Packet type mask for different NICs. */
204 uint16_t pkt_type_mask;
205 uint16_t port_id; /**< Device port identifier. */
206 uint8_t crc_len; /**< 0 if CRC stripped, 4 otherwise. */
207 uint8_t drop_en; /**< If not 0, set SRRCTL.Drop_En. */
208 uint8_t rx_deferred_start; /**< not in global dev start. */
209 uint64_t offloads; /**< Rx offloads with DEV_RX_OFFLOAD_* */
210 /** need to alloc dummy mbuf, for wraparound when scanning hw ring */
211 struct rte_mbuf fake_mbuf;
212 /** hold packets to return to application */
213 struct rte_mbuf *rx_stage[RTE_PMD_TXGBE_RX_MAX_BURST * 2];
217 * TXGBE CTX Constants
220 TXGBE_CTX_0 = 0, /**< CTX0 */
221 TXGBE_CTX_1 = 1, /**< CTX1 */
222 TXGBE_CTX_NUM = 2, /**< CTX NUMBER */
225 /** Offload features */
226 union txgbe_tx_offload {
229 uint64_t ptid:8; /**< Packet Type Identifier. */
230 uint64_t l2_len:7; /**< L2 (MAC) Header Length. */
231 uint64_t l3_len:9; /**< L3 (IP) Header Length. */
232 uint64_t l4_len:8; /**< L4 (TCP/UDP) Header Length. */
233 uint64_t tso_segsz:16; /**< TCP TSO segment size */
234 uint64_t vlan_tci:16;
235 /**< VLAN Tag Control Identifier (CPU order). */
237 /* fields for TX offloading of tunnels */
238 uint64_t outer_tun_len:8; /**< Outer TUN (Tunnel) Hdr Length. */
239 uint64_t outer_l2_len:8; /**< Outer L2 (MAC) Hdr Length. */
240 uint64_t outer_l3_len:16; /**< Outer L3 (IP) Hdr Length. */
245 * Structure to check if new context need be built
247 struct txgbe_ctx_info {
248 uint64_t flags; /**< ol_flags for context build. */
249 /**< tx offload: vlan, tso, l2-l3-l4 lengths. */
250 union txgbe_tx_offload tx_offload;
251 /** compare mask for tx offload. */
252 union txgbe_tx_offload tx_offload_mask;
256 * Structure associated with each TX queue.
258 struct txgbe_tx_queue {
259 /** TX ring virtual address. */
260 volatile struct txgbe_tx_desc *tx_ring;
261 uint64_t tx_ring_phys_addr; /**< TX ring DMA address. */
263 /**< address of SW ring for scalar PMD. */
264 struct txgbe_tx_entry *sw_ring;
265 /**< address of SW ring for vector PMD */
266 struct txgbe_tx_entry_v *sw_ring_v;
268 volatile uint32_t *tdt_reg_addr; /**< Address of TDT register. */
269 volatile uint32_t *tdc_reg_addr; /**< Address of TDC register. */
270 uint16_t nb_tx_desc; /**< number of TX descriptors. */
271 uint16_t tx_tail; /**< current value of TDT reg. */
272 /**< Start freeing TX buffers if there are less free descriptors than
275 uint16_t tx_free_thresh;
276 /** Index to last TX descriptor to have been cleaned. */
277 uint16_t last_desc_cleaned;
278 /** Total number of TX descriptors ready to be allocated. */
280 uint16_t tx_next_dd; /**< next desc to scan for DD bit */
281 uint16_t queue_id; /**< TX queue index. */
282 uint16_t reg_idx; /**< TX queue register index. */
283 uint16_t port_id; /**< Device port identifier. */
284 uint8_t pthresh; /**< Prefetch threshold register. */
285 uint8_t hthresh; /**< Host threshold register. */
286 uint8_t wthresh; /**< Write-back threshold reg. */
287 uint64_t offloads; /* Tx offload flags of DEV_TX_OFFLOAD_* */
288 uint32_t ctx_curr; /**< Hardware context states. */
289 /** Hardware context0 history. */
290 struct txgbe_ctx_info ctx_cache[TXGBE_CTX_NUM];
291 const struct txgbe_txq_ops *ops; /**< txq ops */
292 uint8_t tx_deferred_start; /**< not in global dev start. */
295 struct txgbe_txq_ops {
296 void (*release_mbufs)(struct txgbe_tx_queue *txq);
297 void (*free_swring)(struct txgbe_tx_queue *txq);
298 void (*reset)(struct txgbe_tx_queue *txq);
301 /* Takes an ethdev and a queue and sets up the tx function to be used based on
302 * the queue parameters. Used in tx_queue_setup by primary process and then
303 * in dev_init by secondary process when attaching to an existing ethdev.
305 void txgbe_set_tx_function(struct rte_eth_dev *dev, struct txgbe_tx_queue *txq);
307 void txgbe_set_rx_function(struct rte_eth_dev *dev);
309 uint64_t txgbe_get_tx_port_offloads(struct rte_eth_dev *dev);
310 uint64_t txgbe_get_rx_queue_offloads(struct rte_eth_dev *dev);
311 uint64_t txgbe_get_rx_port_offloads(struct rte_eth_dev *dev);
312 uint64_t txgbe_get_tx_queue_offloads(struct rte_eth_dev *dev);
314 #endif /* _TXGBE_RXTX_H_ */