1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2010-2014 Intel Corporation
6 #ifdef RTE_EXEC_ENV_LINUX
14 #include "virtio_pci.h"
15 #include "virtio_logs.h"
16 #include "virtqueue.h"
19 * Following macros are derived from linux/pci_regs.h, however,
20 * we can't simply include that header here, as there is no such
21 * file for non-Linux platform.
23 #define PCI_CAPABILITY_LIST 0x34
24 #define PCI_CAP_ID_VNDR 0x09
25 #define PCI_CAP_ID_MSIX 0x11
28 * The remaining space is defined by each driver as the per-driver
29 * configuration space.
31 #define VIRTIO_PCI_CONFIG(dev) \
32 (((dev)->msix_status == VIRTIO_MSIX_ENABLED) ? 24 : 20)
34 struct virtio_pci_internal virtio_pci_internal[RTE_MAX_ETHPORTS];
37 check_vq_phys_addr_ok(struct virtqueue *vq)
39 /* Virtio PCI device VIRTIO_PCI_QUEUE_PF register is 32bit,
40 * and only accepts 32 bit page frame number.
41 * Check if the allocated physical memory exceeds 16TB.
43 if ((vq->vq_ring_mem + vq->vq_ring_size - 1) >>
44 (VIRTIO_PCI_QUEUE_ADDR_SHIFT + 32)) {
45 PMD_INIT_LOG(ERR, "vring address shouldn't be above 16TB!");
52 #define PCI_MSIX_ENABLE 0x8000
54 static enum virtio_msix_status
55 vtpci_msix_detect(struct rte_pci_device *dev)
60 ret = rte_pci_read_config(dev, &pos, 1, PCI_CAPABILITY_LIST);
63 "failed to read pci capability list, ret %d", ret);
64 return VIRTIO_MSIX_NONE;
70 ret = rte_pci_read_config(dev, cap, sizeof(cap), pos);
71 if (ret != sizeof(cap)) {
73 "failed to read pci cap at pos: %x ret %d",
78 if (cap[0] == PCI_CAP_ID_MSIX) {
81 ret = rte_pci_read_config(dev, &flags, sizeof(flags),
83 if (ret != sizeof(flags)) {
85 "failed to read pci cap at pos:"
86 " %x ret %d", pos + 2, ret);
90 if (flags & PCI_MSIX_ENABLE)
91 return VIRTIO_MSIX_ENABLED;
93 return VIRTIO_MSIX_DISABLED;
99 return VIRTIO_MSIX_NONE;
103 * Since we are in legacy mode:
104 * http://ozlabs.org/~rusty/virtio-spec/virtio-0.9.5.pdf
106 * "Note that this is possible because while the virtio header is PCI (i.e.
107 * little) endian, the device-specific region is encoded in the native endian of
108 * the guest (where such distinction is applicable)."
110 * For powerpc which supports both, qemu supposes that cpu is big endian and
111 * enforces this for the virtio-net stuff.
114 legacy_read_dev_config(struct virtio_hw *hw, size_t offset,
115 void *dst, int length)
117 struct virtio_pci_dev *dev = virtio_pci_get_dev(hw);
118 #ifdef RTE_ARCH_PPC_64
124 rte_pci_ioport_read(VTPCI_IO(hw), dst, size,
125 VIRTIO_PCI_CONFIG(dev) + offset);
126 *(uint32_t *)dst = rte_be_to_cpu_32(*(uint32_t *)dst);
127 } else if (length >= 2) {
129 rte_pci_ioport_read(VTPCI_IO(hw), dst, size,
130 VIRTIO_PCI_CONFIG(dev) + offset);
131 *(uint16_t *)dst = rte_be_to_cpu_16(*(uint16_t *)dst);
134 rte_pci_ioport_read(VTPCI_IO(hw), dst, size,
135 VIRTIO_PCI_CONFIG(dev) + offset);
138 dst = (char *)dst + size;
143 rte_pci_ioport_read(VTPCI_IO(hw), dst, length,
144 VIRTIO_PCI_CONFIG(dev) + offset);
149 legacy_write_dev_config(struct virtio_hw *hw, size_t offset,
150 const void *src, int length)
152 struct virtio_pci_dev *dev = virtio_pci_get_dev(hw);
153 #ifdef RTE_ARCH_PPC_64
163 tmp.u32 = rte_cpu_to_be_32(*(const uint32_t *)src);
164 rte_pci_ioport_write(VTPCI_IO(hw), &tmp.u32, size,
165 VIRTIO_PCI_CONFIG(dev) + offset);
166 } else if (length >= 2) {
168 tmp.u16 = rte_cpu_to_be_16(*(const uint16_t *)src);
169 rte_pci_ioport_write(VTPCI_IO(hw), &tmp.u16, size,
170 VIRTIO_PCI_CONFIG(dev) + offset);
173 rte_pci_ioport_write(VTPCI_IO(hw), src, size,
174 VIRTIO_PCI_CONFIG(dev) + offset);
177 src = (const char *)src + size;
182 rte_pci_ioport_write(VTPCI_IO(hw), src, length,
183 VIRTIO_PCI_CONFIG(dev) + offset);
188 legacy_get_features(struct virtio_hw *hw)
192 rte_pci_ioport_read(VTPCI_IO(hw), &dst, 4, VIRTIO_PCI_HOST_FEATURES);
197 legacy_set_features(struct virtio_hw *hw, uint64_t features)
199 if ((features >> 32) != 0) {
201 "only 32 bit features are allowed for legacy virtio!");
204 rte_pci_ioport_write(VTPCI_IO(hw), &features, 4,
205 VIRTIO_PCI_GUEST_FEATURES);
209 legacy_features_ok(struct virtio_hw *hw __rte_unused)
215 legacy_get_status(struct virtio_hw *hw)
219 rte_pci_ioport_read(VTPCI_IO(hw), &dst, 1, VIRTIO_PCI_STATUS);
224 legacy_set_status(struct virtio_hw *hw, uint8_t status)
226 rte_pci_ioport_write(VTPCI_IO(hw), &status, 1, VIRTIO_PCI_STATUS);
230 legacy_get_isr(struct virtio_hw *hw)
234 rte_pci_ioport_read(VTPCI_IO(hw), &dst, 1, VIRTIO_PCI_ISR);
238 /* Enable one vector (0) for Link State Intrerrupt */
240 legacy_set_config_irq(struct virtio_hw *hw, uint16_t vec)
244 rte_pci_ioport_write(VTPCI_IO(hw), &vec, 2, VIRTIO_MSI_CONFIG_VECTOR);
245 rte_pci_ioport_read(VTPCI_IO(hw), &dst, 2, VIRTIO_MSI_CONFIG_VECTOR);
250 legacy_set_queue_irq(struct virtio_hw *hw, struct virtqueue *vq, uint16_t vec)
254 rte_pci_ioport_write(VTPCI_IO(hw), &vq->vq_queue_index, 2,
255 VIRTIO_PCI_QUEUE_SEL);
256 rte_pci_ioport_write(VTPCI_IO(hw), &vec, 2, VIRTIO_MSI_QUEUE_VECTOR);
257 rte_pci_ioport_read(VTPCI_IO(hw), &dst, 2, VIRTIO_MSI_QUEUE_VECTOR);
262 legacy_get_queue_num(struct virtio_hw *hw, uint16_t queue_id)
266 rte_pci_ioport_write(VTPCI_IO(hw), &queue_id, 2, VIRTIO_PCI_QUEUE_SEL);
267 rte_pci_ioport_read(VTPCI_IO(hw), &dst, 2, VIRTIO_PCI_QUEUE_NUM);
272 legacy_setup_queue(struct virtio_hw *hw, struct virtqueue *vq)
276 if (!check_vq_phys_addr_ok(vq))
279 rte_pci_ioport_write(VTPCI_IO(hw), &vq->vq_queue_index, 2,
280 VIRTIO_PCI_QUEUE_SEL);
281 src = vq->vq_ring_mem >> VIRTIO_PCI_QUEUE_ADDR_SHIFT;
282 rte_pci_ioport_write(VTPCI_IO(hw), &src, 4, VIRTIO_PCI_QUEUE_PFN);
288 legacy_del_queue(struct virtio_hw *hw, struct virtqueue *vq)
292 rte_pci_ioport_write(VTPCI_IO(hw), &vq->vq_queue_index, 2,
293 VIRTIO_PCI_QUEUE_SEL);
294 rte_pci_ioport_write(VTPCI_IO(hw), &src, 4, VIRTIO_PCI_QUEUE_PFN);
298 legacy_notify_queue(struct virtio_hw *hw, struct virtqueue *vq)
300 rte_pci_ioport_write(VTPCI_IO(hw), &vq->vq_queue_index, 2,
301 VIRTIO_PCI_QUEUE_NOTIFY);
305 legacy_intr_detect(struct virtio_hw *hw)
307 struct virtio_pci_dev *dev = virtio_pci_get_dev(hw);
309 dev->msix_status = vtpci_msix_detect(VTPCI_DEV(hw));
310 hw->intr_lsc = !!dev->msix_status;
314 legacy_dev_close(struct virtio_hw *hw)
316 rte_pci_unmap_device(VTPCI_DEV(hw));
317 rte_pci_ioport_unmap(VTPCI_IO(hw));
322 const struct virtio_ops legacy_ops = {
323 .read_dev_cfg = legacy_read_dev_config,
324 .write_dev_cfg = legacy_write_dev_config,
325 .get_status = legacy_get_status,
326 .set_status = legacy_set_status,
327 .get_features = legacy_get_features,
328 .set_features = legacy_set_features,
329 .features_ok = legacy_features_ok,
330 .get_isr = legacy_get_isr,
331 .set_config_irq = legacy_set_config_irq,
332 .set_queue_irq = legacy_set_queue_irq,
333 .get_queue_num = legacy_get_queue_num,
334 .setup_queue = legacy_setup_queue,
335 .del_queue = legacy_del_queue,
336 .notify_queue = legacy_notify_queue,
337 .intr_detect = legacy_intr_detect,
338 .dev_close = legacy_dev_close,
342 io_write64_twopart(uint64_t val, uint32_t *lo, uint32_t *hi)
344 rte_write32(val & ((1ULL << 32) - 1), lo);
345 rte_write32(val >> 32, hi);
349 modern_read_dev_config(struct virtio_hw *hw, size_t offset,
350 void *dst, int length)
352 struct virtio_pci_dev *dev = virtio_pci_get_dev(hw);
355 uint8_t old_gen, new_gen;
358 old_gen = rte_read8(&dev->common_cfg->config_generation);
361 for (i = 0; i < length; i++)
362 *p++ = rte_read8((uint8_t *)dev->dev_cfg + offset + i);
364 new_gen = rte_read8(&dev->common_cfg->config_generation);
365 } while (old_gen != new_gen);
369 modern_write_dev_config(struct virtio_hw *hw, size_t offset,
370 const void *src, int length)
372 struct virtio_pci_dev *dev = virtio_pci_get_dev(hw);
374 const uint8_t *p = src;
376 for (i = 0; i < length; i++)
377 rte_write8((*p++), (((uint8_t *)dev->dev_cfg) + offset + i));
381 modern_get_features(struct virtio_hw *hw)
383 struct virtio_pci_dev *dev = virtio_pci_get_dev(hw);
384 uint32_t features_lo, features_hi;
386 rte_write32(0, &dev->common_cfg->device_feature_select);
387 features_lo = rte_read32(&dev->common_cfg->device_feature);
389 rte_write32(1, &dev->common_cfg->device_feature_select);
390 features_hi = rte_read32(&dev->common_cfg->device_feature);
392 return ((uint64_t)features_hi << 32) | features_lo;
396 modern_set_features(struct virtio_hw *hw, uint64_t features)
398 struct virtio_pci_dev *dev = virtio_pci_get_dev(hw);
400 rte_write32(0, &dev->common_cfg->guest_feature_select);
401 rte_write32(features & ((1ULL << 32) - 1),
402 &dev->common_cfg->guest_feature);
404 rte_write32(1, &dev->common_cfg->guest_feature_select);
405 rte_write32(features >> 32,
406 &dev->common_cfg->guest_feature);
410 modern_features_ok(struct virtio_hw *hw)
412 if (!virtio_with_feature(hw, VIRTIO_F_VERSION_1)) {
413 PMD_INIT_LOG(ERR, "Version 1+ required with modern devices");
421 modern_get_status(struct virtio_hw *hw)
423 struct virtio_pci_dev *dev = virtio_pci_get_dev(hw);
425 return rte_read8(&dev->common_cfg->device_status);
429 modern_set_status(struct virtio_hw *hw, uint8_t status)
431 struct virtio_pci_dev *dev = virtio_pci_get_dev(hw);
433 rte_write8(status, &dev->common_cfg->device_status);
437 modern_get_isr(struct virtio_hw *hw)
439 struct virtio_pci_dev *dev = virtio_pci_get_dev(hw);
441 return rte_read8(dev->isr);
445 modern_set_config_irq(struct virtio_hw *hw, uint16_t vec)
447 struct virtio_pci_dev *dev = virtio_pci_get_dev(hw);
449 rte_write16(vec, &dev->common_cfg->msix_config);
450 return rte_read16(&dev->common_cfg->msix_config);
454 modern_set_queue_irq(struct virtio_hw *hw, struct virtqueue *vq, uint16_t vec)
456 struct virtio_pci_dev *dev = virtio_pci_get_dev(hw);
458 rte_write16(vq->vq_queue_index, &dev->common_cfg->queue_select);
459 rte_write16(vec, &dev->common_cfg->queue_msix_vector);
460 return rte_read16(&dev->common_cfg->queue_msix_vector);
464 modern_get_queue_num(struct virtio_hw *hw, uint16_t queue_id)
466 struct virtio_pci_dev *dev = virtio_pci_get_dev(hw);
468 rte_write16(queue_id, &dev->common_cfg->queue_select);
469 return rte_read16(&dev->common_cfg->queue_size);
473 modern_setup_queue(struct virtio_hw *hw, struct virtqueue *vq)
475 struct virtio_pci_dev *dev = virtio_pci_get_dev(hw);
476 uint64_t desc_addr, avail_addr, used_addr;
479 if (!check_vq_phys_addr_ok(vq))
482 desc_addr = vq->vq_ring_mem;
483 avail_addr = desc_addr + vq->vq_nentries * sizeof(struct vring_desc);
484 used_addr = RTE_ALIGN_CEIL(avail_addr + offsetof(struct vring_avail,
485 ring[vq->vq_nentries]),
488 rte_write16(vq->vq_queue_index, &dev->common_cfg->queue_select);
490 io_write64_twopart(desc_addr, &dev->common_cfg->queue_desc_lo,
491 &dev->common_cfg->queue_desc_hi);
492 io_write64_twopart(avail_addr, &dev->common_cfg->queue_avail_lo,
493 &dev->common_cfg->queue_avail_hi);
494 io_write64_twopart(used_addr, &dev->common_cfg->queue_used_lo,
495 &dev->common_cfg->queue_used_hi);
497 notify_off = rte_read16(&dev->common_cfg->queue_notify_off);
498 vq->notify_addr = (void *)((uint8_t *)dev->notify_base +
499 notify_off * dev->notify_off_multiplier);
501 rte_write16(1, &dev->common_cfg->queue_enable);
503 PMD_INIT_LOG(DEBUG, "queue %u addresses:", vq->vq_queue_index);
504 PMD_INIT_LOG(DEBUG, "\t desc_addr: %" PRIx64, desc_addr);
505 PMD_INIT_LOG(DEBUG, "\t aval_addr: %" PRIx64, avail_addr);
506 PMD_INIT_LOG(DEBUG, "\t used_addr: %" PRIx64, used_addr);
507 PMD_INIT_LOG(DEBUG, "\t notify addr: %p (notify offset: %u)",
508 vq->notify_addr, notify_off);
514 modern_del_queue(struct virtio_hw *hw, struct virtqueue *vq)
516 struct virtio_pci_dev *dev = virtio_pci_get_dev(hw);
518 rte_write16(vq->vq_queue_index, &dev->common_cfg->queue_select);
520 io_write64_twopart(0, &dev->common_cfg->queue_desc_lo,
521 &dev->common_cfg->queue_desc_hi);
522 io_write64_twopart(0, &dev->common_cfg->queue_avail_lo,
523 &dev->common_cfg->queue_avail_hi);
524 io_write64_twopart(0, &dev->common_cfg->queue_used_lo,
525 &dev->common_cfg->queue_used_hi);
527 rte_write16(0, &dev->common_cfg->queue_enable);
531 modern_notify_queue(struct virtio_hw *hw, struct virtqueue *vq)
533 uint32_t notify_data;
535 if (!virtio_with_feature(hw, VIRTIO_F_NOTIFICATION_DATA)) {
536 rte_write16(vq->vq_queue_index, vq->notify_addr);
540 if (virtio_with_packed_queue(hw)) {
542 * Bit[0:15]: vq queue index
543 * Bit[16:30]: avail index
544 * Bit[31]: avail wrap counter
546 notify_data = ((uint32_t)(!!(vq->vq_packed.cached_flags &
547 VRING_PACKED_DESC_F_AVAIL)) << 31) |
548 ((uint32_t)vq->vq_avail_idx << 16) |
552 * Bit[0:15]: vq queue index
553 * Bit[16:31]: avail index
555 notify_data = ((uint32_t)vq->vq_avail_idx << 16) |
558 rte_write32(notify_data, vq->notify_addr);
564 modern_intr_detect(struct virtio_hw *hw)
566 struct virtio_pci_dev *dev = virtio_pci_get_dev(hw);
568 dev->msix_status = vtpci_msix_detect(VTPCI_DEV(hw));
569 hw->intr_lsc = !!dev->msix_status;
573 modern_dev_close(struct virtio_hw *hw)
575 rte_pci_unmap_device(VTPCI_DEV(hw));
580 const struct virtio_ops modern_ops = {
581 .read_dev_cfg = modern_read_dev_config,
582 .write_dev_cfg = modern_write_dev_config,
583 .get_status = modern_get_status,
584 .set_status = modern_set_status,
585 .get_features = modern_get_features,
586 .set_features = modern_set_features,
587 .features_ok = modern_features_ok,
588 .get_isr = modern_get_isr,
589 .set_config_irq = modern_set_config_irq,
590 .set_queue_irq = modern_set_queue_irq,
591 .get_queue_num = modern_get_queue_num,
592 .setup_queue = modern_setup_queue,
593 .del_queue = modern_del_queue,
594 .notify_queue = modern_notify_queue,
595 .intr_detect = modern_intr_detect,
596 .dev_close = modern_dev_close,
600 get_cfg_addr(struct rte_pci_device *dev, struct virtio_pci_cap *cap)
602 uint8_t bar = cap->bar;
603 uint32_t length = cap->length;
604 uint32_t offset = cap->offset;
607 if (bar >= PCI_MAX_RESOURCE) {
608 PMD_INIT_LOG(ERR, "invalid bar: %u", bar);
612 if (offset + length < offset) {
613 PMD_INIT_LOG(ERR, "offset(%u) + length(%u) overflows",
618 if (offset + length > dev->mem_resource[bar].len) {
620 "invalid cap: overflows bar space: %u > %" PRIu64,
621 offset + length, dev->mem_resource[bar].len);
625 base = dev->mem_resource[bar].addr;
627 PMD_INIT_LOG(ERR, "bar %u base addr is NULL", bar);
631 return base + offset;
635 virtio_read_caps(struct rte_pci_device *pci_dev, struct virtio_hw *hw)
637 struct virtio_pci_dev *dev = virtio_pci_get_dev(hw);
639 struct virtio_pci_cap cap;
642 if (rte_pci_map_device(pci_dev)) {
643 PMD_INIT_LOG(DEBUG, "failed to map pci device!");
647 ret = rte_pci_read_config(pci_dev, &pos, 1, PCI_CAPABILITY_LIST);
650 "failed to read pci capability list, ret %d", ret);
655 ret = rte_pci_read_config(pci_dev, &cap, 2, pos);
658 "failed to read pci cap at pos: %x ret %d",
663 if (cap.cap_vndr == PCI_CAP_ID_MSIX) {
664 /* Transitional devices would also have this capability,
665 * that's why we also check if msix is enabled.
666 * 1st byte is cap ID; 2nd byte is the position of next
667 * cap; next two bytes are the flags.
671 ret = rte_pci_read_config(pci_dev, &flags, sizeof(flags),
673 if (ret != sizeof(flags)) {
675 "failed to read pci cap at pos:"
676 " %x ret %d", pos + 2, ret);
680 if (flags & PCI_MSIX_ENABLE)
681 dev->msix_status = VIRTIO_MSIX_ENABLED;
683 dev->msix_status = VIRTIO_MSIX_DISABLED;
686 if (cap.cap_vndr != PCI_CAP_ID_VNDR) {
688 "[%2x] skipping non VNDR cap id: %02x",
693 ret = rte_pci_read_config(pci_dev, &cap, sizeof(cap), pos);
694 if (ret != sizeof(cap)) {
696 "failed to read pci cap at pos: %x ret %d",
702 "[%2x] cfg type: %u, bar: %u, offset: %04x, len: %u",
703 pos, cap.cfg_type, cap.bar, cap.offset, cap.length);
705 switch (cap.cfg_type) {
706 case VIRTIO_PCI_CAP_COMMON_CFG:
707 dev->common_cfg = get_cfg_addr(pci_dev, &cap);
709 case VIRTIO_PCI_CAP_NOTIFY_CFG:
710 ret = rte_pci_read_config(pci_dev,
711 &dev->notify_off_multiplier,
712 4, pos + sizeof(cap));
715 "failed to read notify_off_multiplier, ret %d",
718 dev->notify_base = get_cfg_addr(pci_dev, &cap);
720 case VIRTIO_PCI_CAP_DEVICE_CFG:
721 dev->dev_cfg = get_cfg_addr(pci_dev, &cap);
723 case VIRTIO_PCI_CAP_ISR_CFG:
724 dev->isr = get_cfg_addr(pci_dev, &cap);
732 if (dev->common_cfg == NULL || dev->notify_base == NULL ||
733 dev->dev_cfg == NULL || dev->isr == NULL) {
734 PMD_INIT_LOG(INFO, "no modern virtio pci device found.");
738 PMD_INIT_LOG(INFO, "found modern virtio pci device.");
740 PMD_INIT_LOG(DEBUG, "common cfg mapped at: %p", dev->common_cfg);
741 PMD_INIT_LOG(DEBUG, "device cfg mapped at: %p", dev->dev_cfg);
742 PMD_INIT_LOG(DEBUG, "isr cfg mapped at: %p", dev->isr);
743 PMD_INIT_LOG(DEBUG, "notify base: %p, notify off multiplier: %u",
744 dev->notify_base, dev->notify_off_multiplier);
751 * if there is error mapping with VFIO/UIO.
752 * if port map error when driver type is KDRV_NONE.
753 * if marked as allowed but driver type is KDRV_UNKNOWN.
754 * Return 1 if kernel driver is managing the device.
755 * Return 0 on success.
758 vtpci_init(struct rte_pci_device *pci_dev, struct virtio_pci_dev *dev)
760 struct virtio_hw *hw = &dev->hw;
762 RTE_BUILD_BUG_ON(offsetof(struct virtio_pci_dev, hw) != 0);
765 * Try if we can succeed reading virtio pci caps, which exists
766 * only on modern pci device. If failed, we fallback to legacy
769 if (virtio_read_caps(pci_dev, hw) == 0) {
770 PMD_INIT_LOG(INFO, "modern virtio pci detected.");
771 VIRTIO_OPS(hw) = &modern_ops;
776 PMD_INIT_LOG(INFO, "trying with legacy virtio pci.");
777 if (rte_pci_ioport_map(pci_dev, 0, VTPCI_IO(hw)) < 0) {
778 rte_pci_unmap_device(pci_dev);
779 if (pci_dev->kdrv == RTE_PCI_KDRV_UNKNOWN &&
780 (!pci_dev->device.devargs ||
781 pci_dev->device.devargs->bus !=
782 rte_bus_find_by_name("pci"))) {
784 "skip kernel managed virtio device.");
790 VIRTIO_OPS(hw) = &legacy_ops;
794 VIRTIO_OPS(hw)->intr_detect(hw);
799 void vtpci_legacy_ioport_unmap(struct virtio_hw *hw)
801 rte_pci_ioport_unmap(VTPCI_IO(hw));
804 int vtpci_legacy_ioport_map(struct virtio_hw *hw)
806 return rte_pci_ioport_map(VTPCI_DEV(hw), 0, VTPCI_IO(hw));