1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2010-2014 Intel Corporation
6 #ifdef RTE_EXEC_ENV_LINUX
14 #include "virtio_pci.h"
15 #include "virtio_logs.h"
16 #include "virtqueue.h"
19 * Following macros are derived from linux/pci_regs.h, however,
20 * we can't simply include that header here, as there is no such
21 * file for non-Linux platform.
23 #define PCI_CAPABILITY_LIST 0x34
24 #define PCI_CAP_ID_VNDR 0x09
25 #define PCI_CAP_ID_MSIX 0x11
28 * The remaining space is defined by each driver as the per-driver
29 * configuration space.
31 #define VIRTIO_PCI_CONFIG(hw) \
32 (((hw)->use_msix == VIRTIO_MSIX_ENABLED) ? 24 : 20)
35 check_vq_phys_addr_ok(struct virtqueue *vq)
37 /* Virtio PCI device VIRTIO_PCI_QUEUE_PF register is 32bit,
38 * and only accepts 32 bit page frame number.
39 * Check if the allocated physical memory exceeds 16TB.
41 if ((vq->vq_ring_mem + vq->vq_ring_size - 1) >>
42 (VIRTIO_PCI_QUEUE_ADDR_SHIFT + 32)) {
43 PMD_INIT_LOG(ERR, "vring address shouldn't be above 16TB!");
50 #define PCI_MSIX_ENABLE 0x8000
52 static enum virtio_msix_status
53 vtpci_msix_detect(struct rte_pci_device *dev)
58 ret = rte_pci_read_config(dev, &pos, 1, PCI_CAPABILITY_LIST);
61 "failed to read pci capability list, ret %d", ret);
62 return VIRTIO_MSIX_NONE;
68 ret = rte_pci_read_config(dev, cap, sizeof(cap), pos);
69 if (ret != sizeof(cap)) {
71 "failed to read pci cap at pos: %x ret %d",
76 if (cap[0] == PCI_CAP_ID_MSIX) {
79 ret = rte_pci_read_config(dev, &flags, sizeof(flags),
81 if (ret != sizeof(flags)) {
83 "failed to read pci cap at pos:"
84 " %x ret %d", pos + 2, ret);
88 if (flags & PCI_MSIX_ENABLE)
89 return VIRTIO_MSIX_ENABLED;
91 return VIRTIO_MSIX_DISABLED;
97 return VIRTIO_MSIX_NONE;
101 * Since we are in legacy mode:
102 * http://ozlabs.org/~rusty/virtio-spec/virtio-0.9.5.pdf
104 * "Note that this is possible because while the virtio header is PCI (i.e.
105 * little) endian, the device-specific region is encoded in the native endian of
106 * the guest (where such distinction is applicable)."
108 * For powerpc which supports both, qemu supposes that cpu is big endian and
109 * enforces this for the virtio-net stuff.
112 legacy_read_dev_config(struct virtio_hw *hw, size_t offset,
113 void *dst, int length)
115 #ifdef RTE_ARCH_PPC_64
121 rte_pci_ioport_read(VTPCI_IO(hw), dst, size,
122 VIRTIO_PCI_CONFIG(hw) + offset);
123 *(uint32_t *)dst = rte_be_to_cpu_32(*(uint32_t *)dst);
124 } else if (length >= 2) {
126 rte_pci_ioport_read(VTPCI_IO(hw), dst, size,
127 VIRTIO_PCI_CONFIG(hw) + offset);
128 *(uint16_t *)dst = rte_be_to_cpu_16(*(uint16_t *)dst);
131 rte_pci_ioport_read(VTPCI_IO(hw), dst, size,
132 VIRTIO_PCI_CONFIG(hw) + offset);
135 dst = (char *)dst + size;
140 rte_pci_ioport_read(VTPCI_IO(hw), dst, length,
141 VIRTIO_PCI_CONFIG(hw) + offset);
146 legacy_write_dev_config(struct virtio_hw *hw, size_t offset,
147 const void *src, int length)
149 #ifdef RTE_ARCH_PPC_64
159 tmp.u32 = rte_cpu_to_be_32(*(const uint32_t *)src);
160 rte_pci_ioport_write(VTPCI_IO(hw), &tmp.u32, size,
161 VIRTIO_PCI_CONFIG(hw) + offset);
162 } else if (length >= 2) {
164 tmp.u16 = rte_cpu_to_be_16(*(const uint16_t *)src);
165 rte_pci_ioport_write(VTPCI_IO(hw), &tmp.u16, size,
166 VIRTIO_PCI_CONFIG(hw) + offset);
169 rte_pci_ioport_write(VTPCI_IO(hw), src, size,
170 VIRTIO_PCI_CONFIG(hw) + offset);
173 src = (const char *)src + size;
178 rte_pci_ioport_write(VTPCI_IO(hw), src, length,
179 VIRTIO_PCI_CONFIG(hw) + offset);
184 legacy_get_features(struct virtio_hw *hw)
188 rte_pci_ioport_read(VTPCI_IO(hw), &dst, 4, VIRTIO_PCI_HOST_FEATURES);
193 legacy_set_features(struct virtio_hw *hw, uint64_t features)
195 if ((features >> 32) != 0) {
197 "only 32 bit features are allowed for legacy virtio!");
200 rte_pci_ioport_write(VTPCI_IO(hw), &features, 4,
201 VIRTIO_PCI_GUEST_FEATURES);
205 legacy_features_ok(struct virtio_hw *hw __rte_unused)
211 legacy_get_status(struct virtio_hw *hw)
215 rte_pci_ioport_read(VTPCI_IO(hw), &dst, 1, VIRTIO_PCI_STATUS);
220 legacy_set_status(struct virtio_hw *hw, uint8_t status)
222 rte_pci_ioport_write(VTPCI_IO(hw), &status, 1, VIRTIO_PCI_STATUS);
226 legacy_get_isr(struct virtio_hw *hw)
230 rte_pci_ioport_read(VTPCI_IO(hw), &dst, 1, VIRTIO_PCI_ISR);
234 /* Enable one vector (0) for Link State Intrerrupt */
236 legacy_set_config_irq(struct virtio_hw *hw, uint16_t vec)
240 rte_pci_ioport_write(VTPCI_IO(hw), &vec, 2, VIRTIO_MSI_CONFIG_VECTOR);
241 rte_pci_ioport_read(VTPCI_IO(hw), &dst, 2, VIRTIO_MSI_CONFIG_VECTOR);
246 legacy_set_queue_irq(struct virtio_hw *hw, struct virtqueue *vq, uint16_t vec)
250 rte_pci_ioport_write(VTPCI_IO(hw), &vq->vq_queue_index, 2,
251 VIRTIO_PCI_QUEUE_SEL);
252 rte_pci_ioport_write(VTPCI_IO(hw), &vec, 2, VIRTIO_MSI_QUEUE_VECTOR);
253 rte_pci_ioport_read(VTPCI_IO(hw), &dst, 2, VIRTIO_MSI_QUEUE_VECTOR);
258 legacy_get_queue_num(struct virtio_hw *hw, uint16_t queue_id)
262 rte_pci_ioport_write(VTPCI_IO(hw), &queue_id, 2, VIRTIO_PCI_QUEUE_SEL);
263 rte_pci_ioport_read(VTPCI_IO(hw), &dst, 2, VIRTIO_PCI_QUEUE_NUM);
268 legacy_setup_queue(struct virtio_hw *hw, struct virtqueue *vq)
272 if (!check_vq_phys_addr_ok(vq))
275 rte_pci_ioport_write(VTPCI_IO(hw), &vq->vq_queue_index, 2,
276 VIRTIO_PCI_QUEUE_SEL);
277 src = vq->vq_ring_mem >> VIRTIO_PCI_QUEUE_ADDR_SHIFT;
278 rte_pci_ioport_write(VTPCI_IO(hw), &src, 4, VIRTIO_PCI_QUEUE_PFN);
284 legacy_del_queue(struct virtio_hw *hw, struct virtqueue *vq)
288 rte_pci_ioport_write(VTPCI_IO(hw), &vq->vq_queue_index, 2,
289 VIRTIO_PCI_QUEUE_SEL);
290 rte_pci_ioport_write(VTPCI_IO(hw), &src, 4, VIRTIO_PCI_QUEUE_PFN);
294 legacy_notify_queue(struct virtio_hw *hw, struct virtqueue *vq)
296 rte_pci_ioport_write(VTPCI_IO(hw), &vq->vq_queue_index, 2,
297 VIRTIO_PCI_QUEUE_NOTIFY);
301 legacy_intr_detect(struct virtio_hw *hw)
303 hw->use_msix = vtpci_msix_detect(VTPCI_DEV(hw));
307 legacy_dev_close(struct virtio_hw *hw)
309 struct virtio_pci_dev *dev = virtio_pci_get_dev(hw);
311 rte_pci_unmap_device(dev->pci_dev);
312 rte_pci_ioport_unmap(VTPCI_IO(hw));
317 const struct virtio_pci_ops legacy_ops = {
318 .read_dev_cfg = legacy_read_dev_config,
319 .write_dev_cfg = legacy_write_dev_config,
320 .get_status = legacy_get_status,
321 .set_status = legacy_set_status,
322 .get_features = legacy_get_features,
323 .set_features = legacy_set_features,
324 .features_ok = legacy_features_ok,
325 .get_isr = legacy_get_isr,
326 .set_config_irq = legacy_set_config_irq,
327 .set_queue_irq = legacy_set_queue_irq,
328 .get_queue_num = legacy_get_queue_num,
329 .setup_queue = legacy_setup_queue,
330 .del_queue = legacy_del_queue,
331 .notify_queue = legacy_notify_queue,
332 .intr_detect = legacy_intr_detect,
333 .dev_close = legacy_dev_close,
337 io_write64_twopart(uint64_t val, uint32_t *lo, uint32_t *hi)
339 rte_write32(val & ((1ULL << 32) - 1), lo);
340 rte_write32(val >> 32, hi);
344 modern_read_dev_config(struct virtio_hw *hw, size_t offset,
345 void *dst, int length)
349 uint8_t old_gen, new_gen;
352 old_gen = rte_read8(&hw->common_cfg->config_generation);
355 for (i = 0; i < length; i++)
356 *p++ = rte_read8((uint8_t *)hw->dev_cfg + offset + i);
358 new_gen = rte_read8(&hw->common_cfg->config_generation);
359 } while (old_gen != new_gen);
363 modern_write_dev_config(struct virtio_hw *hw, size_t offset,
364 const void *src, int length)
367 const uint8_t *p = src;
369 for (i = 0; i < length; i++)
370 rte_write8((*p++), (((uint8_t *)hw->dev_cfg) + offset + i));
374 modern_get_features(struct virtio_hw *hw)
376 uint32_t features_lo, features_hi;
378 rte_write32(0, &hw->common_cfg->device_feature_select);
379 features_lo = rte_read32(&hw->common_cfg->device_feature);
381 rte_write32(1, &hw->common_cfg->device_feature_select);
382 features_hi = rte_read32(&hw->common_cfg->device_feature);
384 return ((uint64_t)features_hi << 32) | features_lo;
388 modern_set_features(struct virtio_hw *hw, uint64_t features)
390 rte_write32(0, &hw->common_cfg->guest_feature_select);
391 rte_write32(features & ((1ULL << 32) - 1),
392 &hw->common_cfg->guest_feature);
394 rte_write32(1, &hw->common_cfg->guest_feature_select);
395 rte_write32(features >> 32,
396 &hw->common_cfg->guest_feature);
400 modern_features_ok(struct virtio_hw *hw)
402 if (!vtpci_with_feature(hw, VIRTIO_F_VERSION_1)) {
403 PMD_INIT_LOG(ERR, "Version 1+ required with modern devices\n");
411 modern_get_status(struct virtio_hw *hw)
413 return rte_read8(&hw->common_cfg->device_status);
417 modern_set_status(struct virtio_hw *hw, uint8_t status)
419 rte_write8(status, &hw->common_cfg->device_status);
423 modern_get_isr(struct virtio_hw *hw)
425 return rte_read8(hw->isr);
429 modern_set_config_irq(struct virtio_hw *hw, uint16_t vec)
431 rte_write16(vec, &hw->common_cfg->msix_config);
432 return rte_read16(&hw->common_cfg->msix_config);
436 modern_set_queue_irq(struct virtio_hw *hw, struct virtqueue *vq, uint16_t vec)
438 rte_write16(vq->vq_queue_index, &hw->common_cfg->queue_select);
439 rte_write16(vec, &hw->common_cfg->queue_msix_vector);
440 return rte_read16(&hw->common_cfg->queue_msix_vector);
444 modern_get_queue_num(struct virtio_hw *hw, uint16_t queue_id)
446 rte_write16(queue_id, &hw->common_cfg->queue_select);
447 return rte_read16(&hw->common_cfg->queue_size);
451 modern_setup_queue(struct virtio_hw *hw, struct virtqueue *vq)
453 uint64_t desc_addr, avail_addr, used_addr;
456 if (!check_vq_phys_addr_ok(vq))
459 desc_addr = vq->vq_ring_mem;
460 avail_addr = desc_addr + vq->vq_nentries * sizeof(struct vring_desc);
461 used_addr = RTE_ALIGN_CEIL(avail_addr + offsetof(struct vring_avail,
462 ring[vq->vq_nentries]),
463 VIRTIO_PCI_VRING_ALIGN);
465 rte_write16(vq->vq_queue_index, &hw->common_cfg->queue_select);
467 io_write64_twopart(desc_addr, &hw->common_cfg->queue_desc_lo,
468 &hw->common_cfg->queue_desc_hi);
469 io_write64_twopart(avail_addr, &hw->common_cfg->queue_avail_lo,
470 &hw->common_cfg->queue_avail_hi);
471 io_write64_twopart(used_addr, &hw->common_cfg->queue_used_lo,
472 &hw->common_cfg->queue_used_hi);
474 notify_off = rte_read16(&hw->common_cfg->queue_notify_off);
475 vq->notify_addr = (void *)((uint8_t *)hw->notify_base +
476 notify_off * hw->notify_off_multiplier);
478 rte_write16(1, &hw->common_cfg->queue_enable);
480 PMD_INIT_LOG(DEBUG, "queue %u addresses:", vq->vq_queue_index);
481 PMD_INIT_LOG(DEBUG, "\t desc_addr: %" PRIx64, desc_addr);
482 PMD_INIT_LOG(DEBUG, "\t aval_addr: %" PRIx64, avail_addr);
483 PMD_INIT_LOG(DEBUG, "\t used_addr: %" PRIx64, used_addr);
484 PMD_INIT_LOG(DEBUG, "\t notify addr: %p (notify offset: %u)",
485 vq->notify_addr, notify_off);
491 modern_del_queue(struct virtio_hw *hw, struct virtqueue *vq)
493 rte_write16(vq->vq_queue_index, &hw->common_cfg->queue_select);
495 io_write64_twopart(0, &hw->common_cfg->queue_desc_lo,
496 &hw->common_cfg->queue_desc_hi);
497 io_write64_twopart(0, &hw->common_cfg->queue_avail_lo,
498 &hw->common_cfg->queue_avail_hi);
499 io_write64_twopart(0, &hw->common_cfg->queue_used_lo,
500 &hw->common_cfg->queue_used_hi);
502 rte_write16(0, &hw->common_cfg->queue_enable);
506 modern_notify_queue(struct virtio_hw *hw, struct virtqueue *vq)
508 uint32_t notify_data;
510 if (!vtpci_with_feature(hw, VIRTIO_F_NOTIFICATION_DATA)) {
511 rte_write16(vq->vq_queue_index, vq->notify_addr);
515 if (vtpci_with_feature(hw, VIRTIO_F_RING_PACKED)) {
517 * Bit[0:15]: vq queue index
518 * Bit[16:30]: avail index
519 * Bit[31]: avail wrap counter
521 notify_data = ((uint32_t)(!!(vq->vq_packed.cached_flags &
522 VRING_PACKED_DESC_F_AVAIL)) << 31) |
523 ((uint32_t)vq->vq_avail_idx << 16) |
527 * Bit[0:15]: vq queue index
528 * Bit[16:31]: avail index
530 notify_data = ((uint32_t)vq->vq_avail_idx << 16) |
533 rte_write32(notify_data, vq->notify_addr);
539 modern_intr_detect(struct virtio_hw *hw)
541 hw->use_msix = vtpci_msix_detect(VTPCI_DEV(hw));
545 modern_dev_close(struct virtio_hw *hw)
547 struct virtio_pci_dev *dev = virtio_pci_get_dev(hw);
549 rte_pci_unmap_device(dev->pci_dev);
554 const struct virtio_pci_ops modern_ops = {
555 .read_dev_cfg = modern_read_dev_config,
556 .write_dev_cfg = modern_write_dev_config,
557 .get_status = modern_get_status,
558 .set_status = modern_set_status,
559 .get_features = modern_get_features,
560 .set_features = modern_set_features,
561 .features_ok = modern_features_ok,
562 .get_isr = modern_get_isr,
563 .set_config_irq = modern_set_config_irq,
564 .set_queue_irq = modern_set_queue_irq,
565 .get_queue_num = modern_get_queue_num,
566 .setup_queue = modern_setup_queue,
567 .del_queue = modern_del_queue,
568 .notify_queue = modern_notify_queue,
569 .intr_detect = modern_intr_detect,
570 .dev_close = modern_dev_close,
575 vtpci_read_dev_config(struct virtio_hw *hw, size_t offset,
576 void *dst, int length)
578 VTPCI_OPS(hw)->read_dev_cfg(hw, offset, dst, length);
582 vtpci_write_dev_config(struct virtio_hw *hw, size_t offset,
583 const void *src, int length)
585 VTPCI_OPS(hw)->write_dev_cfg(hw, offset, src, length);
589 vtpci_negotiate_features(struct virtio_hw *hw, uint64_t host_features)
594 * Limit negotiated features to what the driver, virtqueue, and
597 features = host_features & hw->guest_features;
598 VTPCI_OPS(hw)->set_features(hw, features);
604 vtpci_reset(struct virtio_hw *hw)
606 VTPCI_OPS(hw)->set_status(hw, VIRTIO_CONFIG_STATUS_RESET);
607 /* flush status write */
608 VTPCI_OPS(hw)->get_status(hw);
612 vtpci_reinit_complete(struct virtio_hw *hw)
614 vtpci_set_status(hw, VIRTIO_CONFIG_STATUS_DRIVER_OK);
618 vtpci_set_status(struct virtio_hw *hw, uint8_t status)
620 if (status != VIRTIO_CONFIG_STATUS_RESET)
621 status |= VTPCI_OPS(hw)->get_status(hw);
623 VTPCI_OPS(hw)->set_status(hw, status);
627 vtpci_get_status(struct virtio_hw *hw)
629 return VTPCI_OPS(hw)->get_status(hw);
633 vtpci_isr(struct virtio_hw *hw)
635 return VTPCI_OPS(hw)->get_isr(hw);
639 get_cfg_addr(struct rte_pci_device *dev, struct virtio_pci_cap *cap)
641 uint8_t bar = cap->bar;
642 uint32_t length = cap->length;
643 uint32_t offset = cap->offset;
646 if (bar >= PCI_MAX_RESOURCE) {
647 PMD_INIT_LOG(ERR, "invalid bar: %u", bar);
651 if (offset + length < offset) {
652 PMD_INIT_LOG(ERR, "offset(%u) + length(%u) overflows",
657 if (offset + length > dev->mem_resource[bar].len) {
659 "invalid cap: overflows bar space: %u > %" PRIu64,
660 offset + length, dev->mem_resource[bar].len);
664 base = dev->mem_resource[bar].addr;
666 PMD_INIT_LOG(ERR, "bar %u base addr is NULL", bar);
670 return base + offset;
674 virtio_read_caps(struct rte_pci_device *dev, struct virtio_hw *hw)
677 struct virtio_pci_cap cap;
680 if (rte_pci_map_device(dev)) {
681 PMD_INIT_LOG(DEBUG, "failed to map pci device!");
685 ret = rte_pci_read_config(dev, &pos, 1, PCI_CAPABILITY_LIST);
688 "failed to read pci capability list, ret %d", ret);
693 ret = rte_pci_read_config(dev, &cap, 2, pos);
696 "failed to read pci cap at pos: %x ret %d",
701 if (cap.cap_vndr == PCI_CAP_ID_MSIX) {
702 /* Transitional devices would also have this capability,
703 * that's why we also check if msix is enabled.
704 * 1st byte is cap ID; 2nd byte is the position of next
705 * cap; next two bytes are the flags.
709 ret = rte_pci_read_config(dev, &flags, sizeof(flags),
711 if (ret != sizeof(flags)) {
713 "failed to read pci cap at pos:"
714 " %x ret %d", pos + 2, ret);
718 if (flags & PCI_MSIX_ENABLE)
719 hw->use_msix = VIRTIO_MSIX_ENABLED;
721 hw->use_msix = VIRTIO_MSIX_DISABLED;
724 if (cap.cap_vndr != PCI_CAP_ID_VNDR) {
726 "[%2x] skipping non VNDR cap id: %02x",
731 ret = rte_pci_read_config(dev, &cap, sizeof(cap), pos);
732 if (ret != sizeof(cap)) {
734 "failed to read pci cap at pos: %x ret %d",
740 "[%2x] cfg type: %u, bar: %u, offset: %04x, len: %u",
741 pos, cap.cfg_type, cap.bar, cap.offset, cap.length);
743 switch (cap.cfg_type) {
744 case VIRTIO_PCI_CAP_COMMON_CFG:
745 hw->common_cfg = get_cfg_addr(dev, &cap);
747 case VIRTIO_PCI_CAP_NOTIFY_CFG:
748 ret = rte_pci_read_config(dev,
749 &hw->notify_off_multiplier,
750 4, pos + sizeof(cap));
753 "failed to read notify_off_multiplier, ret %d",
756 hw->notify_base = get_cfg_addr(dev, &cap);
758 case VIRTIO_PCI_CAP_DEVICE_CFG:
759 hw->dev_cfg = get_cfg_addr(dev, &cap);
761 case VIRTIO_PCI_CAP_ISR_CFG:
762 hw->isr = get_cfg_addr(dev, &cap);
770 if (hw->common_cfg == NULL || hw->notify_base == NULL ||
771 hw->dev_cfg == NULL || hw->isr == NULL) {
772 PMD_INIT_LOG(INFO, "no modern virtio pci device found.");
776 PMD_INIT_LOG(INFO, "found modern virtio pci device.");
778 PMD_INIT_LOG(DEBUG, "common cfg mapped at: %p", hw->common_cfg);
779 PMD_INIT_LOG(DEBUG, "device cfg mapped at: %p", hw->dev_cfg);
780 PMD_INIT_LOG(DEBUG, "isr cfg mapped at: %p", hw->isr);
781 PMD_INIT_LOG(DEBUG, "notify base: %p, notify off multiplier: %u",
782 hw->notify_base, hw->notify_off_multiplier);
789 * if there is error mapping with VFIO/UIO.
790 * if port map error when driver type is KDRV_NONE.
791 * if marked as allowed but driver type is KDRV_UNKNOWN.
792 * Return 1 if kernel driver is managing the device.
793 * Return 0 on success.
796 vtpci_init(struct rte_pci_device *pci_dev, struct virtio_pci_dev *dev)
798 struct virtio_hw *hw = &dev->hw;
800 RTE_BUILD_BUG_ON(offsetof(struct virtio_pci_dev, hw) != 0);
802 dev->pci_dev = pci_dev;
805 * Try if we can succeed reading virtio pci caps, which exists
806 * only on modern pci device. If failed, we fallback to legacy
809 if (virtio_read_caps(pci_dev, hw) == 0) {
810 PMD_INIT_LOG(INFO, "modern virtio pci detected.");
811 virtio_hw_internal[hw->port_id].vtpci_ops = &modern_ops;
812 hw->bus_type = VIRTIO_BUS_PCI_MODERN;
817 PMD_INIT_LOG(INFO, "trying with legacy virtio pci.");
818 if (rte_pci_ioport_map(pci_dev, 0, VTPCI_IO(hw)) < 0) {
819 rte_pci_unmap_device(pci_dev);
820 if (pci_dev->kdrv == RTE_PCI_KDRV_UNKNOWN &&
821 (!pci_dev->device.devargs ||
822 pci_dev->device.devargs->bus !=
823 rte_bus_find_by_name("pci"))) {
825 "skip kernel managed virtio device.");
831 virtio_hw_internal[hw->port_id].vtpci_ops = &legacy_ops;
832 hw->bus_type = VIRTIO_BUS_PCI_LEGACY;
836 VTPCI_OPS(hw)->intr_detect(hw);