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35 #ifdef RTE_EXEC_ENV_LINUXAPP
42 #include "virtio_pci.h"
43 #include "virtio_logs.h"
44 #include "virtqueue.h"
47 * Following macros are derived from linux/pci_regs.h, however,
48 * we can't simply include that header here, as there is no such
49 * file for non-Linux platform.
51 #define PCI_CAPABILITY_LIST 0x34
52 #define PCI_CAP_ID_VNDR 0x09
53 #define PCI_CAP_ID_MSIX 0x11
56 * The remaining space is defined by each driver as the per-driver
57 * configuration space.
59 #define VIRTIO_PCI_CONFIG(hw) (((hw)->use_msix) ? 24 : 20)
62 check_vq_phys_addr_ok(struct virtqueue *vq)
64 /* Virtio PCI device VIRTIO_PCI_QUEUE_PF register is 32bit,
65 * and only accepts 32 bit page frame number.
66 * Check if the allocated physical memory exceeds 16TB.
68 if ((vq->vq_ring_mem + vq->vq_ring_size - 1) >>
69 (VIRTIO_PCI_QUEUE_ADDR_SHIFT + 32)) {
70 PMD_INIT_LOG(ERR, "vring address shouldn't be above 16TB!");
78 * Since we are in legacy mode:
79 * http://ozlabs.org/~rusty/virtio-spec/virtio-0.9.5.pdf
81 * "Note that this is possible because while the virtio header is PCI (i.e.
82 * little) endian, the device-specific region is encoded in the native endian of
83 * the guest (where such distinction is applicable)."
85 * For powerpc which supports both, qemu supposes that cpu is big endian and
86 * enforces this for the virtio-net stuff.
89 legacy_read_dev_config(struct virtio_hw *hw, size_t offset,
90 void *dst, int length)
92 #ifdef RTE_ARCH_PPC_64
98 rte_eal_pci_ioport_read(VTPCI_IO(hw), dst, size,
99 VIRTIO_PCI_CONFIG(hw) + offset);
100 *(uint32_t *)dst = rte_be_to_cpu_32(*(uint32_t *)dst);
101 } else if (length >= 2) {
103 rte_eal_pci_ioport_read(VTPCI_IO(hw), dst, size,
104 VIRTIO_PCI_CONFIG(hw) + offset);
105 *(uint16_t *)dst = rte_be_to_cpu_16(*(uint16_t *)dst);
108 rte_eal_pci_ioport_read(VTPCI_IO(hw), dst, size,
109 VIRTIO_PCI_CONFIG(hw) + offset);
112 dst = (char *)dst + size;
117 rte_eal_pci_ioport_read(VTPCI_IO(hw), dst, length,
118 VIRTIO_PCI_CONFIG(hw) + offset);
123 legacy_write_dev_config(struct virtio_hw *hw, size_t offset,
124 const void *src, int length)
126 #ifdef RTE_ARCH_PPC_64
136 tmp.u32 = rte_cpu_to_be_32(*(const uint32_t *)src);
137 rte_eal_pci_ioport_write(VTPCI_IO(hw), &tmp.u32, size,
138 VIRTIO_PCI_CONFIG(hw) + offset);
139 } else if (length >= 2) {
141 tmp.u16 = rte_cpu_to_be_16(*(const uint16_t *)src);
142 rte_eal_pci_ioport_write(VTPCI_IO(hw), &tmp.u16, size,
143 VIRTIO_PCI_CONFIG(hw) + offset);
146 rte_eal_pci_ioport_write(VTPCI_IO(hw), src, size,
147 VIRTIO_PCI_CONFIG(hw) + offset);
150 src = (const char *)src + size;
155 rte_eal_pci_ioport_write(VTPCI_IO(hw), src, length,
156 VIRTIO_PCI_CONFIG(hw) + offset);
161 legacy_get_features(struct virtio_hw *hw)
165 rte_eal_pci_ioport_read(VTPCI_IO(hw), &dst, 4,
166 VIRTIO_PCI_HOST_FEATURES);
171 legacy_set_features(struct virtio_hw *hw, uint64_t features)
173 if ((features >> 32) != 0) {
175 "only 32 bit features are allowed for legacy virtio!");
178 rte_eal_pci_ioport_write(VTPCI_IO(hw), &features, 4,
179 VIRTIO_PCI_GUEST_FEATURES);
183 legacy_get_status(struct virtio_hw *hw)
187 rte_eal_pci_ioport_read(VTPCI_IO(hw), &dst, 1, VIRTIO_PCI_STATUS);
192 legacy_set_status(struct virtio_hw *hw, uint8_t status)
194 rte_eal_pci_ioport_write(VTPCI_IO(hw), &status, 1, VIRTIO_PCI_STATUS);
198 legacy_reset(struct virtio_hw *hw)
200 legacy_set_status(hw, VIRTIO_CONFIG_STATUS_RESET);
204 legacy_get_isr(struct virtio_hw *hw)
208 rte_eal_pci_ioport_read(VTPCI_IO(hw), &dst, 1, VIRTIO_PCI_ISR);
212 /* Enable one vector (0) for Link State Intrerrupt */
214 legacy_set_config_irq(struct virtio_hw *hw, uint16_t vec)
218 rte_eal_pci_ioport_write(VTPCI_IO(hw), &vec, 2,
219 VIRTIO_MSI_CONFIG_VECTOR);
220 rte_eal_pci_ioport_read(VTPCI_IO(hw), &dst, 2,
221 VIRTIO_MSI_CONFIG_VECTOR);
226 legacy_set_queue_irq(struct virtio_hw *hw, struct virtqueue *vq, uint16_t vec)
230 rte_eal_pci_ioport_write(VTPCI_IO(hw), &vq->vq_queue_index, 2,
231 VIRTIO_PCI_QUEUE_SEL);
232 rte_eal_pci_ioport_write(VTPCI_IO(hw), &vec, 2,
233 VIRTIO_MSI_QUEUE_VECTOR);
234 rte_eal_pci_ioport_read(VTPCI_IO(hw), &dst, 2, VIRTIO_MSI_QUEUE_VECTOR);
239 legacy_get_queue_num(struct virtio_hw *hw, uint16_t queue_id)
243 rte_eal_pci_ioport_write(VTPCI_IO(hw), &queue_id, 2,
244 VIRTIO_PCI_QUEUE_SEL);
245 rte_eal_pci_ioport_read(VTPCI_IO(hw), &dst, 2, VIRTIO_PCI_QUEUE_NUM);
250 legacy_setup_queue(struct virtio_hw *hw, struct virtqueue *vq)
254 if (!check_vq_phys_addr_ok(vq))
257 rte_eal_pci_ioport_write(VTPCI_IO(hw), &vq->vq_queue_index, 2,
258 VIRTIO_PCI_QUEUE_SEL);
259 src = vq->vq_ring_mem >> VIRTIO_PCI_QUEUE_ADDR_SHIFT;
260 rte_eal_pci_ioport_write(VTPCI_IO(hw), &src, 4, VIRTIO_PCI_QUEUE_PFN);
266 legacy_del_queue(struct virtio_hw *hw, struct virtqueue *vq)
270 rte_eal_pci_ioport_write(VTPCI_IO(hw), &vq->vq_queue_index, 2,
271 VIRTIO_PCI_QUEUE_SEL);
272 rte_eal_pci_ioport_write(VTPCI_IO(hw), &src, 4, VIRTIO_PCI_QUEUE_PFN);
276 legacy_notify_queue(struct virtio_hw *hw, struct virtqueue *vq)
278 rte_eal_pci_ioport_write(VTPCI_IO(hw), &vq->vq_queue_index, 2,
279 VIRTIO_PCI_QUEUE_NOTIFY);
282 #ifdef RTE_EXEC_ENV_LINUXAPP
284 legacy_virtio_has_msix(const struct rte_pci_addr *loc)
287 char dirname[PATH_MAX];
289 snprintf(dirname, sizeof(dirname),
290 "%s/" PCI_PRI_FMT "/msi_irqs", pci_get_sysfs_path(),
291 loc->domain, loc->bus, loc->devid, loc->function);
293 d = opendir(dirname);
301 legacy_virtio_has_msix(const struct rte_pci_addr *loc __rte_unused)
303 /* nic_uio does not enable interrupts, return 0 (false). */
308 const struct virtio_pci_ops legacy_ops = {
309 .read_dev_cfg = legacy_read_dev_config,
310 .write_dev_cfg = legacy_write_dev_config,
311 .reset = legacy_reset,
312 .get_status = legacy_get_status,
313 .set_status = legacy_set_status,
314 .get_features = legacy_get_features,
315 .set_features = legacy_set_features,
316 .get_isr = legacy_get_isr,
317 .set_config_irq = legacy_set_config_irq,
318 .set_queue_irq = legacy_set_queue_irq,
319 .get_queue_num = legacy_get_queue_num,
320 .setup_queue = legacy_setup_queue,
321 .del_queue = legacy_del_queue,
322 .notify_queue = legacy_notify_queue,
326 io_write64_twopart(uint64_t val, uint32_t *lo, uint32_t *hi)
328 rte_write32(val & ((1ULL << 32) - 1), lo);
329 rte_write32(val >> 32, hi);
333 modern_read_dev_config(struct virtio_hw *hw, size_t offset,
334 void *dst, int length)
338 uint8_t old_gen, new_gen;
341 old_gen = rte_read8(&hw->common_cfg->config_generation);
344 for (i = 0; i < length; i++)
345 *p++ = rte_read8((uint8_t *)hw->dev_cfg + offset + i);
347 new_gen = rte_read8(&hw->common_cfg->config_generation);
348 } while (old_gen != new_gen);
352 modern_write_dev_config(struct virtio_hw *hw, size_t offset,
353 const void *src, int length)
356 const uint8_t *p = src;
358 for (i = 0; i < length; i++)
359 rte_write8((*p++), (((uint8_t *)hw->dev_cfg) + offset + i));
363 modern_get_features(struct virtio_hw *hw)
365 uint32_t features_lo, features_hi;
367 rte_write32(0, &hw->common_cfg->device_feature_select);
368 features_lo = rte_read32(&hw->common_cfg->device_feature);
370 rte_write32(1, &hw->common_cfg->device_feature_select);
371 features_hi = rte_read32(&hw->common_cfg->device_feature);
373 return ((uint64_t)features_hi << 32) | features_lo;
377 modern_set_features(struct virtio_hw *hw, uint64_t features)
379 rte_write32(0, &hw->common_cfg->guest_feature_select);
380 rte_write32(features & ((1ULL << 32) - 1),
381 &hw->common_cfg->guest_feature);
383 rte_write32(1, &hw->common_cfg->guest_feature_select);
384 rte_write32(features >> 32,
385 &hw->common_cfg->guest_feature);
389 modern_get_status(struct virtio_hw *hw)
391 return rte_read8(&hw->common_cfg->device_status);
395 modern_set_status(struct virtio_hw *hw, uint8_t status)
397 rte_write8(status, &hw->common_cfg->device_status);
401 modern_reset(struct virtio_hw *hw)
403 modern_set_status(hw, VIRTIO_CONFIG_STATUS_RESET);
404 modern_get_status(hw);
408 modern_get_isr(struct virtio_hw *hw)
410 return rte_read8(hw->isr);
414 modern_set_config_irq(struct virtio_hw *hw, uint16_t vec)
416 rte_write16(vec, &hw->common_cfg->msix_config);
417 return rte_read16(&hw->common_cfg->msix_config);
421 modern_set_queue_irq(struct virtio_hw *hw, struct virtqueue *vq, uint16_t vec)
423 rte_write16(vq->vq_queue_index, &hw->common_cfg->queue_select);
424 rte_write16(vec, &hw->common_cfg->queue_msix_vector);
425 return rte_read16(&hw->common_cfg->queue_msix_vector);
429 modern_get_queue_num(struct virtio_hw *hw, uint16_t queue_id)
431 rte_write16(queue_id, &hw->common_cfg->queue_select);
432 return rte_read16(&hw->common_cfg->queue_size);
436 modern_setup_queue(struct virtio_hw *hw, struct virtqueue *vq)
438 uint64_t desc_addr, avail_addr, used_addr;
441 if (!check_vq_phys_addr_ok(vq))
444 desc_addr = vq->vq_ring_mem;
445 avail_addr = desc_addr + vq->vq_nentries * sizeof(struct vring_desc);
446 used_addr = RTE_ALIGN_CEIL(avail_addr + offsetof(struct vring_avail,
447 ring[vq->vq_nentries]),
448 VIRTIO_PCI_VRING_ALIGN);
450 rte_write16(vq->vq_queue_index, &hw->common_cfg->queue_select);
452 io_write64_twopart(desc_addr, &hw->common_cfg->queue_desc_lo,
453 &hw->common_cfg->queue_desc_hi);
454 io_write64_twopart(avail_addr, &hw->common_cfg->queue_avail_lo,
455 &hw->common_cfg->queue_avail_hi);
456 io_write64_twopart(used_addr, &hw->common_cfg->queue_used_lo,
457 &hw->common_cfg->queue_used_hi);
459 notify_off = rte_read16(&hw->common_cfg->queue_notify_off);
460 vq->notify_addr = (void *)((uint8_t *)hw->notify_base +
461 notify_off * hw->notify_off_multiplier);
463 rte_write16(1, &hw->common_cfg->queue_enable);
465 PMD_INIT_LOG(DEBUG, "queue %u addresses:", vq->vq_queue_index);
466 PMD_INIT_LOG(DEBUG, "\t desc_addr: %" PRIx64, desc_addr);
467 PMD_INIT_LOG(DEBUG, "\t aval_addr: %" PRIx64, avail_addr);
468 PMD_INIT_LOG(DEBUG, "\t used_addr: %" PRIx64, used_addr);
469 PMD_INIT_LOG(DEBUG, "\t notify addr: %p (notify offset: %u)",
470 vq->notify_addr, notify_off);
476 modern_del_queue(struct virtio_hw *hw, struct virtqueue *vq)
478 rte_write16(vq->vq_queue_index, &hw->common_cfg->queue_select);
480 io_write64_twopart(0, &hw->common_cfg->queue_desc_lo,
481 &hw->common_cfg->queue_desc_hi);
482 io_write64_twopart(0, &hw->common_cfg->queue_avail_lo,
483 &hw->common_cfg->queue_avail_hi);
484 io_write64_twopart(0, &hw->common_cfg->queue_used_lo,
485 &hw->common_cfg->queue_used_hi);
487 rte_write16(0, &hw->common_cfg->queue_enable);
491 modern_notify_queue(struct virtio_hw *hw __rte_unused, struct virtqueue *vq)
493 rte_write16(vq->vq_queue_index, vq->notify_addr);
496 const struct virtio_pci_ops modern_ops = {
497 .read_dev_cfg = modern_read_dev_config,
498 .write_dev_cfg = modern_write_dev_config,
499 .reset = modern_reset,
500 .get_status = modern_get_status,
501 .set_status = modern_set_status,
502 .get_features = modern_get_features,
503 .set_features = modern_set_features,
504 .get_isr = modern_get_isr,
505 .set_config_irq = modern_set_config_irq,
506 .set_queue_irq = modern_set_queue_irq,
507 .get_queue_num = modern_get_queue_num,
508 .setup_queue = modern_setup_queue,
509 .del_queue = modern_del_queue,
510 .notify_queue = modern_notify_queue,
515 vtpci_read_dev_config(struct virtio_hw *hw, size_t offset,
516 void *dst, int length)
518 VTPCI_OPS(hw)->read_dev_cfg(hw, offset, dst, length);
522 vtpci_write_dev_config(struct virtio_hw *hw, size_t offset,
523 const void *src, int length)
525 VTPCI_OPS(hw)->write_dev_cfg(hw, offset, src, length);
529 vtpci_negotiate_features(struct virtio_hw *hw, uint64_t host_features)
534 * Limit negotiated features to what the driver, virtqueue, and
537 features = host_features & hw->guest_features;
538 VTPCI_OPS(hw)->set_features(hw, features);
544 vtpci_reset(struct virtio_hw *hw)
546 VTPCI_OPS(hw)->set_status(hw, VIRTIO_CONFIG_STATUS_RESET);
547 /* flush status write */
548 VTPCI_OPS(hw)->get_status(hw);
552 vtpci_reinit_complete(struct virtio_hw *hw)
554 vtpci_set_status(hw, VIRTIO_CONFIG_STATUS_DRIVER_OK);
558 vtpci_set_status(struct virtio_hw *hw, uint8_t status)
560 if (status != VIRTIO_CONFIG_STATUS_RESET)
561 status |= VTPCI_OPS(hw)->get_status(hw);
563 VTPCI_OPS(hw)->set_status(hw, status);
567 vtpci_get_status(struct virtio_hw *hw)
569 return VTPCI_OPS(hw)->get_status(hw);
573 vtpci_isr(struct virtio_hw *hw)
575 return VTPCI_OPS(hw)->get_isr(hw);
579 get_cfg_addr(struct rte_pci_device *dev, struct virtio_pci_cap *cap)
581 uint8_t bar = cap->bar;
582 uint32_t length = cap->length;
583 uint32_t offset = cap->offset;
587 PMD_INIT_LOG(ERR, "invalid bar: %u", bar);
591 if (offset + length < offset) {
592 PMD_INIT_LOG(ERR, "offset(%u) + length(%u) overflows",
597 if (offset + length > dev->mem_resource[bar].len) {
599 "invalid cap: overflows bar space: %u > %" PRIu64,
600 offset + length, dev->mem_resource[bar].len);
604 base = dev->mem_resource[bar].addr;
606 PMD_INIT_LOG(ERR, "bar %u base addr is NULL", bar);
610 return base + offset;
614 virtio_read_caps(struct rte_pci_device *dev, struct virtio_hw *hw)
617 struct virtio_pci_cap cap;
620 if (rte_eal_pci_map_device(dev)) {
621 PMD_INIT_LOG(DEBUG, "failed to map pci device!");
625 ret = rte_eal_pci_read_config(dev, &pos, 1, PCI_CAPABILITY_LIST);
627 PMD_INIT_LOG(DEBUG, "failed to read pci capability list");
632 ret = rte_eal_pci_read_config(dev, &cap, sizeof(cap), pos);
635 "failed to read pci cap at pos: %x", pos);
639 if (cap.cap_vndr == PCI_CAP_ID_MSIX)
642 if (cap.cap_vndr != PCI_CAP_ID_VNDR) {
644 "[%2x] skipping non VNDR cap id: %02x",
650 "[%2x] cfg type: %u, bar: %u, offset: %04x, len: %u",
651 pos, cap.cfg_type, cap.bar, cap.offset, cap.length);
653 switch (cap.cfg_type) {
654 case VIRTIO_PCI_CAP_COMMON_CFG:
655 hw->common_cfg = get_cfg_addr(dev, &cap);
657 case VIRTIO_PCI_CAP_NOTIFY_CFG:
658 rte_eal_pci_read_config(dev, &hw->notify_off_multiplier,
659 4, pos + sizeof(cap));
660 hw->notify_base = get_cfg_addr(dev, &cap);
662 case VIRTIO_PCI_CAP_DEVICE_CFG:
663 hw->dev_cfg = get_cfg_addr(dev, &cap);
665 case VIRTIO_PCI_CAP_ISR_CFG:
666 hw->isr = get_cfg_addr(dev, &cap);
674 if (hw->common_cfg == NULL || hw->notify_base == NULL ||
675 hw->dev_cfg == NULL || hw->isr == NULL) {
676 PMD_INIT_LOG(INFO, "no modern virtio pci device found.");
680 PMD_INIT_LOG(INFO, "found modern virtio pci device.");
682 PMD_INIT_LOG(DEBUG, "common cfg mapped at: %p", hw->common_cfg);
683 PMD_INIT_LOG(DEBUG, "device cfg mapped at: %p", hw->dev_cfg);
684 PMD_INIT_LOG(DEBUG, "isr cfg mapped at: %p", hw->isr);
685 PMD_INIT_LOG(DEBUG, "notify base: %p, notify off multiplier: %u",
686 hw->notify_base, hw->notify_off_multiplier);
693 * if there is error mapping with VFIO/UIO.
694 * if port map error when driver type is KDRV_NONE.
695 * if whitelisted but driver type is KDRV_UNKNOWN.
696 * Return 1 if kernel driver is managing the device.
697 * Return 0 on success.
700 vtpci_init(struct rte_pci_device *dev, struct virtio_hw *hw)
703 * Try if we can succeed reading virtio pci caps, which exists
704 * only on modern pci device. If failed, we fallback to legacy
707 if (virtio_read_caps(dev, hw) == 0) {
708 PMD_INIT_LOG(INFO, "modern virtio pci detected.");
709 virtio_hw_internal[hw->port_id].vtpci_ops = &modern_ops;
714 PMD_INIT_LOG(INFO, "trying with legacy virtio pci.");
715 if (rte_eal_pci_ioport_map(dev, 0, VTPCI_IO(hw)) < 0) {
716 if (dev->kdrv == RTE_KDRV_UNKNOWN &&
717 (!dev->device.devargs ||
718 dev->device.devargs->type !=
719 RTE_DEVTYPE_WHITELISTED_PCI)) {
721 "skip kernel managed virtio device.");
727 virtio_hw_internal[hw->port_id].vtpci_ops = &legacy_ops;
728 hw->use_msix = legacy_virtio_has_msix(&dev->addr);