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35 #ifdef RTE_EXEC_ENV_LINUXAPP
40 #include "virtio_pci.h"
41 #include "virtio_logs.h"
42 #include "virtqueue.h"
45 * Following macros are derived from linux/pci_regs.h, however,
46 * we can't simply include that header here, as there is no such
47 * file for non-Linux platform.
49 #define PCI_CAPABILITY_LIST 0x34
50 #define PCI_CAP_ID_VNDR 0x09
53 * The remaining space is defined by each driver as the per-driver
54 * configuration space.
56 #define VIRTIO_PCI_CONFIG(hw) (((hw)->use_msix) ? 24 : 20)
59 check_vq_phys_addr_ok(struct virtqueue *vq)
61 /* Virtio PCI device VIRTIO_PCI_QUEUE_PF register is 32bit,
62 * and only accepts 32 bit page frame number.
63 * Check if the allocated physical memory exceeds 16TB.
65 if ((vq->vq_ring_mem + vq->vq_ring_size - 1) >>
66 (VIRTIO_PCI_QUEUE_ADDR_SHIFT + 32)) {
67 PMD_INIT_LOG(ERR, "vring address shouldn't be above 16TB!");
75 * Since we are in legacy mode:
76 * http://ozlabs.org/~rusty/virtio-spec/virtio-0.9.5.pdf
78 * "Note that this is possible because while the virtio header is PCI (i.e.
79 * little) endian, the device-specific region is encoded in the native endian of
80 * the guest (where such distinction is applicable)."
82 * For powerpc which supports both, qemu supposes that cpu is big endian and
83 * enforces this for the virtio-net stuff.
86 legacy_read_dev_config(struct virtio_hw *hw, size_t offset,
87 void *dst, int length)
89 #ifdef RTE_ARCH_PPC_64
95 rte_eal_pci_ioport_read(VTPCI_IO(hw), dst, size,
96 VIRTIO_PCI_CONFIG(hw) + offset);
97 *(uint32_t *)dst = rte_be_to_cpu_32(*(uint32_t *)dst);
98 } else if (length >= 2) {
100 rte_eal_pci_ioport_read(VTPCI_IO(hw), dst, size,
101 VIRTIO_PCI_CONFIG(hw) + offset);
102 *(uint16_t *)dst = rte_be_to_cpu_16(*(uint16_t *)dst);
105 rte_eal_pci_ioport_read(VTPCI_IO(hw), dst, size,
106 VIRTIO_PCI_CONFIG(hw) + offset);
109 dst = (char *)dst + size;
114 rte_eal_pci_ioport_read(VTPCI_IO(hw), dst, length,
115 VIRTIO_PCI_CONFIG(hw) + offset);
120 legacy_write_dev_config(struct virtio_hw *hw, size_t offset,
121 const void *src, int length)
123 #ifdef RTE_ARCH_PPC_64
133 tmp.u32 = rte_cpu_to_be_32(*(const uint32_t *)src);
134 rte_eal_pci_ioport_write(VTPCI_IO(hw), &tmp.u32, size,
135 VIRTIO_PCI_CONFIG(hw) + offset);
136 } else if (length >= 2) {
138 tmp.u16 = rte_cpu_to_be_16(*(const uint16_t *)src);
139 rte_eal_pci_ioport_write(VTPCI_IO(hw), &tmp.u16, size,
140 VIRTIO_PCI_CONFIG(hw) + offset);
143 rte_eal_pci_ioport_write(VTPCI_IO(hw), src, size,
144 VIRTIO_PCI_CONFIG(hw) + offset);
147 src = (const char *)src + size;
152 rte_eal_pci_ioport_write(VTPCI_IO(hw), src, length,
153 VIRTIO_PCI_CONFIG(hw) + offset);
158 legacy_get_features(struct virtio_hw *hw)
162 rte_eal_pci_ioport_read(VTPCI_IO(hw), &dst, 4,
163 VIRTIO_PCI_HOST_FEATURES);
168 legacy_set_features(struct virtio_hw *hw, uint64_t features)
170 if ((features >> 32) != 0) {
172 "only 32 bit features are allowed for legacy virtio!");
175 rte_eal_pci_ioport_write(VTPCI_IO(hw), &features, 4,
176 VIRTIO_PCI_GUEST_FEATURES);
180 legacy_get_status(struct virtio_hw *hw)
184 rte_eal_pci_ioport_read(VTPCI_IO(hw), &dst, 1, VIRTIO_PCI_STATUS);
189 legacy_set_status(struct virtio_hw *hw, uint8_t status)
191 rte_eal_pci_ioport_write(VTPCI_IO(hw), &status, 1, VIRTIO_PCI_STATUS);
195 legacy_reset(struct virtio_hw *hw)
197 legacy_set_status(hw, VIRTIO_CONFIG_STATUS_RESET);
201 legacy_get_isr(struct virtio_hw *hw)
205 rte_eal_pci_ioport_read(VTPCI_IO(hw), &dst, 1, VIRTIO_PCI_ISR);
209 /* Enable one vector (0) for Link State Intrerrupt */
211 legacy_set_config_irq(struct virtio_hw *hw, uint16_t vec)
215 rte_eal_pci_ioport_write(VTPCI_IO(hw), &vec, 2,
216 VIRTIO_MSI_CONFIG_VECTOR);
217 rte_eal_pci_ioport_read(VTPCI_IO(hw), &dst, 2,
218 VIRTIO_MSI_CONFIG_VECTOR);
223 legacy_set_queue_irq(struct virtio_hw *hw, struct virtqueue *vq, uint16_t vec)
227 rte_eal_pci_ioport_write(VTPCI_IO(hw), &vq->vq_queue_index, 2,
228 VIRTIO_PCI_QUEUE_SEL);
229 rte_eal_pci_ioport_write(VTPCI_IO(hw), &vec, 2,
230 VIRTIO_MSI_QUEUE_VECTOR);
231 rte_eal_pci_ioport_read(VTPCI_IO(hw), &dst, 2, VIRTIO_MSI_QUEUE_VECTOR);
236 legacy_get_queue_num(struct virtio_hw *hw, uint16_t queue_id)
240 rte_eal_pci_ioport_write(VTPCI_IO(hw), &queue_id, 2,
241 VIRTIO_PCI_QUEUE_SEL);
242 rte_eal_pci_ioport_read(VTPCI_IO(hw), &dst, 2, VIRTIO_PCI_QUEUE_NUM);
247 legacy_setup_queue(struct virtio_hw *hw, struct virtqueue *vq)
251 if (!check_vq_phys_addr_ok(vq))
254 rte_eal_pci_ioport_write(VTPCI_IO(hw), &vq->vq_queue_index, 2,
255 VIRTIO_PCI_QUEUE_SEL);
256 src = vq->vq_ring_mem >> VIRTIO_PCI_QUEUE_ADDR_SHIFT;
257 rte_eal_pci_ioport_write(VTPCI_IO(hw), &src, 4, VIRTIO_PCI_QUEUE_PFN);
263 legacy_del_queue(struct virtio_hw *hw, struct virtqueue *vq)
267 rte_eal_pci_ioport_write(VTPCI_IO(hw), &vq->vq_queue_index, 2,
268 VIRTIO_PCI_QUEUE_SEL);
269 rte_eal_pci_ioport_write(VTPCI_IO(hw), &src, 4, VIRTIO_PCI_QUEUE_PFN);
273 legacy_notify_queue(struct virtio_hw *hw, struct virtqueue *vq)
275 rte_eal_pci_ioport_write(VTPCI_IO(hw), &vq->vq_queue_index, 2,
276 VIRTIO_PCI_QUEUE_NOTIFY);
279 #ifdef RTE_EXEC_ENV_LINUXAPP
281 legacy_virtio_has_msix(const struct rte_pci_addr *loc)
284 char dirname[PATH_MAX];
286 snprintf(dirname, sizeof(dirname),
287 "%s/" PCI_PRI_FMT "/msi_irqs", pci_get_sysfs_path(),
288 loc->domain, loc->bus, loc->devid, loc->function);
290 d = opendir(dirname);
298 legacy_virtio_has_msix(const struct rte_pci_addr *loc __rte_unused)
300 /* nic_uio does not enable interrupts, return 0 (false). */
306 legacy_virtio_resource_init(struct rte_pci_device *pci_dev,
307 struct virtio_hw *hw, uint32_t *dev_flags)
309 if (rte_eal_pci_ioport_map(pci_dev, 0, VTPCI_IO(hw)) < 0)
312 if (pci_dev->intr_handle.type != RTE_INTR_HANDLE_UNKNOWN)
313 *dev_flags |= RTE_ETH_DEV_INTR_LSC;
315 *dev_flags &= ~RTE_ETH_DEV_INTR_LSC;
320 const struct virtio_pci_ops legacy_ops = {
321 .read_dev_cfg = legacy_read_dev_config,
322 .write_dev_cfg = legacy_write_dev_config,
323 .reset = legacy_reset,
324 .get_status = legacy_get_status,
325 .set_status = legacy_set_status,
326 .get_features = legacy_get_features,
327 .set_features = legacy_set_features,
328 .get_isr = legacy_get_isr,
329 .set_config_irq = legacy_set_config_irq,
330 .set_queue_irq = legacy_set_queue_irq,
331 .get_queue_num = legacy_get_queue_num,
332 .setup_queue = legacy_setup_queue,
333 .del_queue = legacy_del_queue,
334 .notify_queue = legacy_notify_queue,
338 static inline uint8_t
339 io_read8(uint8_t *addr)
341 return *(volatile uint8_t *)addr;
345 io_write8(uint8_t val, uint8_t *addr)
347 *(volatile uint8_t *)addr = val;
350 static inline uint16_t
351 io_read16(uint16_t *addr)
353 return *(volatile uint16_t *)addr;
357 io_write16(uint16_t val, uint16_t *addr)
359 *(volatile uint16_t *)addr = val;
362 static inline uint32_t
363 io_read32(uint32_t *addr)
365 return *(volatile uint32_t *)addr;
369 io_write32(uint32_t val, uint32_t *addr)
371 *(volatile uint32_t *)addr = val;
375 io_write64_twopart(uint64_t val, uint32_t *lo, uint32_t *hi)
377 io_write32(val & ((1ULL << 32) - 1), lo);
378 io_write32(val >> 32, hi);
382 modern_read_dev_config(struct virtio_hw *hw, size_t offset,
383 void *dst, int length)
387 uint8_t old_gen, new_gen;
390 old_gen = io_read8(&hw->common_cfg->config_generation);
393 for (i = 0; i < length; i++)
394 *p++ = io_read8((uint8_t *)hw->dev_cfg + offset + i);
396 new_gen = io_read8(&hw->common_cfg->config_generation);
397 } while (old_gen != new_gen);
401 modern_write_dev_config(struct virtio_hw *hw, size_t offset,
402 const void *src, int length)
405 const uint8_t *p = src;
407 for (i = 0; i < length; i++)
408 io_write8(*p++, (uint8_t *)hw->dev_cfg + offset + i);
412 modern_get_features(struct virtio_hw *hw)
414 uint32_t features_lo, features_hi;
416 io_write32(0, &hw->common_cfg->device_feature_select);
417 features_lo = io_read32(&hw->common_cfg->device_feature);
419 io_write32(1, &hw->common_cfg->device_feature_select);
420 features_hi = io_read32(&hw->common_cfg->device_feature);
422 return ((uint64_t)features_hi << 32) | features_lo;
426 modern_set_features(struct virtio_hw *hw, uint64_t features)
428 io_write32(0, &hw->common_cfg->guest_feature_select);
429 io_write32(features & ((1ULL << 32) - 1),
430 &hw->common_cfg->guest_feature);
432 io_write32(1, &hw->common_cfg->guest_feature_select);
433 io_write32(features >> 32,
434 &hw->common_cfg->guest_feature);
438 modern_get_status(struct virtio_hw *hw)
440 return io_read8(&hw->common_cfg->device_status);
444 modern_set_status(struct virtio_hw *hw, uint8_t status)
446 io_write8(status, &hw->common_cfg->device_status);
450 modern_reset(struct virtio_hw *hw)
452 modern_set_status(hw, VIRTIO_CONFIG_STATUS_RESET);
453 modern_get_status(hw);
457 modern_get_isr(struct virtio_hw *hw)
459 return io_read8(hw->isr);
463 modern_set_config_irq(struct virtio_hw *hw, uint16_t vec)
465 io_write16(vec, &hw->common_cfg->msix_config);
466 return io_read16(&hw->common_cfg->msix_config);
470 modern_set_queue_irq(struct virtio_hw *hw, struct virtqueue *vq, uint16_t vec)
472 io_write16(vq->vq_queue_index, &hw->common_cfg->queue_select);
473 io_write16(vec, &hw->common_cfg->queue_msix_vector);
474 return io_read16(&hw->common_cfg->queue_msix_vector);
478 modern_get_queue_num(struct virtio_hw *hw, uint16_t queue_id)
480 io_write16(queue_id, &hw->common_cfg->queue_select);
481 return io_read16(&hw->common_cfg->queue_size);
485 modern_setup_queue(struct virtio_hw *hw, struct virtqueue *vq)
487 uint64_t desc_addr, avail_addr, used_addr;
490 if (!check_vq_phys_addr_ok(vq))
493 desc_addr = vq->vq_ring_mem;
494 avail_addr = desc_addr + vq->vq_nentries * sizeof(struct vring_desc);
495 used_addr = RTE_ALIGN_CEIL(avail_addr + offsetof(struct vring_avail,
496 ring[vq->vq_nentries]),
497 VIRTIO_PCI_VRING_ALIGN);
499 io_write16(vq->vq_queue_index, &hw->common_cfg->queue_select);
501 io_write64_twopart(desc_addr, &hw->common_cfg->queue_desc_lo,
502 &hw->common_cfg->queue_desc_hi);
503 io_write64_twopart(avail_addr, &hw->common_cfg->queue_avail_lo,
504 &hw->common_cfg->queue_avail_hi);
505 io_write64_twopart(used_addr, &hw->common_cfg->queue_used_lo,
506 &hw->common_cfg->queue_used_hi);
508 notify_off = io_read16(&hw->common_cfg->queue_notify_off);
509 vq->notify_addr = (void *)((uint8_t *)hw->notify_base +
510 notify_off * hw->notify_off_multiplier);
512 io_write16(1, &hw->common_cfg->queue_enable);
514 PMD_INIT_LOG(DEBUG, "queue %u addresses:", vq->vq_queue_index);
515 PMD_INIT_LOG(DEBUG, "\t desc_addr: %" PRIx64, desc_addr);
516 PMD_INIT_LOG(DEBUG, "\t aval_addr: %" PRIx64, avail_addr);
517 PMD_INIT_LOG(DEBUG, "\t used_addr: %" PRIx64, used_addr);
518 PMD_INIT_LOG(DEBUG, "\t notify addr: %p (notify offset: %u)",
519 vq->notify_addr, notify_off);
525 modern_del_queue(struct virtio_hw *hw, struct virtqueue *vq)
527 io_write16(vq->vq_queue_index, &hw->common_cfg->queue_select);
529 io_write64_twopart(0, &hw->common_cfg->queue_desc_lo,
530 &hw->common_cfg->queue_desc_hi);
531 io_write64_twopart(0, &hw->common_cfg->queue_avail_lo,
532 &hw->common_cfg->queue_avail_hi);
533 io_write64_twopart(0, &hw->common_cfg->queue_used_lo,
534 &hw->common_cfg->queue_used_hi);
536 io_write16(0, &hw->common_cfg->queue_enable);
540 modern_notify_queue(struct virtio_hw *hw __rte_unused, struct virtqueue *vq)
542 io_write16(1, vq->notify_addr);
545 const struct virtio_pci_ops modern_ops = {
546 .read_dev_cfg = modern_read_dev_config,
547 .write_dev_cfg = modern_write_dev_config,
548 .reset = modern_reset,
549 .get_status = modern_get_status,
550 .set_status = modern_set_status,
551 .get_features = modern_get_features,
552 .set_features = modern_set_features,
553 .get_isr = modern_get_isr,
554 .set_config_irq = modern_set_config_irq,
555 .set_queue_irq = modern_set_queue_irq,
556 .get_queue_num = modern_get_queue_num,
557 .setup_queue = modern_setup_queue,
558 .del_queue = modern_del_queue,
559 .notify_queue = modern_notify_queue,
564 vtpci_read_dev_config(struct virtio_hw *hw, size_t offset,
565 void *dst, int length)
567 VTPCI_OPS(hw)->read_dev_cfg(hw, offset, dst, length);
571 vtpci_write_dev_config(struct virtio_hw *hw, size_t offset,
572 const void *src, int length)
574 VTPCI_OPS(hw)->write_dev_cfg(hw, offset, src, length);
578 vtpci_negotiate_features(struct virtio_hw *hw, uint64_t host_features)
583 * Limit negotiated features to what the driver, virtqueue, and
586 features = host_features & hw->guest_features;
587 VTPCI_OPS(hw)->set_features(hw, features);
593 vtpci_reset(struct virtio_hw *hw)
595 VTPCI_OPS(hw)->set_status(hw, VIRTIO_CONFIG_STATUS_RESET);
596 /* flush status write */
597 VTPCI_OPS(hw)->get_status(hw);
601 vtpci_reinit_complete(struct virtio_hw *hw)
603 vtpci_set_status(hw, VIRTIO_CONFIG_STATUS_DRIVER_OK);
607 vtpci_set_status(struct virtio_hw *hw, uint8_t status)
609 if (status != VIRTIO_CONFIG_STATUS_RESET)
610 status |= VTPCI_OPS(hw)->get_status(hw);
612 VTPCI_OPS(hw)->set_status(hw, status);
616 vtpci_get_status(struct virtio_hw *hw)
618 return VTPCI_OPS(hw)->get_status(hw);
622 vtpci_isr(struct virtio_hw *hw)
624 return VTPCI_OPS(hw)->get_isr(hw);
628 get_cfg_addr(struct rte_pci_device *dev, struct virtio_pci_cap *cap)
630 uint8_t bar = cap->bar;
631 uint32_t length = cap->length;
632 uint32_t offset = cap->offset;
636 PMD_INIT_LOG(ERR, "invalid bar: %u", bar);
640 if (offset + length < offset) {
641 PMD_INIT_LOG(ERR, "offset(%u) + length(%u) overflows",
646 if (offset + length > dev->mem_resource[bar].len) {
648 "invalid cap: overflows bar space: %u > %" PRIu64,
649 offset + length, dev->mem_resource[bar].len);
653 base = dev->mem_resource[bar].addr;
655 PMD_INIT_LOG(ERR, "bar %u base addr is NULL", bar);
659 return base + offset;
663 virtio_read_caps(struct rte_pci_device *dev, struct virtio_hw *hw)
666 struct virtio_pci_cap cap;
669 if (rte_eal_pci_map_device(dev)) {
670 PMD_INIT_LOG(DEBUG, "failed to map pci device!");
674 ret = rte_eal_pci_read_config(dev, &pos, 1, PCI_CAPABILITY_LIST);
676 PMD_INIT_LOG(DEBUG, "failed to read pci capability list");
681 ret = rte_eal_pci_read_config(dev, &cap, sizeof(cap), pos);
684 "failed to read pci cap at pos: %x", pos);
688 if (cap.cap_vndr != PCI_CAP_ID_VNDR) {
690 "[%2x] skipping non VNDR cap id: %02x",
696 "[%2x] cfg type: %u, bar: %u, offset: %04x, len: %u",
697 pos, cap.cfg_type, cap.bar, cap.offset, cap.length);
699 switch (cap.cfg_type) {
700 case VIRTIO_PCI_CAP_COMMON_CFG:
701 hw->common_cfg = get_cfg_addr(dev, &cap);
703 case VIRTIO_PCI_CAP_NOTIFY_CFG:
704 rte_eal_pci_read_config(dev, &hw->notify_off_multiplier,
705 4, pos + sizeof(cap));
706 hw->notify_base = get_cfg_addr(dev, &cap);
708 case VIRTIO_PCI_CAP_DEVICE_CFG:
709 hw->dev_cfg = get_cfg_addr(dev, &cap);
711 case VIRTIO_PCI_CAP_ISR_CFG:
712 hw->isr = get_cfg_addr(dev, &cap);
720 if (hw->common_cfg == NULL || hw->notify_base == NULL ||
721 hw->dev_cfg == NULL || hw->isr == NULL) {
722 PMD_INIT_LOG(INFO, "no modern virtio pci device found.");
726 PMD_INIT_LOG(INFO, "found modern virtio pci device.");
728 PMD_INIT_LOG(DEBUG, "common cfg mapped at: %p", hw->common_cfg);
729 PMD_INIT_LOG(DEBUG, "device cfg mapped at: %p", hw->dev_cfg);
730 PMD_INIT_LOG(DEBUG, "isr cfg mapped at: %p", hw->isr);
731 PMD_INIT_LOG(DEBUG, "notify base: %p, notify off multiplier: %u",
732 hw->notify_base, hw->notify_off_multiplier);
739 * if there is error mapping with VFIO/UIO.
740 * if port map error when driver type is KDRV_NONE.
741 * if whitelisted but driver type is KDRV_UNKNOWN.
742 * Return 1 if kernel driver is managing the device.
743 * Return 0 on success.
746 vtpci_init(struct rte_pci_device *dev, struct virtio_hw *hw,
750 * Try if we can succeed reading virtio pci caps, which exists
751 * only on modern pci device. If failed, we fallback to legacy
754 if (virtio_read_caps(dev, hw) == 0) {
755 PMD_INIT_LOG(INFO, "modern virtio pci detected.");
756 virtio_hw_internal[hw->port_id].vtpci_ops = &modern_ops;
758 *dev_flags |= RTE_ETH_DEV_INTR_LSC;
762 PMD_INIT_LOG(INFO, "trying with legacy virtio pci.");
763 if (legacy_virtio_resource_init(dev, hw, dev_flags) < 0) {
764 if (dev->kdrv == RTE_KDRV_UNKNOWN &&
765 (!dev->device.devargs ||
766 dev->device.devargs->type !=
767 RTE_DEVTYPE_WHITELISTED_PCI)) {
769 "skip kernel managed virtio device.");
775 virtio_hw_internal[hw->port_id].vtpci_ops = &legacy_ops;
776 hw->use_msix = legacy_virtio_has_msix(&dev->addr);