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35 #ifdef RTE_EXEC_ENV_LINUXAPP
42 #include "virtio_pci.h"
43 #include "virtio_logs.h"
44 #include "virtqueue.h"
47 * Following macros are derived from linux/pci_regs.h, however,
48 * we can't simply include that header here, as there is no such
49 * file for non-Linux platform.
51 #define PCI_CAPABILITY_LIST 0x34
52 #define PCI_CAP_ID_VNDR 0x09
55 * The remaining space is defined by each driver as the per-driver
56 * configuration space.
58 #define VIRTIO_PCI_CONFIG(hw) (((hw)->use_msix) ? 24 : 20)
61 check_vq_phys_addr_ok(struct virtqueue *vq)
63 /* Virtio PCI device VIRTIO_PCI_QUEUE_PF register is 32bit,
64 * and only accepts 32 bit page frame number.
65 * Check if the allocated physical memory exceeds 16TB.
67 if ((vq->vq_ring_mem + vq->vq_ring_size - 1) >>
68 (VIRTIO_PCI_QUEUE_ADDR_SHIFT + 32)) {
69 PMD_INIT_LOG(ERR, "vring address shouldn't be above 16TB!");
77 * Since we are in legacy mode:
78 * http://ozlabs.org/~rusty/virtio-spec/virtio-0.9.5.pdf
80 * "Note that this is possible because while the virtio header is PCI (i.e.
81 * little) endian, the device-specific region is encoded in the native endian of
82 * the guest (where such distinction is applicable)."
84 * For powerpc which supports both, qemu supposes that cpu is big endian and
85 * enforces this for the virtio-net stuff.
88 legacy_read_dev_config(struct virtio_hw *hw, size_t offset,
89 void *dst, int length)
91 #ifdef RTE_ARCH_PPC_64
97 rte_eal_pci_ioport_read(VTPCI_IO(hw), dst, size,
98 VIRTIO_PCI_CONFIG(hw) + offset);
99 *(uint32_t *)dst = rte_be_to_cpu_32(*(uint32_t *)dst);
100 } else if (length >= 2) {
102 rte_eal_pci_ioport_read(VTPCI_IO(hw), dst, size,
103 VIRTIO_PCI_CONFIG(hw) + offset);
104 *(uint16_t *)dst = rte_be_to_cpu_16(*(uint16_t *)dst);
107 rte_eal_pci_ioport_read(VTPCI_IO(hw), dst, size,
108 VIRTIO_PCI_CONFIG(hw) + offset);
111 dst = (char *)dst + size;
116 rte_eal_pci_ioport_read(VTPCI_IO(hw), dst, length,
117 VIRTIO_PCI_CONFIG(hw) + offset);
122 legacy_write_dev_config(struct virtio_hw *hw, size_t offset,
123 const void *src, int length)
125 #ifdef RTE_ARCH_PPC_64
135 tmp.u32 = rte_cpu_to_be_32(*(const uint32_t *)src);
136 rte_eal_pci_ioport_write(VTPCI_IO(hw), &tmp.u32, size,
137 VIRTIO_PCI_CONFIG(hw) + offset);
138 } else if (length >= 2) {
140 tmp.u16 = rte_cpu_to_be_16(*(const uint16_t *)src);
141 rte_eal_pci_ioport_write(VTPCI_IO(hw), &tmp.u16, size,
142 VIRTIO_PCI_CONFIG(hw) + offset);
145 rte_eal_pci_ioport_write(VTPCI_IO(hw), src, size,
146 VIRTIO_PCI_CONFIG(hw) + offset);
149 src = (const char *)src + size;
154 rte_eal_pci_ioport_write(VTPCI_IO(hw), src, length,
155 VIRTIO_PCI_CONFIG(hw) + offset);
160 legacy_get_features(struct virtio_hw *hw)
164 rte_eal_pci_ioport_read(VTPCI_IO(hw), &dst, 4,
165 VIRTIO_PCI_HOST_FEATURES);
170 legacy_set_features(struct virtio_hw *hw, uint64_t features)
172 if ((features >> 32) != 0) {
174 "only 32 bit features are allowed for legacy virtio!");
177 rte_eal_pci_ioport_write(VTPCI_IO(hw), &features, 4,
178 VIRTIO_PCI_GUEST_FEATURES);
182 legacy_get_status(struct virtio_hw *hw)
186 rte_eal_pci_ioport_read(VTPCI_IO(hw), &dst, 1, VIRTIO_PCI_STATUS);
191 legacy_set_status(struct virtio_hw *hw, uint8_t status)
193 rte_eal_pci_ioport_write(VTPCI_IO(hw), &status, 1, VIRTIO_PCI_STATUS);
197 legacy_reset(struct virtio_hw *hw)
199 legacy_set_status(hw, VIRTIO_CONFIG_STATUS_RESET);
203 legacy_get_isr(struct virtio_hw *hw)
207 rte_eal_pci_ioport_read(VTPCI_IO(hw), &dst, 1, VIRTIO_PCI_ISR);
211 /* Enable one vector (0) for Link State Intrerrupt */
213 legacy_set_config_irq(struct virtio_hw *hw, uint16_t vec)
217 rte_eal_pci_ioport_write(VTPCI_IO(hw), &vec, 2,
218 VIRTIO_MSI_CONFIG_VECTOR);
219 rte_eal_pci_ioport_read(VTPCI_IO(hw), &dst, 2,
220 VIRTIO_MSI_CONFIG_VECTOR);
225 legacy_set_queue_irq(struct virtio_hw *hw, struct virtqueue *vq, uint16_t vec)
229 rte_eal_pci_ioport_write(VTPCI_IO(hw), &vq->vq_queue_index, 2,
230 VIRTIO_PCI_QUEUE_SEL);
231 rte_eal_pci_ioport_write(VTPCI_IO(hw), &vec, 2,
232 VIRTIO_MSI_QUEUE_VECTOR);
233 rte_eal_pci_ioport_read(VTPCI_IO(hw), &dst, 2, VIRTIO_MSI_QUEUE_VECTOR);
238 legacy_get_queue_num(struct virtio_hw *hw, uint16_t queue_id)
242 rte_eal_pci_ioport_write(VTPCI_IO(hw), &queue_id, 2,
243 VIRTIO_PCI_QUEUE_SEL);
244 rte_eal_pci_ioport_read(VTPCI_IO(hw), &dst, 2, VIRTIO_PCI_QUEUE_NUM);
249 legacy_setup_queue(struct virtio_hw *hw, struct virtqueue *vq)
253 if (!check_vq_phys_addr_ok(vq))
256 rte_eal_pci_ioport_write(VTPCI_IO(hw), &vq->vq_queue_index, 2,
257 VIRTIO_PCI_QUEUE_SEL);
258 src = vq->vq_ring_mem >> VIRTIO_PCI_QUEUE_ADDR_SHIFT;
259 rte_eal_pci_ioport_write(VTPCI_IO(hw), &src, 4, VIRTIO_PCI_QUEUE_PFN);
265 legacy_del_queue(struct virtio_hw *hw, struct virtqueue *vq)
269 rte_eal_pci_ioport_write(VTPCI_IO(hw), &vq->vq_queue_index, 2,
270 VIRTIO_PCI_QUEUE_SEL);
271 rte_eal_pci_ioport_write(VTPCI_IO(hw), &src, 4, VIRTIO_PCI_QUEUE_PFN);
275 legacy_notify_queue(struct virtio_hw *hw, struct virtqueue *vq)
277 rte_eal_pci_ioport_write(VTPCI_IO(hw), &vq->vq_queue_index, 2,
278 VIRTIO_PCI_QUEUE_NOTIFY);
281 #ifdef RTE_EXEC_ENV_LINUXAPP
283 legacy_virtio_has_msix(const struct rte_pci_addr *loc)
286 char dirname[PATH_MAX];
288 snprintf(dirname, sizeof(dirname),
289 "%s/" PCI_PRI_FMT "/msi_irqs", pci_get_sysfs_path(),
290 loc->domain, loc->bus, loc->devid, loc->function);
292 d = opendir(dirname);
300 legacy_virtio_has_msix(const struct rte_pci_addr *loc __rte_unused)
302 /* nic_uio does not enable interrupts, return 0 (false). */
308 legacy_virtio_resource_init(struct rte_pci_device *pci_dev,
309 struct virtio_hw *hw, uint32_t *dev_flags)
311 if (rte_eal_pci_ioport_map(pci_dev, 0, VTPCI_IO(hw)) < 0)
314 if (pci_dev->intr_handle.type != RTE_INTR_HANDLE_UNKNOWN)
315 *dev_flags |= RTE_ETH_DEV_INTR_LSC;
317 *dev_flags &= ~RTE_ETH_DEV_INTR_LSC;
322 const struct virtio_pci_ops legacy_ops = {
323 .read_dev_cfg = legacy_read_dev_config,
324 .write_dev_cfg = legacy_write_dev_config,
325 .reset = legacy_reset,
326 .get_status = legacy_get_status,
327 .set_status = legacy_set_status,
328 .get_features = legacy_get_features,
329 .set_features = legacy_set_features,
330 .get_isr = legacy_get_isr,
331 .set_config_irq = legacy_set_config_irq,
332 .set_queue_irq = legacy_set_queue_irq,
333 .get_queue_num = legacy_get_queue_num,
334 .setup_queue = legacy_setup_queue,
335 .del_queue = legacy_del_queue,
336 .notify_queue = legacy_notify_queue,
340 io_write64_twopart(uint64_t val, uint32_t *lo, uint32_t *hi)
342 rte_write32(val & ((1ULL << 32) - 1), lo);
343 rte_write32(val >> 32, hi);
347 modern_read_dev_config(struct virtio_hw *hw, size_t offset,
348 void *dst, int length)
352 uint8_t old_gen, new_gen;
355 old_gen = rte_read8(&hw->common_cfg->config_generation);
358 for (i = 0; i < length; i++)
359 *p++ = rte_read8((uint8_t *)hw->dev_cfg + offset + i);
361 new_gen = rte_read8(&hw->common_cfg->config_generation);
362 } while (old_gen != new_gen);
366 modern_write_dev_config(struct virtio_hw *hw, size_t offset,
367 const void *src, int length)
370 const uint8_t *p = src;
372 for (i = 0; i < length; i++)
373 rte_write8((*p++), (((uint8_t *)hw->dev_cfg) + offset + i));
377 modern_get_features(struct virtio_hw *hw)
379 uint32_t features_lo, features_hi;
381 rte_write32(0, &hw->common_cfg->device_feature_select);
382 features_lo = rte_read32(&hw->common_cfg->device_feature);
384 rte_write32(1, &hw->common_cfg->device_feature_select);
385 features_hi = rte_read32(&hw->common_cfg->device_feature);
387 return ((uint64_t)features_hi << 32) | features_lo;
391 modern_set_features(struct virtio_hw *hw, uint64_t features)
393 rte_write32(0, &hw->common_cfg->guest_feature_select);
394 rte_write32(features & ((1ULL << 32) - 1),
395 &hw->common_cfg->guest_feature);
397 rte_write32(1, &hw->common_cfg->guest_feature_select);
398 rte_write32(features >> 32,
399 &hw->common_cfg->guest_feature);
403 modern_get_status(struct virtio_hw *hw)
405 return rte_read8(&hw->common_cfg->device_status);
409 modern_set_status(struct virtio_hw *hw, uint8_t status)
411 rte_write8(status, &hw->common_cfg->device_status);
415 modern_reset(struct virtio_hw *hw)
417 modern_set_status(hw, VIRTIO_CONFIG_STATUS_RESET);
418 modern_get_status(hw);
422 modern_get_isr(struct virtio_hw *hw)
424 return rte_read8(hw->isr);
428 modern_set_config_irq(struct virtio_hw *hw, uint16_t vec)
430 rte_write16(vec, &hw->common_cfg->msix_config);
431 return rte_read16(&hw->common_cfg->msix_config);
435 modern_set_queue_irq(struct virtio_hw *hw, struct virtqueue *vq, uint16_t vec)
437 rte_write16(vq->vq_queue_index, &hw->common_cfg->queue_select);
438 rte_write16(vec, &hw->common_cfg->queue_msix_vector);
439 return rte_read16(&hw->common_cfg->queue_msix_vector);
443 modern_get_queue_num(struct virtio_hw *hw, uint16_t queue_id)
445 rte_write16(queue_id, &hw->common_cfg->queue_select);
446 return rte_read16(&hw->common_cfg->queue_size);
450 modern_setup_queue(struct virtio_hw *hw, struct virtqueue *vq)
452 uint64_t desc_addr, avail_addr, used_addr;
455 if (!check_vq_phys_addr_ok(vq))
458 desc_addr = vq->vq_ring_mem;
459 avail_addr = desc_addr + vq->vq_nentries * sizeof(struct vring_desc);
460 used_addr = RTE_ALIGN_CEIL(avail_addr + offsetof(struct vring_avail,
461 ring[vq->vq_nentries]),
462 VIRTIO_PCI_VRING_ALIGN);
464 rte_write16(vq->vq_queue_index, &hw->common_cfg->queue_select);
466 io_write64_twopart(desc_addr, &hw->common_cfg->queue_desc_lo,
467 &hw->common_cfg->queue_desc_hi);
468 io_write64_twopart(avail_addr, &hw->common_cfg->queue_avail_lo,
469 &hw->common_cfg->queue_avail_hi);
470 io_write64_twopart(used_addr, &hw->common_cfg->queue_used_lo,
471 &hw->common_cfg->queue_used_hi);
473 notify_off = rte_read16(&hw->common_cfg->queue_notify_off);
474 vq->notify_addr = (void *)((uint8_t *)hw->notify_base +
475 notify_off * hw->notify_off_multiplier);
477 rte_write16(1, &hw->common_cfg->queue_enable);
479 PMD_INIT_LOG(DEBUG, "queue %u addresses:", vq->vq_queue_index);
480 PMD_INIT_LOG(DEBUG, "\t desc_addr: %" PRIx64, desc_addr);
481 PMD_INIT_LOG(DEBUG, "\t aval_addr: %" PRIx64, avail_addr);
482 PMD_INIT_LOG(DEBUG, "\t used_addr: %" PRIx64, used_addr);
483 PMD_INIT_LOG(DEBUG, "\t notify addr: %p (notify offset: %u)",
484 vq->notify_addr, notify_off);
490 modern_del_queue(struct virtio_hw *hw, struct virtqueue *vq)
492 rte_write16(vq->vq_queue_index, &hw->common_cfg->queue_select);
494 io_write64_twopart(0, &hw->common_cfg->queue_desc_lo,
495 &hw->common_cfg->queue_desc_hi);
496 io_write64_twopart(0, &hw->common_cfg->queue_avail_lo,
497 &hw->common_cfg->queue_avail_hi);
498 io_write64_twopart(0, &hw->common_cfg->queue_used_lo,
499 &hw->common_cfg->queue_used_hi);
501 rte_write16(0, &hw->common_cfg->queue_enable);
505 modern_notify_queue(struct virtio_hw *hw __rte_unused, struct virtqueue *vq)
507 rte_write16(1, vq->notify_addr);
510 const struct virtio_pci_ops modern_ops = {
511 .read_dev_cfg = modern_read_dev_config,
512 .write_dev_cfg = modern_write_dev_config,
513 .reset = modern_reset,
514 .get_status = modern_get_status,
515 .set_status = modern_set_status,
516 .get_features = modern_get_features,
517 .set_features = modern_set_features,
518 .get_isr = modern_get_isr,
519 .set_config_irq = modern_set_config_irq,
520 .set_queue_irq = modern_set_queue_irq,
521 .get_queue_num = modern_get_queue_num,
522 .setup_queue = modern_setup_queue,
523 .del_queue = modern_del_queue,
524 .notify_queue = modern_notify_queue,
529 vtpci_read_dev_config(struct virtio_hw *hw, size_t offset,
530 void *dst, int length)
532 VTPCI_OPS(hw)->read_dev_cfg(hw, offset, dst, length);
536 vtpci_write_dev_config(struct virtio_hw *hw, size_t offset,
537 const void *src, int length)
539 VTPCI_OPS(hw)->write_dev_cfg(hw, offset, src, length);
543 vtpci_negotiate_features(struct virtio_hw *hw, uint64_t host_features)
548 * Limit negotiated features to what the driver, virtqueue, and
551 features = host_features & hw->guest_features;
552 VTPCI_OPS(hw)->set_features(hw, features);
558 vtpci_reset(struct virtio_hw *hw)
560 VTPCI_OPS(hw)->set_status(hw, VIRTIO_CONFIG_STATUS_RESET);
561 /* flush status write */
562 VTPCI_OPS(hw)->get_status(hw);
566 vtpci_reinit_complete(struct virtio_hw *hw)
568 vtpci_set_status(hw, VIRTIO_CONFIG_STATUS_DRIVER_OK);
572 vtpci_set_status(struct virtio_hw *hw, uint8_t status)
574 if (status != VIRTIO_CONFIG_STATUS_RESET)
575 status |= VTPCI_OPS(hw)->get_status(hw);
577 VTPCI_OPS(hw)->set_status(hw, status);
581 vtpci_get_status(struct virtio_hw *hw)
583 return VTPCI_OPS(hw)->get_status(hw);
587 vtpci_isr(struct virtio_hw *hw)
589 return VTPCI_OPS(hw)->get_isr(hw);
593 get_cfg_addr(struct rte_pci_device *dev, struct virtio_pci_cap *cap)
595 uint8_t bar = cap->bar;
596 uint32_t length = cap->length;
597 uint32_t offset = cap->offset;
601 PMD_INIT_LOG(ERR, "invalid bar: %u", bar);
605 if (offset + length < offset) {
606 PMD_INIT_LOG(ERR, "offset(%u) + length(%u) overflows",
611 if (offset + length > dev->mem_resource[bar].len) {
613 "invalid cap: overflows bar space: %u > %" PRIu64,
614 offset + length, dev->mem_resource[bar].len);
618 base = dev->mem_resource[bar].addr;
620 PMD_INIT_LOG(ERR, "bar %u base addr is NULL", bar);
624 return base + offset;
628 virtio_read_caps(struct rte_pci_device *dev, struct virtio_hw *hw)
631 struct virtio_pci_cap cap;
634 if (rte_eal_pci_map_device(dev)) {
635 PMD_INIT_LOG(DEBUG, "failed to map pci device!");
639 ret = rte_eal_pci_read_config(dev, &pos, 1, PCI_CAPABILITY_LIST);
641 PMD_INIT_LOG(DEBUG, "failed to read pci capability list");
646 ret = rte_eal_pci_read_config(dev, &cap, sizeof(cap), pos);
649 "failed to read pci cap at pos: %x", pos);
653 if (cap.cap_vndr != PCI_CAP_ID_VNDR) {
655 "[%2x] skipping non VNDR cap id: %02x",
661 "[%2x] cfg type: %u, bar: %u, offset: %04x, len: %u",
662 pos, cap.cfg_type, cap.bar, cap.offset, cap.length);
664 switch (cap.cfg_type) {
665 case VIRTIO_PCI_CAP_COMMON_CFG:
666 hw->common_cfg = get_cfg_addr(dev, &cap);
668 case VIRTIO_PCI_CAP_NOTIFY_CFG:
669 rte_eal_pci_read_config(dev, &hw->notify_off_multiplier,
670 4, pos + sizeof(cap));
671 hw->notify_base = get_cfg_addr(dev, &cap);
673 case VIRTIO_PCI_CAP_DEVICE_CFG:
674 hw->dev_cfg = get_cfg_addr(dev, &cap);
676 case VIRTIO_PCI_CAP_ISR_CFG:
677 hw->isr = get_cfg_addr(dev, &cap);
685 if (hw->common_cfg == NULL || hw->notify_base == NULL ||
686 hw->dev_cfg == NULL || hw->isr == NULL) {
687 PMD_INIT_LOG(INFO, "no modern virtio pci device found.");
691 PMD_INIT_LOG(INFO, "found modern virtio pci device.");
693 PMD_INIT_LOG(DEBUG, "common cfg mapped at: %p", hw->common_cfg);
694 PMD_INIT_LOG(DEBUG, "device cfg mapped at: %p", hw->dev_cfg);
695 PMD_INIT_LOG(DEBUG, "isr cfg mapped at: %p", hw->isr);
696 PMD_INIT_LOG(DEBUG, "notify base: %p, notify off multiplier: %u",
697 hw->notify_base, hw->notify_off_multiplier);
704 * if there is error mapping with VFIO/UIO.
705 * if port map error when driver type is KDRV_NONE.
706 * if whitelisted but driver type is KDRV_UNKNOWN.
707 * Return 1 if kernel driver is managing the device.
708 * Return 0 on success.
711 vtpci_init(struct rte_pci_device *dev, struct virtio_hw *hw,
715 * Try if we can succeed reading virtio pci caps, which exists
716 * only on modern pci device. If failed, we fallback to legacy
719 if (virtio_read_caps(dev, hw) == 0) {
720 PMD_INIT_LOG(INFO, "modern virtio pci detected.");
721 virtio_hw_internal[hw->port_id].vtpci_ops = &modern_ops;
723 *dev_flags |= RTE_ETH_DEV_INTR_LSC;
727 PMD_INIT_LOG(INFO, "trying with legacy virtio pci.");
728 if (legacy_virtio_resource_init(dev, hw, dev_flags) < 0) {
729 if (dev->kdrv == RTE_KDRV_UNKNOWN &&
730 (!dev->device.devargs ||
731 dev->device.devargs->type !=
732 RTE_DEVTYPE_WHITELISTED_PCI)) {
734 "skip kernel managed virtio device.");
740 virtio_hw_internal[hw->port_id].vtpci_ops = &legacy_ops;
741 hw->use_msix = legacy_virtio_has_msix(&dev->addr);