1 /*********************************************************
2 * Copyright (C) 2007 VMware, Inc. All rights reserved.
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 *********************************************************/
31 * Definitions shared by device emulation and guest drivers for
35 #ifndef _VMXNET3_DEFS_H_
36 #define _VMXNET3_DEFS_H_
38 #define INCLUDE_ALLOW_USERLEVEL
39 #define INCLUDE_ALLOW_VMKERNEL
40 #define INCLUDE_ALLOW_DISTRIBUTE
41 #define INCLUDE_ALLOW_VMKDRIVERS
42 #define INCLUDE_ALLOW_VMCORE
43 #define INCLUDE_ALLOW_MODULE
44 #include "includeCheck.h"
46 #include "upt1_defs.h"
48 /* all registers are 32 bit wide */
50 #define VMXNET3_REG_VRRS 0x0 /* Vmxnet3 Revision Report Selection */
51 #define VMXNET3_REG_UVRS 0x8 /* UPT Version Report Selection */
52 #define VMXNET3_REG_DSAL 0x10 /* Driver Shared Address Low */
53 #define VMXNET3_REG_DSAH 0x18 /* Driver Shared Address High */
54 #define VMXNET3_REG_CMD 0x20 /* Command */
55 #define VMXNET3_REG_MACL 0x28 /* MAC Address Low */
56 #define VMXNET3_REG_MACH 0x30 /* MAC Address High */
57 #define VMXNET3_REG_ICR 0x38 /* Interrupt Cause Register */
58 #define VMXNET3_REG_ECR 0x40 /* Event Cause Register */
60 #define VMXNET3_REG_WSAL 0xF00 /* Wireless Shared Address Lo */
61 #define VMXNET3_REG_WSAH 0xF08 /* Wireless Shared Address Hi */
62 #define VMXNET3_REG_WCMD 0xF18 /* Wireless Command */
65 #define VMXNET3_REG_IMR 0x0 /* Interrupt Mask Register */
66 #define VMXNET3_REG_TXPROD 0x600 /* Tx Producer Index */
67 #define VMXNET3_REG_RXPROD 0x800 /* Rx Producer Index for ring 1 */
68 #define VMXNET3_REG_RXPROD2 0xA00 /* Rx Producer Index for ring 2 */
70 #define VMXNET3_PT_REG_SIZE 4096 /* BAR 0 */
71 #define VMXNET3_VD_REG_SIZE 4096 /* BAR 1 */
74 * The two Vmxnet3 MMIO Register PCI BARs (BAR 0 at offset 10h and BAR 1 at
75 * offset 14h) as well as the MSI-X BAR are combined into one PhysMem region:
76 * <-VMXNET3_PT_REG_SIZE-><-VMXNET3_VD_REG_SIZE-><-VMXNET3_MSIX_BAR_SIZE-->
77 * -------------------------------------------------------------------------
78 * |Pass Thru Registers | Virtual Dev Registers | MSI-X Vector/PBA Table |
79 * -------------------------------------------------------------------------
80 * VMXNET3_MSIX_BAR_SIZE is defined in "vmxnet3Int.h"
82 #define VMXNET3_PHYSMEM_PAGES 4
84 #define VMXNET3_REG_ALIGN 8 /* All registers are 8-byte aligned. */
85 #define VMXNET3_REG_ALIGN_MASK 0x7
87 /* I/O Mapped access to registers */
88 #define VMXNET3_IO_TYPE_PT 0
89 #define VMXNET3_IO_TYPE_VD 1
90 #define VMXNET3_IO_ADDR(type, reg) (((type) << 24) | ((reg) & 0xFFFFFF))
91 #define VMXNET3_IO_TYPE(addr) ((addr) >> 24)
92 #define VMXNET3_IO_REG(addr) ((addr) & 0xFFFFFF)
101 #define __le64 uint64
105 VMXNET3_CMD_FIRST_SET = 0xCAFE0000,
106 VMXNET3_CMD_ACTIVATE_DEV = VMXNET3_CMD_FIRST_SET,
107 VMXNET3_CMD_QUIESCE_DEV,
108 VMXNET3_CMD_RESET_DEV,
109 VMXNET3_CMD_UPDATE_RX_MODE,
110 VMXNET3_CMD_UPDATE_MAC_FILTERS,
111 VMXNET3_CMD_UPDATE_VLAN_FILTERS,
112 VMXNET3_CMD_UPDATE_RSSIDT,
113 VMXNET3_CMD_UPDATE_IML,
114 VMXNET3_CMD_UPDATE_PMCFG,
115 VMXNET3_CMD_UPDATE_FEATURE,
116 VMXNET3_CMD_STOP_EMULATION,
117 VMXNET3_CMD_LOAD_PLUGIN,
118 VMXNET3_CMD_ACTIVATE_VF,
120 VMXNET3_CMD_FIRST_GET = 0xF00D0000,
121 VMXNET3_CMD_GET_QUEUE_STATUS = VMXNET3_CMD_FIRST_GET,
122 VMXNET3_CMD_GET_STATS,
123 VMXNET3_CMD_GET_LINK,
124 VMXNET3_CMD_GET_PERM_MAC_LO,
125 VMXNET3_CMD_GET_PERM_MAC_HI,
126 VMXNET3_CMD_GET_DID_LO,
127 VMXNET3_CMD_GET_DID_HI,
128 VMXNET3_CMD_GET_DEV_EXTRA_INFO,
129 VMXNET3_CMD_GET_CONF_INTR,
130 VMXNET3_CMD_GET_ADAPTIVE_RING_INFO
133 /* Adaptive Ring Info Flags */
134 #define VMXNET3_DISABLE_ADAPTIVE_RING 1
137 * Little Endian layout of bitfields -
138 * Byte 0 : 7.....len.....0
139 * Byte 1 : rsvd gen 13.len.8
140 * Byte 2 : 5.msscof.0 ext1 dtype
141 * Byte 3 : 13...msscof...6
143 * Big Endian layout of bitfields -
144 * Byte 0: 13...msscof...6
145 * Byte 1 : 5.msscof.0 ext1 dtype
146 * Byte 2 : rsvd gen 13.len.8
147 * Byte 3 : 7.....len.....0
149 * Thus, le32_to_cpu on the dword will allow the big endian driver to read
150 * the bit fields correctly. And cpu_to_le32 will convert bitfields
151 * bit fields written by big endian driver to format required by device.
155 #include "vmware_pack_begin.h"
156 struct Vmxnet3_TxDesc {
159 #ifdef __BIG_ENDIAN_BITFIELD
160 uint32 msscof:14; /* MSS, checksum offset, flags */
162 uint32 dtype:1; /* descriptor type */
164 uint32 gen:1; /* generation bit */
168 uint32 gen:1; /* generation bit */
170 uint32 dtype:1; /* descriptor type */
172 uint32 msscof:14; /* MSS, checksum offset, flags */
173 #endif /* __BIG_ENDIAN_BITFIELD */
175 #ifdef __BIG_ENDIAN_BITFIELD
176 uint32 tci:16; /* Tag to Insert */
177 uint32 ti:1; /* VLAN Tag Insertion */
179 uint32 cq:1; /* completion request */
180 uint32 eop:1; /* End Of Packet */
181 uint32 om:2; /* offload mode */
182 uint32 hlen:10; /* header len */
184 uint32 hlen:10; /* header len */
185 uint32 om:2; /* offload mode */
186 uint32 eop:1; /* End Of Packet */
187 uint32 cq:1; /* completion request */
189 uint32 ti:1; /* VLAN Tag Insertion */
190 uint32 tci:16; /* Tag to Insert */
191 #endif /* __BIG_ENDIAN_BITFIELD */
193 #include "vmware_pack_end.h"
196 /* TxDesc.OM values */
197 #define VMXNET3_OM_NONE 0
198 #define VMXNET3_OM_CSUM 2
199 #define VMXNET3_OM_TSO 3
201 /* fields in TxDesc we access w/o using bit fields */
202 #define VMXNET3_TXD_EOP_SHIFT 12
203 #define VMXNET3_TXD_CQ_SHIFT 13
204 #define VMXNET3_TXD_GEN_SHIFT 14
205 #define VMXNET3_TXD_EOP_DWORD_SHIFT 3
206 #define VMXNET3_TXD_GEN_DWORD_SHIFT 2
208 #define VMXNET3_TXD_CQ (1 << VMXNET3_TXD_CQ_SHIFT)
209 #define VMXNET3_TXD_EOP (1 << VMXNET3_TXD_EOP_SHIFT)
210 #define VMXNET3_TXD_GEN (1 << VMXNET3_TXD_GEN_SHIFT)
212 #define VMXNET3_TXD_GEN_SIZE 1
213 #define VMXNET3_TXD_EOP_SIZE 1
215 #define VMXNET3_HDR_COPY_SIZE 128
218 #include "vmware_pack_begin.h"
219 struct Vmxnet3_TxDataDesc {
220 uint8 data[VMXNET3_HDR_COPY_SIZE];
222 #include "vmware_pack_end.h"
225 #define VMXNET3_TCD_GEN_SHIFT 31
226 #define VMXNET3_TCD_GEN_SIZE 1
227 #define VMXNET3_TCD_TXIDX_SHIFT 0
228 #define VMXNET3_TCD_TXIDX_SIZE 12
229 #define VMXNET3_TCD_GEN_DWORD_SHIFT 3
232 #include "vmware_pack_begin.h"
233 struct Vmxnet3_TxCompDesc {
234 uint32 txdIdx:12; /* Index of the EOP TxDesc */
241 uint32 type:7; /* completion type */
242 uint32 gen:1; /* generation bit */
244 #include "vmware_pack_end.h"
248 #include "vmware_pack_begin.h"
249 struct Vmxnet3_RxDesc {
252 #ifdef __BIG_ENDIAN_BITFIELD
253 uint32 gen:1; /* Generation bit */
255 uint32 dtype:1; /* Descriptor type */
256 uint32 btype:1; /* Buffer Type */
260 uint32 btype:1; /* Buffer Type */
261 uint32 dtype:1; /* Descriptor type */
263 uint32 gen:1; /* Generation bit */
267 #include "vmware_pack_end.h"
270 /* values of RXD.BTYPE */
271 #define VMXNET3_RXD_BTYPE_HEAD 0 /* head only */
272 #define VMXNET3_RXD_BTYPE_BODY 1 /* body only */
274 /* fields in RxDesc we access w/o using bit fields */
275 #define VMXNET3_RXD_BTYPE_SHIFT 14
276 #define VMXNET3_RXD_GEN_SHIFT 31
279 #include "vmware_pack_begin.h"
280 struct Vmxnet3_RxCompDesc {
281 #ifdef __BIG_ENDIAN_BITFIELD
283 uint32 cnc:1; /* Checksum Not Calculated */
284 uint32 rssType:4; /* RSS hash type used */
285 uint32 rqID:10; /* rx queue/ring ID */
286 uint32 sop:1; /* Start of Packet */
287 uint32 eop:1; /* End of Packet */
289 uint32 rxdIdx:12; /* Index of the RxDesc */
291 uint32 rxdIdx:12; /* Index of the RxDesc */
293 uint32 eop:1; /* End of Packet */
294 uint32 sop:1; /* Start of Packet */
295 uint32 rqID:10; /* rx queue/ring ID */
296 uint32 rssType:4; /* RSS hash type used */
297 uint32 cnc:1; /* Checksum Not Calculated */
299 #endif /* __BIG_ENDIAN_BITFIELD */
301 __le32 rssHash; /* RSS hash value */
303 #ifdef __BIG_ENDIAN_BITFIELD
304 uint32 tci:16; /* Tag stripped */
305 uint32 ts:1; /* Tag is stripped */
306 uint32 err:1; /* Error */
307 uint32 len:14; /* data length */
309 uint32 len:14; /* data length */
310 uint32 err:1; /* Error */
311 uint32 ts:1; /* Tag is stripped */
312 uint32 tci:16; /* Tag stripped */
313 #endif /* __BIG_ENDIAN_BITFIELD */
316 #ifdef __BIG_ENDIAN_BITFIELD
317 uint32 gen:1; /* generation bit */
318 uint32 type:7; /* completion type */
319 uint32 fcs:1; /* Frame CRC correct */
320 uint32 frg:1; /* IP Fragment */
321 uint32 v4:1; /* IPv4 */
322 uint32 v6:1; /* IPv6 */
323 uint32 ipc:1; /* IP Checksum Correct */
324 uint32 tcp:1; /* TCP packet */
325 uint32 udp:1; /* UDP packet */
326 uint32 tuc:1; /* TCP/UDP Checksum Correct */
330 uint32 tuc:1; /* TCP/UDP Checksum Correct */
331 uint32 udp:1; /* UDP packet */
332 uint32 tcp:1; /* TCP packet */
333 uint32 ipc:1; /* IP Checksum Correct */
334 uint32 v6:1; /* IPv6 */
335 uint32 v4:1; /* IPv4 */
336 uint32 frg:1; /* IP Fragment */
337 uint32 fcs:1; /* Frame CRC correct */
338 uint32 type:7; /* completion type */
339 uint32 gen:1; /* generation bit */
340 #endif /* __BIG_ENDIAN_BITFIELD */
342 #include "vmware_pack_end.h"
346 #include "vmware_pack_begin.h"
347 struct Vmxnet3_RxCompDescExt {
349 uint8 segCnt; /* Number of aggregated packets */
350 uint8 dupAckCnt; /* Number of duplicate Acks */
351 __le16 tsDelta; /* TCP timestamp difference */
354 #include "vmware_pack_end.h"
355 Vmxnet3_RxCompDescExt;
357 /* fields in RxCompDesc we access via Vmxnet3_GenericDesc.dword[3] */
358 #define VMXNET3_RCD_TUC_SHIFT 16
359 #define VMXNET3_RCD_IPC_SHIFT 19
361 /* fields in RxCompDesc we access via Vmxnet3_GenericDesc.qword[1] */
362 #define VMXNET3_RCD_TYPE_SHIFT 56
363 #define VMXNET3_RCD_GEN_SHIFT 63
365 /* csum OK for TCP/UDP pkts over IP */
366 #define VMXNET3_RCD_CSUM_OK (1 << VMXNET3_RCD_TUC_SHIFT | 1 << VMXNET3_RCD_IPC_SHIFT)
368 /* value of RxCompDesc.rssType */
369 #define VMXNET3_RCD_RSS_TYPE_NONE 0
370 #define VMXNET3_RCD_RSS_TYPE_IPV4 1
371 #define VMXNET3_RCD_RSS_TYPE_TCPIPV4 2
372 #define VMXNET3_RCD_RSS_TYPE_IPV6 3
373 #define VMXNET3_RCD_RSS_TYPE_TCPIPV6 4
375 /* a union for accessing all cmd/completion descriptors */
376 typedef union Vmxnet3_GenericDesc {
382 Vmxnet3_TxCompDesc tcd;
383 Vmxnet3_RxCompDesc rcd;
384 Vmxnet3_RxCompDescExt rcdExt;
385 } Vmxnet3_GenericDesc;
387 #define VMXNET3_INIT_GEN 1
389 /* Max size of a single tx buffer */
390 #define VMXNET3_MAX_TX_BUF_SIZE (1 << 14)
392 /* # of tx desc needed for a tx buffer size */
393 #define VMXNET3_TXD_NEEDED(size) (((size) + VMXNET3_MAX_TX_BUF_SIZE - 1) / VMXNET3_MAX_TX_BUF_SIZE)
395 /* max # of tx descs for a non-tso pkt */
396 #define VMXNET3_MAX_TXD_PER_PKT 16
398 /* Max size of a single rx buffer */
399 #define VMXNET3_MAX_RX_BUF_SIZE ((1 << 14) - 1)
400 /* Minimum size of a type 0 buffer */
401 #define VMXNET3_MIN_T0_BUF_SIZE 128
402 #define VMXNET3_MAX_CSUM_OFFSET 1024
404 /* Ring base address alignment */
405 #define VMXNET3_RING_BA_ALIGN 512
406 #define VMXNET3_RING_BA_MASK (VMXNET3_RING_BA_ALIGN - 1)
408 /* Ring size must be a multiple of 32 */
409 #define VMXNET3_RING_SIZE_ALIGN 32
410 #define VMXNET3_RING_SIZE_MASK (VMXNET3_RING_SIZE_ALIGN - 1)
413 #define VMXNET3_TX_RING_MAX_SIZE 4096
414 #define VMXNET3_TC_RING_MAX_SIZE 4096
415 #define VMXNET3_RX_RING_MAX_SIZE 4096
416 #define VMXNET3_RC_RING_MAX_SIZE 8192
418 /* a list of reasons for queue stop */
420 #define VMXNET3_ERR_NOEOP 0x80000000 /* cannot find the EOP desc of a pkt */
421 #define VMXNET3_ERR_TXD_REUSE 0x80000001 /* reuse a TxDesc before tx completion */
422 #define VMXNET3_ERR_BIG_PKT 0x80000002 /* too many TxDesc for a pkt */
423 #define VMXNET3_ERR_DESC_NOT_SPT 0x80000003 /* descriptor type not supported */
424 #define VMXNET3_ERR_SMALL_BUF 0x80000004 /* type 0 buffer too small */
425 #define VMXNET3_ERR_STRESS 0x80000005 /* stress option firing in vmkernel */
426 #define VMXNET3_ERR_SWITCH 0x80000006 /* mode switch failure */
427 #define VMXNET3_ERR_TXD_INVALID 0x80000007 /* invalid TxDesc */
429 /* completion descriptor types */
430 #define VMXNET3_CDTYPE_TXCOMP 0 /* Tx Completion Descriptor */
431 #define VMXNET3_CDTYPE_RXCOMP 3 /* Rx Completion Descriptor */
432 #define VMXNET3_CDTYPE_RXCOMP_LRO 4 /* Rx Completion Descriptor for LRO */
434 #define VMXNET3_GOS_BITS_UNK 0 /* unknown */
435 #define VMXNET3_GOS_BITS_32 1
436 #define VMXNET3_GOS_BITS_64 2
438 #define VMXNET3_GOS_TYPE_UNK 0 /* unknown */
439 #define VMXNET3_GOS_TYPE_LINUX 1
440 #define VMXNET3_GOS_TYPE_WIN 2
441 #define VMXNET3_GOS_TYPE_SOLARIS 3
442 #define VMXNET3_GOS_TYPE_FREEBSD 4
443 #define VMXNET3_GOS_TYPE_PXE 5
445 /* All structures in DriverShared are padded to multiples of 8 bytes */
448 #include "vmware_pack_begin.h"
449 struct Vmxnet3_GOSInfo {
450 #ifdef __BIG_ENDIAN_BITFIELD
451 uint32 gosMisc: 10; /* other info about gos */
452 uint32 gosVer: 16; /* gos version */
453 uint32 gosType: 4; /* which guest */
454 uint32 gosBits: 2; /* 32-bit or 64-bit? */
456 uint32 gosBits: 2; /* 32-bit or 64-bit? */
457 uint32 gosType: 4; /* which guest */
458 uint32 gosVer: 16; /* gos version */
459 uint32 gosMisc: 10; /* other info about gos */
460 #endif /* __BIG_ENDIAN_BITFIELD */
462 #include "vmware_pack_end.h"
466 #include "vmware_pack_begin.h"
467 struct Vmxnet3_DriverInfo {
468 __le32 version; /* driver version */
470 __le32 vmxnet3RevSpt; /* vmxnet3 revision supported */
471 __le32 uptVerSpt; /* upt version supported */
473 #include "vmware_pack_end.h"
476 #define VMXNET3_REV1_MAGIC 0xbabefee1
479 * QueueDescPA must be 128 bytes aligned. It points to an array of
480 * Vmxnet3_TxQueueDesc followed by an array of Vmxnet3_RxQueueDesc.
481 * The number of Vmxnet3_TxQueueDesc/Vmxnet3_RxQueueDesc are specified by
482 * Vmxnet3_MiscConf.numTxQueues/numRxQueues, respectively.
484 #define VMXNET3_QUEUE_DESC_ALIGN 128
487 #include "vmware_pack_begin.h"
488 struct Vmxnet3_MiscConf {
489 Vmxnet3_DriverInfo driverInfo;
491 __le64 ddPA; /* driver data PA */
492 __le64 queueDescPA; /* queue descriptor table PA */
493 __le32 ddLen; /* driver data len */
494 __le32 queueDescLen; /* queue descriptor table len, in bytes */
501 #include "vmware_pack_end.h"
505 #include "vmware_pack_begin.h"
506 struct Vmxnet3_TxQueueConf {
508 __le64 dataRingBasePA;
509 __le64 compRingBasePA;
510 __le64 ddPA; /* driver data */
512 __le32 txRingSize; /* # of tx desc */
513 __le32 dataRingSize; /* # of data desc */
514 __le32 compRingSize; /* # of comp desc */
515 __le32 ddLen; /* size of driver data */
519 #include "vmware_pack_end.h"
523 #include "vmware_pack_begin.h"
524 struct Vmxnet3_RxQueueConf {
525 __le64 rxRingBasePA[2];
526 __le64 compRingBasePA;
527 __le64 ddPA; /* driver data */
529 __le32 rxRingSize[2]; /* # of rx desc */
530 __le32 compRingSize; /* # of rx comp desc */
531 __le32 ddLen; /* size of driver data */
535 #include "vmware_pack_end.h"
538 enum vmxnet3_intr_mask_mode {
539 VMXNET3_IMM_AUTO = 0,
540 VMXNET3_IMM_ACTIVE = 1,
544 enum vmxnet3_intr_type {
551 #define VMXNET3_MAX_TX_QUEUES 8
552 #define VMXNET3_MAX_RX_QUEUES 16
553 /* addition 1 for events */
554 #define VMXNET3_MAX_INTRS 25
556 /* value of intrCtrl */
557 #define VMXNET3_IC_DISABLE_ALL 0x1 /* bit 0 */
560 #include "vmware_pack_begin.h"
561 struct Vmxnet3_IntrConf {
563 uint8 numIntrs; /* # of interrupts */
565 uint8 modLevels[VMXNET3_MAX_INTRS]; /* moderation level for each intr */
569 #include "vmware_pack_end.h"
572 /* one bit per VLAN ID, the size is in the units of uint32 */
573 #define VMXNET3_VFT_SIZE (4096 / (sizeof(uint32) * 8))
576 #include "vmware_pack_begin.h"
577 struct Vmxnet3_QueueStatus {
582 #include "vmware_pack_end.h"
586 #include "vmware_pack_begin.h"
587 struct Vmxnet3_TxQueueCtrl {
588 __le32 txNumDeferred;
592 #include "vmware_pack_end.h"
596 #include "vmware_pack_begin.h"
597 struct Vmxnet3_RxQueueCtrl {
602 #include "vmware_pack_end.h"
605 #define VMXNET3_RXM_UCAST 0x01 /* unicast only */
606 #define VMXNET3_RXM_MCAST 0x02 /* multicast passing the filters */
607 #define VMXNET3_RXM_BCAST 0x04 /* broadcast only */
608 #define VMXNET3_RXM_ALL_MULTI 0x08 /* all multicast */
609 #define VMXNET3_RXM_PROMISC 0x10 /* promiscuous */
612 #include "vmware_pack_begin.h"
613 struct Vmxnet3_RxFilterConf {
614 __le32 rxMode; /* VMXNET3_RXM_xxx */
615 __le16 mfTableLen; /* size of the multicast filter table */
617 __le64 mfTablePA; /* PA of the multicast filters table */
618 __le32 vfTable[VMXNET3_VFT_SIZE]; /* vlan filter */
620 #include "vmware_pack_end.h"
621 Vmxnet3_RxFilterConf;
623 #define VMXNET3_PM_MAX_FILTERS 6
624 #define VMXNET3_PM_MAX_PATTERN_SIZE 128
625 #define VMXNET3_PM_MAX_MASK_SIZE (VMXNET3_PM_MAX_PATTERN_SIZE / 8)
627 #define VMXNET3_PM_WAKEUP_MAGIC 0x01 /* wake up on magic pkts */
628 #define VMXNET3_PM_WAKEUP_FILTER 0x02 /* wake up on pkts matching filters */
631 #include "vmware_pack_begin.h"
632 struct Vmxnet3_PM_PktFilter {
635 uint8 mask[VMXNET3_PM_MAX_MASK_SIZE];
636 uint8 pattern[VMXNET3_PM_MAX_PATTERN_SIZE];
639 #include "vmware_pack_end.h"
640 Vmxnet3_PM_PktFilter;
643 #include "vmware_pack_begin.h"
644 struct Vmxnet3_PMConf {
645 __le16 wakeUpEvents; /* VMXNET3_PM_WAKEUP_xxx */
648 Vmxnet3_PM_PktFilter filters[VMXNET3_PM_MAX_FILTERS];
650 #include "vmware_pack_end.h"
654 #include "vmware_pack_begin.h"
655 struct Vmxnet3_VariableLenConfDesc {
660 #include "vmware_pack_end.h"
661 Vmxnet3_VariableLenConfDesc;
664 #include "vmware_pack_begin.h"
665 struct Vmxnet3_DSDevRead {
666 /* read-only region for device, read by dev in response to a SET cmd */
667 Vmxnet3_MiscConf misc;
668 Vmxnet3_IntrConf intrConf;
669 Vmxnet3_RxFilterConf rxFilterConf;
670 Vmxnet3_VariableLenConfDesc rssConfDesc;
671 Vmxnet3_VariableLenConfDesc pmConfDesc;
672 Vmxnet3_VariableLenConfDesc pluginConfDesc;
674 #include "vmware_pack_end.h"
678 #include "vmware_pack_begin.h"
679 struct Vmxnet3_TxQueueDesc {
680 Vmxnet3_TxQueueCtrl ctrl;
681 Vmxnet3_TxQueueConf conf;
682 /* Driver read after a GET command */
683 Vmxnet3_QueueStatus status;
685 uint8 _pad[88]; /* 128 aligned */
687 #include "vmware_pack_end.h"
691 #include "vmware_pack_begin.h"
692 struct Vmxnet3_RxQueueDesc {
693 Vmxnet3_RxQueueCtrl ctrl;
694 Vmxnet3_RxQueueConf conf;
695 /* Driver read after a GET command */
696 Vmxnet3_QueueStatus status;
698 uint8 _pad[88]; /* 128 aligned */
700 #include "vmware_pack_end.h"
704 #include "vmware_pack_begin.h"
705 struct Vmxnet3_DriverShared {
707 __le32 pad; /* make devRead start at 64-bit boundaries */
708 Vmxnet3_DSDevRead devRead;
712 #include "vmware_pack_end.h"
713 Vmxnet3_DriverShared;
715 #define VMXNET3_ECR_RQERR (1 << 0)
716 #define VMXNET3_ECR_TQERR (1 << 1)
717 #define VMXNET3_ECR_LINK (1 << 2)
718 #define VMXNET3_ECR_DIC (1 << 3)
719 #define VMXNET3_ECR_DEBUG (1 << 4)
721 /* flip the gen bit of a ring */
722 #define VMXNET3_FLIP_RING_GEN(gen) ((gen) = (gen) ^ 0x1)
724 /* only use this if moving the idx won't affect the gen bit */
725 #define VMXNET3_INC_RING_IDX_ONLY(idx, ring_size) \
728 if (UNLIKELY((idx) == (ring_size))) {\
733 #define VMXNET3_SET_VFTABLE_ENTRY(vfTable, vid) \
734 vfTable[vid >> 5] |= (1 << (vid & 31))
735 #define VMXNET3_CLEAR_VFTABLE_ENTRY(vfTable, vid) \
736 vfTable[vid >> 5] &= ~(1 << (vid & 31))
738 #define VMXNET3_VFTABLE_ENTRY_IS_SET(vfTable, vid) \
739 ((vfTable[vid >> 5] & (1 << (vid & 31))) != 0)
741 #define VMXNET3_MAX_MTU 9000
742 #define VMXNET3_MIN_MTU 60
744 #define VMXNET3_LINK_UP (10000 << 16 | 1) // 10 Gbps, up
745 #define VMXNET3_LINK_DOWN 0
747 #define VMXWIFI_DRIVER_SHARED_LEN 8192
749 #define VMXNET3_DID_PASSTHRU 0xFFFF
751 #endif /* _VMXNET3_DEFS_H_ */