1 /*********************************************************
2 * Copyright (C) 2007 VMware, Inc. All rights reserved.
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 *********************************************************/
31 * Definitions shared by device emulation and guest drivers for
35 #ifndef _VMXNET3_DEFS_H_
36 #define _VMXNET3_DEFS_H_
38 #include "vmxnet3_osdep.h"
39 #include "upt1_defs.h"
41 /* all registers are 32 bit wide */
43 #define VMXNET3_REG_VRRS 0x0 /* Vmxnet3 Revision Report Selection */
44 #define VMXNET3_REG_UVRS 0x8 /* UPT Version Report Selection */
45 #define VMXNET3_REG_DSAL 0x10 /* Driver Shared Address Low */
46 #define VMXNET3_REG_DSAH 0x18 /* Driver Shared Address High */
47 #define VMXNET3_REG_CMD 0x20 /* Command */
48 #define VMXNET3_REG_MACL 0x28 /* MAC Address Low */
49 #define VMXNET3_REG_MACH 0x30 /* MAC Address High */
50 #define VMXNET3_REG_ICR 0x38 /* Interrupt Cause Register */
51 #define VMXNET3_REG_ECR 0x40 /* Event Cause Register */
53 #define VMXNET3_REG_WSAL 0xF00 /* Wireless Shared Address Lo */
54 #define VMXNET3_REG_WSAH 0xF08 /* Wireless Shared Address Hi */
55 #define VMXNET3_REG_WCMD 0xF18 /* Wireless Command */
58 #define VMXNET3_REG_IMR 0x0 /* Interrupt Mask Register */
59 #define VMXNET3_REG_TXPROD 0x600 /* Tx Producer Index */
60 #define VMXNET3_REG_RXPROD 0x800 /* Rx Producer Index for ring 1 */
61 #define VMXNET3_REG_RXPROD2 0xA00 /* Rx Producer Index for ring 2 */
63 #define VMXNET3_PT_REG_SIZE 4096 /* BAR 0 */
64 #define VMXNET3_VD_REG_SIZE 4096 /* BAR 1 */
67 * The two Vmxnet3 MMIO Register PCI BARs (BAR 0 at offset 10h and BAR 1 at
68 * offset 14h) as well as the MSI-X BAR are combined into one PhysMem region:
69 * <-VMXNET3_PT_REG_SIZE-><-VMXNET3_VD_REG_SIZE-><-VMXNET3_MSIX_BAR_SIZE-->
70 * -------------------------------------------------------------------------
71 * |Pass Thru Registers | Virtual Dev Registers | MSI-X Vector/PBA Table |
72 * -------------------------------------------------------------------------
73 * VMXNET3_MSIX_BAR_SIZE is defined in "vmxnet3Int.h"
75 #define VMXNET3_PHYSMEM_PAGES 4
77 #define VMXNET3_REG_ALIGN 8 /* All registers are 8-byte aligned. */
78 #define VMXNET3_REG_ALIGN_MASK 0x7
80 /* I/O Mapped access to registers */
81 #define VMXNET3_IO_TYPE_PT 0
82 #define VMXNET3_IO_TYPE_VD 1
83 #define VMXNET3_IO_ADDR(type, reg) (((type) << 24) | ((reg) & 0xFFFFFF))
84 #define VMXNET3_IO_TYPE(addr) ((addr) >> 24)
85 #define VMXNET3_IO_REG(addr) ((addr) & 0xFFFFFF)
98 VMXNET3_CMD_FIRST_SET = 0xCAFE0000,
99 VMXNET3_CMD_ACTIVATE_DEV = VMXNET3_CMD_FIRST_SET,
100 VMXNET3_CMD_QUIESCE_DEV,
101 VMXNET3_CMD_RESET_DEV,
102 VMXNET3_CMD_UPDATE_RX_MODE,
103 VMXNET3_CMD_UPDATE_MAC_FILTERS,
104 VMXNET3_CMD_UPDATE_VLAN_FILTERS,
105 VMXNET3_CMD_UPDATE_RSSIDT,
106 VMXNET3_CMD_UPDATE_IML,
107 VMXNET3_CMD_UPDATE_PMCFG,
108 VMXNET3_CMD_UPDATE_FEATURE,
109 VMXNET3_CMD_STOP_EMULATION,
110 VMXNET3_CMD_LOAD_PLUGIN,
111 VMXNET3_CMD_ACTIVATE_VF,
113 VMXNET3_CMD_FIRST_GET = 0xF00D0000,
114 VMXNET3_CMD_GET_QUEUE_STATUS = VMXNET3_CMD_FIRST_GET,
115 VMXNET3_CMD_GET_STATS,
116 VMXNET3_CMD_GET_LINK,
117 VMXNET3_CMD_GET_PERM_MAC_LO,
118 VMXNET3_CMD_GET_PERM_MAC_HI,
119 VMXNET3_CMD_GET_DID_LO,
120 VMXNET3_CMD_GET_DID_HI,
121 VMXNET3_CMD_GET_DEV_EXTRA_INFO,
122 VMXNET3_CMD_GET_CONF_INTR,
123 VMXNET3_CMD_GET_ADAPTIVE_RING_INFO
126 /* Adaptive Ring Info Flags */
127 #define VMXNET3_DISABLE_ADAPTIVE_RING 1
130 * Little Endian layout of bitfields -
131 * Byte 0 : 7.....len.....0
132 * Byte 1 : rsvd gen 13.len.8
133 * Byte 2 : 5.msscof.0 ext1 dtype
134 * Byte 3 : 13...msscof...6
136 * Big Endian layout of bitfields -
137 * Byte 0: 13...msscof...6
138 * Byte 1 : 5.msscof.0 ext1 dtype
139 * Byte 2 : rsvd gen 13.len.8
140 * Byte 3 : 7.....len.....0
142 * Thus, le32_to_cpu on the dword will allow the big endian driver to read
143 * the bit fields correctly. And cpu_to_le32 will convert bitfields
144 * bit fields written by big endian driver to format required by device.
148 #include "vmware_pack_begin.h"
149 struct Vmxnet3_TxDesc {
152 #ifdef __BIG_ENDIAN_BITFIELD
153 uint32 msscof:14; /* MSS, checksum offset, flags */
155 uint32 dtype:1; /* descriptor type */
157 uint32 gen:1; /* generation bit */
161 uint32 gen:1; /* generation bit */
163 uint32 dtype:1; /* descriptor type */
165 uint32 msscof:14; /* MSS, checksum offset, flags */
166 #endif /* __BIG_ENDIAN_BITFIELD */
168 #ifdef __BIG_ENDIAN_BITFIELD
169 uint32 tci:16; /* Tag to Insert */
170 uint32 ti:1; /* VLAN Tag Insertion */
172 uint32 cq:1; /* completion request */
173 uint32 eop:1; /* End Of Packet */
174 uint32 om:2; /* offload mode */
175 uint32 hlen:10; /* header len */
177 uint32 hlen:10; /* header len */
178 uint32 om:2; /* offload mode */
179 uint32 eop:1; /* End Of Packet */
180 uint32 cq:1; /* completion request */
182 uint32 ti:1; /* VLAN Tag Insertion */
183 uint32 tci:16; /* Tag to Insert */
184 #endif /* __BIG_ENDIAN_BITFIELD */
186 #include "vmware_pack_end.h"
189 /* TxDesc.OM values */
190 #define VMXNET3_OM_NONE 0
191 #define VMXNET3_OM_CSUM 2
192 #define VMXNET3_OM_TSO 3
194 /* fields in TxDesc we access w/o using bit fields */
195 #define VMXNET3_TXD_EOP_SHIFT 12
196 #define VMXNET3_TXD_CQ_SHIFT 13
197 #define VMXNET3_TXD_GEN_SHIFT 14
198 #define VMXNET3_TXD_EOP_DWORD_SHIFT 3
199 #define VMXNET3_TXD_GEN_DWORD_SHIFT 2
201 #define VMXNET3_TXD_CQ (1 << VMXNET3_TXD_CQ_SHIFT)
202 #define VMXNET3_TXD_EOP (1 << VMXNET3_TXD_EOP_SHIFT)
203 #define VMXNET3_TXD_GEN (1 << VMXNET3_TXD_GEN_SHIFT)
205 #define VMXNET3_TXD_GEN_SIZE 1
206 #define VMXNET3_TXD_EOP_SIZE 1
208 #define VMXNET3_HDR_COPY_SIZE 128
211 #include "vmware_pack_begin.h"
212 struct Vmxnet3_TxDataDesc {
213 uint8 data[VMXNET3_HDR_COPY_SIZE];
215 #include "vmware_pack_end.h"
218 #define VMXNET3_TCD_GEN_SHIFT 31
219 #define VMXNET3_TCD_GEN_SIZE 1
220 #define VMXNET3_TCD_TXIDX_SHIFT 0
221 #define VMXNET3_TCD_TXIDX_SIZE 12
222 #define VMXNET3_TCD_GEN_DWORD_SHIFT 3
225 #include "vmware_pack_begin.h"
226 struct Vmxnet3_TxCompDesc {
227 uint32 txdIdx:12; /* Index of the EOP TxDesc */
234 uint32 type:7; /* completion type */
235 uint32 gen:1; /* generation bit */
237 #include "vmware_pack_end.h"
241 #include "vmware_pack_begin.h"
242 struct Vmxnet3_RxDesc {
245 #ifdef __BIG_ENDIAN_BITFIELD
246 uint32 gen:1; /* Generation bit */
248 uint32 dtype:1; /* Descriptor type */
249 uint32 btype:1; /* Buffer Type */
253 uint32 btype:1; /* Buffer Type */
254 uint32 dtype:1; /* Descriptor type */
256 uint32 gen:1; /* Generation bit */
260 #include "vmware_pack_end.h"
263 /* values of RXD.BTYPE */
264 #define VMXNET3_RXD_BTYPE_HEAD 0 /* head only */
265 #define VMXNET3_RXD_BTYPE_BODY 1 /* body only */
267 /* fields in RxDesc we access w/o using bit fields */
268 #define VMXNET3_RXD_BTYPE_SHIFT 14
269 #define VMXNET3_RXD_GEN_SHIFT 31
272 #include "vmware_pack_begin.h"
273 struct Vmxnet3_RxCompDesc {
274 #ifdef __BIG_ENDIAN_BITFIELD
276 uint32 cnc:1; /* Checksum Not Calculated */
277 uint32 rssType:4; /* RSS hash type used */
278 uint32 rqID:10; /* rx queue/ring ID */
279 uint32 sop:1; /* Start of Packet */
280 uint32 eop:1; /* End of Packet */
282 uint32 rxdIdx:12; /* Index of the RxDesc */
284 uint32 rxdIdx:12; /* Index of the RxDesc */
286 uint32 eop:1; /* End of Packet */
287 uint32 sop:1; /* Start of Packet */
288 uint32 rqID:10; /* rx queue/ring ID */
289 uint32 rssType:4; /* RSS hash type used */
290 uint32 cnc:1; /* Checksum Not Calculated */
292 #endif /* __BIG_ENDIAN_BITFIELD */
294 __le32 rssHash; /* RSS hash value */
296 #ifdef __BIG_ENDIAN_BITFIELD
297 uint32 tci:16; /* Tag stripped */
298 uint32 ts:1; /* Tag is stripped */
299 uint32 err:1; /* Error */
300 uint32 len:14; /* data length */
302 uint32 len:14; /* data length */
303 uint32 err:1; /* Error */
304 uint32 ts:1; /* Tag is stripped */
305 uint32 tci:16; /* Tag stripped */
306 #endif /* __BIG_ENDIAN_BITFIELD */
309 #ifdef __BIG_ENDIAN_BITFIELD
310 uint32 gen:1; /* generation bit */
311 uint32 type:7; /* completion type */
312 uint32 fcs:1; /* Frame CRC correct */
313 uint32 frg:1; /* IP Fragment */
314 uint32 v4:1; /* IPv4 */
315 uint32 v6:1; /* IPv6 */
316 uint32 ipc:1; /* IP Checksum Correct */
317 uint32 tcp:1; /* TCP packet */
318 uint32 udp:1; /* UDP packet */
319 uint32 tuc:1; /* TCP/UDP Checksum Correct */
323 uint32 tuc:1; /* TCP/UDP Checksum Correct */
324 uint32 udp:1; /* UDP packet */
325 uint32 tcp:1; /* TCP packet */
326 uint32 ipc:1; /* IP Checksum Correct */
327 uint32 v6:1; /* IPv6 */
328 uint32 v4:1; /* IPv4 */
329 uint32 frg:1; /* IP Fragment */
330 uint32 fcs:1; /* Frame CRC correct */
331 uint32 type:7; /* completion type */
332 uint32 gen:1; /* generation bit */
333 #endif /* __BIG_ENDIAN_BITFIELD */
335 #include "vmware_pack_end.h"
339 #include "vmware_pack_begin.h"
340 struct Vmxnet3_RxCompDescExt {
342 uint8 segCnt; /* Number of aggregated packets */
343 uint8 dupAckCnt; /* Number of duplicate Acks */
344 __le16 tsDelta; /* TCP timestamp difference */
347 #include "vmware_pack_end.h"
348 Vmxnet3_RxCompDescExt;
350 /* fields in RxCompDesc we access via Vmxnet3_GenericDesc.dword[3] */
351 #define VMXNET3_RCD_TUC_SHIFT 16
352 #define VMXNET3_RCD_IPC_SHIFT 19
354 /* fields in RxCompDesc we access via Vmxnet3_GenericDesc.qword[1] */
355 #define VMXNET3_RCD_TYPE_SHIFT 56
356 #define VMXNET3_RCD_GEN_SHIFT 63
358 /* csum OK for TCP/UDP pkts over IP */
359 #define VMXNET3_RCD_CSUM_OK (1 << VMXNET3_RCD_TUC_SHIFT | 1 << VMXNET3_RCD_IPC_SHIFT)
361 /* value of RxCompDesc.rssType */
362 #define VMXNET3_RCD_RSS_TYPE_NONE 0
363 #define VMXNET3_RCD_RSS_TYPE_IPV4 1
364 #define VMXNET3_RCD_RSS_TYPE_TCPIPV4 2
365 #define VMXNET3_RCD_RSS_TYPE_IPV6 3
366 #define VMXNET3_RCD_RSS_TYPE_TCPIPV6 4
368 /* a union for accessing all cmd/completion descriptors */
369 typedef union Vmxnet3_GenericDesc {
375 Vmxnet3_TxCompDesc tcd;
376 Vmxnet3_RxCompDesc rcd;
377 Vmxnet3_RxCompDescExt rcdExt;
378 } Vmxnet3_GenericDesc;
380 #define VMXNET3_INIT_GEN 1
382 /* Max size of a single tx buffer */
383 #define VMXNET3_MAX_TX_BUF_SIZE (1 << 14)
385 /* # of tx desc needed for a tx buffer size */
386 #define VMXNET3_TXD_NEEDED(size) (((size) + VMXNET3_MAX_TX_BUF_SIZE - 1) / VMXNET3_MAX_TX_BUF_SIZE)
388 /* max # of tx descs for a non-tso pkt */
389 #define VMXNET3_MAX_TXD_PER_PKT 16
391 /* Max size of a single rx buffer */
392 #define VMXNET3_MAX_RX_BUF_SIZE ((1 << 14) - 1)
393 /* Minimum size of a type 0 buffer */
394 #define VMXNET3_MIN_T0_BUF_SIZE 128
395 #define VMXNET3_MAX_CSUM_OFFSET 1024
397 /* Ring base address alignment */
398 #define VMXNET3_RING_BA_ALIGN 512
399 #define VMXNET3_RING_BA_MASK (VMXNET3_RING_BA_ALIGN - 1)
401 /* Ring size must be a multiple of 32 */
402 #define VMXNET3_RING_SIZE_ALIGN 32
403 #define VMXNET3_RING_SIZE_MASK (VMXNET3_RING_SIZE_ALIGN - 1)
406 #define VMXNET3_TX_RING_MAX_SIZE 4096
407 #define VMXNET3_TC_RING_MAX_SIZE 4096
408 #define VMXNET3_RX_RING_MAX_SIZE 4096
409 #define VMXNET3_RC_RING_MAX_SIZE 8192
411 /* a list of reasons for queue stop */
413 #define VMXNET3_ERR_NOEOP 0x80000000 /* cannot find the EOP desc of a pkt */
414 #define VMXNET3_ERR_TXD_REUSE 0x80000001 /* reuse a TxDesc before tx completion */
415 #define VMXNET3_ERR_BIG_PKT 0x80000002 /* too many TxDesc for a pkt */
416 #define VMXNET3_ERR_DESC_NOT_SPT 0x80000003 /* descriptor type not supported */
417 #define VMXNET3_ERR_SMALL_BUF 0x80000004 /* type 0 buffer too small */
418 #define VMXNET3_ERR_STRESS 0x80000005 /* stress option firing in vmkernel */
419 #define VMXNET3_ERR_SWITCH 0x80000006 /* mode switch failure */
420 #define VMXNET3_ERR_TXD_INVALID 0x80000007 /* invalid TxDesc */
422 /* completion descriptor types */
423 #define VMXNET3_CDTYPE_TXCOMP 0 /* Tx Completion Descriptor */
424 #define VMXNET3_CDTYPE_RXCOMP 3 /* Rx Completion Descriptor */
425 #define VMXNET3_CDTYPE_RXCOMP_LRO 4 /* Rx Completion Descriptor for LRO */
427 #define VMXNET3_GOS_BITS_UNK 0 /* unknown */
428 #define VMXNET3_GOS_BITS_32 1
429 #define VMXNET3_GOS_BITS_64 2
431 #define VMXNET3_GOS_TYPE_UNK 0 /* unknown */
432 #define VMXNET3_GOS_TYPE_LINUX 1
433 #define VMXNET3_GOS_TYPE_WIN 2
434 #define VMXNET3_GOS_TYPE_SOLARIS 3
435 #define VMXNET3_GOS_TYPE_FREEBSD 4
436 #define VMXNET3_GOS_TYPE_PXE 5
438 /* All structures in DriverShared are padded to multiples of 8 bytes */
441 #include "vmware_pack_begin.h"
442 struct Vmxnet3_GOSInfo {
443 #ifdef __BIG_ENDIAN_BITFIELD
444 uint32 gosMisc: 10; /* other info about gos */
445 uint32 gosVer: 16; /* gos version */
446 uint32 gosType: 4; /* which guest */
447 uint32 gosBits: 2; /* 32-bit or 64-bit? */
449 uint32 gosBits: 2; /* 32-bit or 64-bit? */
450 uint32 gosType: 4; /* which guest */
451 uint32 gosVer: 16; /* gos version */
452 uint32 gosMisc: 10; /* other info about gos */
453 #endif /* __BIG_ENDIAN_BITFIELD */
455 #include "vmware_pack_end.h"
459 #include "vmware_pack_begin.h"
460 struct Vmxnet3_DriverInfo {
461 __le32 version; /* driver version */
463 __le32 vmxnet3RevSpt; /* vmxnet3 revision supported */
464 __le32 uptVerSpt; /* upt version supported */
466 #include "vmware_pack_end.h"
469 #define VMXNET3_REV1_MAGIC 0xbabefee1
472 * QueueDescPA must be 128 bytes aligned. It points to an array of
473 * Vmxnet3_TxQueueDesc followed by an array of Vmxnet3_RxQueueDesc.
474 * The number of Vmxnet3_TxQueueDesc/Vmxnet3_RxQueueDesc are specified by
475 * Vmxnet3_MiscConf.numTxQueues/numRxQueues, respectively.
477 #define VMXNET3_QUEUE_DESC_ALIGN 128
480 #include "vmware_pack_begin.h"
481 struct Vmxnet3_MiscConf {
482 Vmxnet3_DriverInfo driverInfo;
484 __le64 ddPA; /* driver data PA */
485 __le64 queueDescPA; /* queue descriptor table PA */
486 __le32 ddLen; /* driver data len */
487 __le32 queueDescLen; /* queue descriptor table len, in bytes */
494 #include "vmware_pack_end.h"
498 #include "vmware_pack_begin.h"
499 struct Vmxnet3_TxQueueConf {
501 __le64 dataRingBasePA;
502 __le64 compRingBasePA;
503 __le64 ddPA; /* driver data */
505 __le32 txRingSize; /* # of tx desc */
506 __le32 dataRingSize; /* # of data desc */
507 __le32 compRingSize; /* # of comp desc */
508 __le32 ddLen; /* size of driver data */
512 #include "vmware_pack_end.h"
516 #include "vmware_pack_begin.h"
517 struct Vmxnet3_RxQueueConf {
518 __le64 rxRingBasePA[2];
519 __le64 compRingBasePA;
520 __le64 ddPA; /* driver data */
522 __le32 rxRingSize[2]; /* # of rx desc */
523 __le32 compRingSize; /* # of rx comp desc */
524 __le32 ddLen; /* size of driver data */
528 #include "vmware_pack_end.h"
531 enum vmxnet3_intr_mask_mode {
532 VMXNET3_IMM_AUTO = 0,
533 VMXNET3_IMM_ACTIVE = 1,
537 enum vmxnet3_intr_type {
544 #define VMXNET3_MAX_TX_QUEUES 8
545 #define VMXNET3_MAX_RX_QUEUES 16
546 /* addition 1 for events */
547 #define VMXNET3_MAX_INTRS 25
549 /* value of intrCtrl */
550 #define VMXNET3_IC_DISABLE_ALL 0x1 /* bit 0 */
553 #include "vmware_pack_begin.h"
554 struct Vmxnet3_IntrConf {
556 uint8 numIntrs; /* # of interrupts */
558 uint8 modLevels[VMXNET3_MAX_INTRS]; /* moderation level for each intr */
562 #include "vmware_pack_end.h"
565 /* one bit per VLAN ID, the size is in the units of uint32 */
566 #define VMXNET3_VFT_SIZE (4096 / (sizeof(uint32) * 8))
569 #include "vmware_pack_begin.h"
570 struct Vmxnet3_QueueStatus {
575 #include "vmware_pack_end.h"
579 #include "vmware_pack_begin.h"
580 struct Vmxnet3_TxQueueCtrl {
581 __le32 txNumDeferred;
585 #include "vmware_pack_end.h"
589 #include "vmware_pack_begin.h"
590 struct Vmxnet3_RxQueueCtrl {
595 #include "vmware_pack_end.h"
598 #define VMXNET3_RXM_UCAST 0x01 /* unicast only */
599 #define VMXNET3_RXM_MCAST 0x02 /* multicast passing the filters */
600 #define VMXNET3_RXM_BCAST 0x04 /* broadcast only */
601 #define VMXNET3_RXM_ALL_MULTI 0x08 /* all multicast */
602 #define VMXNET3_RXM_PROMISC 0x10 /* promiscuous */
605 #include "vmware_pack_begin.h"
606 struct Vmxnet3_RxFilterConf {
607 __le32 rxMode; /* VMXNET3_RXM_xxx */
608 __le16 mfTableLen; /* size of the multicast filter table */
610 __le64 mfTablePA; /* PA of the multicast filters table */
611 __le32 vfTable[VMXNET3_VFT_SIZE]; /* vlan filter */
613 #include "vmware_pack_end.h"
614 Vmxnet3_RxFilterConf;
616 #define VMXNET3_PM_MAX_FILTERS 6
617 #define VMXNET3_PM_MAX_PATTERN_SIZE 128
618 #define VMXNET3_PM_MAX_MASK_SIZE (VMXNET3_PM_MAX_PATTERN_SIZE / 8)
620 #define VMXNET3_PM_WAKEUP_MAGIC 0x01 /* wake up on magic pkts */
621 #define VMXNET3_PM_WAKEUP_FILTER 0x02 /* wake up on pkts matching filters */
624 #include "vmware_pack_begin.h"
625 struct Vmxnet3_PM_PktFilter {
628 uint8 mask[VMXNET3_PM_MAX_MASK_SIZE];
629 uint8 pattern[VMXNET3_PM_MAX_PATTERN_SIZE];
632 #include "vmware_pack_end.h"
633 Vmxnet3_PM_PktFilter;
636 #include "vmware_pack_begin.h"
637 struct Vmxnet3_PMConf {
638 __le16 wakeUpEvents; /* VMXNET3_PM_WAKEUP_xxx */
641 Vmxnet3_PM_PktFilter filters[VMXNET3_PM_MAX_FILTERS];
643 #include "vmware_pack_end.h"
647 #include "vmware_pack_begin.h"
648 struct Vmxnet3_VariableLenConfDesc {
653 #include "vmware_pack_end.h"
654 Vmxnet3_VariableLenConfDesc;
657 #include "vmware_pack_begin.h"
658 struct Vmxnet3_DSDevRead {
659 /* read-only region for device, read by dev in response to a SET cmd */
660 Vmxnet3_MiscConf misc;
661 Vmxnet3_IntrConf intrConf;
662 Vmxnet3_RxFilterConf rxFilterConf;
663 Vmxnet3_VariableLenConfDesc rssConfDesc;
664 Vmxnet3_VariableLenConfDesc pmConfDesc;
665 Vmxnet3_VariableLenConfDesc pluginConfDesc;
667 #include "vmware_pack_end.h"
671 #include "vmware_pack_begin.h"
672 struct Vmxnet3_TxQueueDesc {
673 Vmxnet3_TxQueueCtrl ctrl;
674 Vmxnet3_TxQueueConf conf;
675 /* Driver read after a GET command */
676 Vmxnet3_QueueStatus status;
678 uint8 _pad[88]; /* 128 aligned */
680 #include "vmware_pack_end.h"
684 #include "vmware_pack_begin.h"
685 struct Vmxnet3_RxQueueDesc {
686 Vmxnet3_RxQueueCtrl ctrl;
687 Vmxnet3_RxQueueConf conf;
688 /* Driver read after a GET command */
689 Vmxnet3_QueueStatus status;
691 uint8 _pad[88]; /* 128 aligned */
693 #include "vmware_pack_end.h"
697 #include "vmware_pack_begin.h"
698 struct Vmxnet3_DriverShared {
700 __le32 pad; /* make devRead start at 64-bit boundaries */
701 Vmxnet3_DSDevRead devRead;
705 #include "vmware_pack_end.h"
706 Vmxnet3_DriverShared;
708 #define VMXNET3_ECR_RQERR (1 << 0)
709 #define VMXNET3_ECR_TQERR (1 << 1)
710 #define VMXNET3_ECR_LINK (1 << 2)
711 #define VMXNET3_ECR_DIC (1 << 3)
712 #define VMXNET3_ECR_DEBUG (1 << 4)
714 /* flip the gen bit of a ring */
715 #define VMXNET3_FLIP_RING_GEN(gen) ((gen) = (gen) ^ 0x1)
717 /* only use this if moving the idx won't affect the gen bit */
718 #define VMXNET3_INC_RING_IDX_ONLY(idx, ring_size) \
721 if (UNLIKELY((idx) == (ring_size))) {\
726 #define VMXNET3_SET_VFTABLE_ENTRY(vfTable, vid) \
727 vfTable[vid >> 5] |= (1 << (vid & 31))
728 #define VMXNET3_CLEAR_VFTABLE_ENTRY(vfTable, vid) \
729 vfTable[vid >> 5] &= ~(1 << (vid & 31))
731 #define VMXNET3_VFTABLE_ENTRY_IS_SET(vfTable, vid) \
732 ((vfTable[vid >> 5] & (1 << (vid & 31))) != 0)
734 #define VMXNET3_MAX_MTU 9000
735 #define VMXNET3_MIN_MTU 60
737 #define VMXNET3_LINK_UP (10000 << 16 | 1) // 10 Gbps, up
738 #define VMXNET3_LINK_DOWN 0
740 #define VMXWIFI_DRIVER_SHARED_LEN 8192
742 #define VMXNET3_DID_PASSTHRU 0xFFFF
744 #endif /* _VMXNET3_DEFS_H_ */