1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright (C) 2007 VMware, Inc. All rights reserved.
8 * Definitions shared by device emulation and guest drivers for
12 #ifndef _VMXNET3_DEFS_H_
13 #define _VMXNET3_DEFS_H_
15 #include "vmxnet3_osdep.h"
16 #include "upt1_defs.h"
18 /* all registers are 32 bit wide */
20 #define VMXNET3_REG_VRRS 0x0 /* Vmxnet3 Revision Report Selection */
21 #define VMXNET3_REG_UVRS 0x8 /* UPT Version Report Selection */
22 #define VMXNET3_REG_DSAL 0x10 /* Driver Shared Address Low */
23 #define VMXNET3_REG_DSAH 0x18 /* Driver Shared Address High */
24 #define VMXNET3_REG_CMD 0x20 /* Command */
25 #define VMXNET3_REG_MACL 0x28 /* MAC Address Low */
26 #define VMXNET3_REG_MACH 0x30 /* MAC Address High */
27 #define VMXNET3_REG_ICR 0x38 /* Interrupt Cause Register */
28 #define VMXNET3_REG_ECR 0x40 /* Event Cause Register */
30 #define VMXNET3_REG_WSAL 0xF00 /* Wireless Shared Address Lo */
31 #define VMXNET3_REG_WSAH 0xF08 /* Wireless Shared Address Hi */
32 #define VMXNET3_REG_WCMD 0xF18 /* Wireless Command */
35 #define VMXNET3_REG_IMR 0x0 /* Interrupt Mask Register */
36 #define VMXNET3_REG_TXPROD 0x600 /* Tx Producer Index */
37 #define VMXNET3_REG_RXPROD 0x800 /* Rx Producer Index for ring 1 */
38 #define VMXNET3_REG_RXPROD2 0xA00 /* Rx Producer Index for ring 2 */
40 #define VMXNET3_PT_REG_SIZE 4096 /* BAR 0 */
41 #define VMXNET3_VD_REG_SIZE 4096 /* BAR 1 */
44 * The two Vmxnet3 MMIO Register PCI BARs (BAR 0 at offset 10h and BAR 1 at
45 * offset 14h) as well as the MSI-X BAR are combined into one PhysMem region:
46 * <-VMXNET3_PT_REG_SIZE-><-VMXNET3_VD_REG_SIZE-><-VMXNET3_MSIX_BAR_SIZE-->
47 * -------------------------------------------------------------------------
48 * |Pass Thru Registers | Virtual Dev Registers | MSI-X Vector/PBA Table |
49 * -------------------------------------------------------------------------
50 * VMXNET3_MSIX_BAR_SIZE is defined in "vmxnet3Int.h"
52 #define VMXNET3_PHYSMEM_PAGES 4
54 #define VMXNET3_REG_ALIGN 8 /* All registers are 8-byte aligned. */
55 #define VMXNET3_REG_ALIGN_MASK 0x7
57 /* I/O Mapped access to registers */
58 #define VMXNET3_IO_TYPE_PT 0
59 #define VMXNET3_IO_TYPE_VD 1
60 #define VMXNET3_IO_ADDR(type, reg) (((type) << 24) | ((reg) & 0xFFFFFF))
61 #define VMXNET3_IO_TYPE(addr) ((addr) >> 24)
62 #define VMXNET3_IO_REG(addr) ((addr) & 0xFFFFFF)
75 VMXNET3_CMD_FIRST_SET = 0xCAFE0000,
76 VMXNET3_CMD_ACTIVATE_DEV = VMXNET3_CMD_FIRST_SET,
77 VMXNET3_CMD_QUIESCE_DEV,
78 VMXNET3_CMD_RESET_DEV,
79 VMXNET3_CMD_UPDATE_RX_MODE,
80 VMXNET3_CMD_UPDATE_MAC_FILTERS,
81 VMXNET3_CMD_UPDATE_VLAN_FILTERS,
82 VMXNET3_CMD_UPDATE_RSSIDT,
83 VMXNET3_CMD_UPDATE_IML,
84 VMXNET3_CMD_UPDATE_PMCFG,
85 VMXNET3_CMD_UPDATE_FEATURE,
86 VMXNET3_CMD_STOP_EMULATION,
87 VMXNET3_CMD_LOAD_PLUGIN,
88 VMXNET3_CMD_ACTIVATE_VF,
89 VMXNET3_CMD_RESERVED3,
90 VMXNET3_CMD_RESERVED4,
91 VMXNET3_CMD_REGISTER_MEMREGS,
93 VMXNET3_CMD_FIRST_GET = 0xF00D0000,
94 VMXNET3_CMD_GET_QUEUE_STATUS = VMXNET3_CMD_FIRST_GET,
95 VMXNET3_CMD_GET_STATS,
97 VMXNET3_CMD_GET_PERM_MAC_LO,
98 VMXNET3_CMD_GET_PERM_MAC_HI,
99 VMXNET3_CMD_GET_DID_LO,
100 VMXNET3_CMD_GET_DID_HI,
101 VMXNET3_CMD_GET_DEV_EXTRA_INFO,
102 VMXNET3_CMD_GET_CONF_INTR,
103 VMXNET3_CMD_GET_ADAPTIVE_RING_INFO,
104 VMXNET3_CMD_GET_TXDATA_DESC_SIZE,
105 VMXNET3_CMD_RESERVED5,
108 /* Adaptive Ring Info Flags */
109 #define VMXNET3_DISABLE_ADAPTIVE_RING 1
112 * Little Endian layout of bitfields -
113 * Byte 0 : 7.....len.....0
114 * Byte 1 : rsvd gen 13.len.8
115 * Byte 2 : 5.msscof.0 ext1 dtype
116 * Byte 3 : 13...msscof...6
118 * Big Endian layout of bitfields -
119 * Byte 0: 13...msscof...6
120 * Byte 1 : 5.msscof.0 ext1 dtype
121 * Byte 2 : rsvd gen 13.len.8
122 * Byte 3 : 7.....len.....0
124 * Thus, le32_to_cpu on the dword will allow the big endian driver to read
125 * the bit fields correctly. And cpu_to_le32 will convert bitfields
126 * bit fields written by big endian driver to format required by device.
130 #include "vmware_pack_begin.h"
131 struct Vmxnet3_TxDesc {
134 #ifdef __BIG_ENDIAN_BITFIELD
135 uint32 msscof:14; /* MSS, checksum offset, flags */
137 uint32 dtype:1; /* descriptor type */
139 uint32 gen:1; /* generation bit */
143 uint32 gen:1; /* generation bit */
145 uint32 dtype:1; /* descriptor type */
147 uint32 msscof:14; /* MSS, checksum offset, flags */
148 #endif /* __BIG_ENDIAN_BITFIELD */
150 #ifdef __BIG_ENDIAN_BITFIELD
151 uint32 tci:16; /* Tag to Insert */
152 uint32 ti:1; /* VLAN Tag Insertion */
154 uint32 cq:1; /* completion request */
155 uint32 eop:1; /* End Of Packet */
156 uint32 om:2; /* offload mode */
157 uint32 hlen:10; /* header len */
159 uint32 hlen:10; /* header len */
160 uint32 om:2; /* offload mode */
161 uint32 eop:1; /* End Of Packet */
162 uint32 cq:1; /* completion request */
164 uint32 ti:1; /* VLAN Tag Insertion */
165 uint32 tci:16; /* Tag to Insert */
166 #endif /* __BIG_ENDIAN_BITFIELD */
168 #include "vmware_pack_end.h"
171 /* TxDesc.OM values */
172 #define VMXNET3_OM_NONE 0
173 #define VMXNET3_OM_CSUM 2
174 #define VMXNET3_OM_TSO 3
176 /* fields in TxDesc we access w/o using bit fields */
177 #define VMXNET3_TXD_EOP_SHIFT 12
178 #define VMXNET3_TXD_CQ_SHIFT 13
179 #define VMXNET3_TXD_GEN_SHIFT 14
180 #define VMXNET3_TXD_EOP_DWORD_SHIFT 3
181 #define VMXNET3_TXD_GEN_DWORD_SHIFT 2
183 #define VMXNET3_TXD_CQ (1 << VMXNET3_TXD_CQ_SHIFT)
184 #define VMXNET3_TXD_EOP (1 << VMXNET3_TXD_EOP_SHIFT)
185 #define VMXNET3_TXD_GEN (1 << VMXNET3_TXD_GEN_SHIFT)
187 #define VMXNET3_TXD_GEN_SIZE 1
188 #define VMXNET3_TXD_EOP_SIZE 1
190 #define VMXNET3_HDR_COPY_SIZE 128
193 #include "vmware_pack_begin.h"
194 struct Vmxnet3_TxDataDesc {
195 uint8 data[VMXNET3_HDR_COPY_SIZE];
197 #include "vmware_pack_end.h"
200 #define VMXNET3_TCD_GEN_SHIFT 31
201 #define VMXNET3_TCD_GEN_SIZE 1
202 #define VMXNET3_TCD_TXIDX_SHIFT 0
203 #define VMXNET3_TCD_TXIDX_SIZE 12
204 #define VMXNET3_TCD_GEN_DWORD_SHIFT 3
207 #include "vmware_pack_begin.h"
208 struct Vmxnet3_TxCompDesc {
209 uint32 txdIdx:12; /* Index of the EOP TxDesc */
216 uint32 type:7; /* completion type */
217 uint32 gen:1; /* generation bit */
219 #include "vmware_pack_end.h"
223 #include "vmware_pack_begin.h"
224 struct Vmxnet3_RxDesc {
227 #ifdef __BIG_ENDIAN_BITFIELD
228 uint32 gen:1; /* Generation bit */
230 uint32 dtype:1; /* Descriptor type */
231 uint32 btype:1; /* Buffer Type */
235 uint32 btype:1; /* Buffer Type */
236 uint32 dtype:1; /* Descriptor type */
238 uint32 gen:1; /* Generation bit */
242 #include "vmware_pack_end.h"
245 /* values of RXD.BTYPE */
246 #define VMXNET3_RXD_BTYPE_HEAD 0 /* head only */
247 #define VMXNET3_RXD_BTYPE_BODY 1 /* body only */
249 /* fields in RxDesc we access w/o using bit fields */
250 #define VMXNET3_RXD_BTYPE_SHIFT 14
251 #define VMXNET3_RXD_GEN_SHIFT 31
254 #include "vmware_pack_begin.h"
255 struct Vmxnet3_RxCompDesc {
256 #ifdef __BIG_ENDIAN_BITFIELD
258 uint32 cnc:1; /* Checksum Not Calculated */
259 uint32 rssType:4; /* RSS hash type used */
260 uint32 rqID:10; /* rx queue/ring ID */
261 uint32 sop:1; /* Start of Packet */
262 uint32 eop:1; /* End of Packet */
264 uint32 rxdIdx:12; /* Index of the RxDesc */
266 uint32 rxdIdx:12; /* Index of the RxDesc */
268 uint32 eop:1; /* End of Packet */
269 uint32 sop:1; /* Start of Packet */
270 uint32 rqID:10; /* rx queue/ring ID */
271 uint32 rssType:4; /* RSS hash type used */
272 uint32 cnc:1; /* Checksum Not Calculated */
274 #endif /* __BIG_ENDIAN_BITFIELD */
276 __le32 rssHash; /* RSS hash value */
278 #ifdef __BIG_ENDIAN_BITFIELD
279 uint32 tci:16; /* Tag stripped */
280 uint32 ts:1; /* Tag is stripped */
281 uint32 err:1; /* Error */
282 uint32 len:14; /* data length */
284 uint32 len:14; /* data length */
285 uint32 err:1; /* Error */
286 uint32 ts:1; /* Tag is stripped */
287 uint32 tci:16; /* Tag stripped */
288 #endif /* __BIG_ENDIAN_BITFIELD */
291 #ifdef __BIG_ENDIAN_BITFIELD
292 uint32 gen:1; /* generation bit */
293 uint32 type:7; /* completion type */
294 uint32 fcs:1; /* Frame CRC correct */
295 uint32 frg:1; /* IP Fragment */
296 uint32 v4:1; /* IPv4 */
297 uint32 v6:1; /* IPv6 */
298 uint32 ipc:1; /* IP Checksum Correct */
299 uint32 tcp:1; /* TCP packet */
300 uint32 udp:1; /* UDP packet */
301 uint32 tuc:1; /* TCP/UDP Checksum Correct */
305 uint32 tuc:1; /* TCP/UDP Checksum Correct */
306 uint32 udp:1; /* UDP packet */
307 uint32 tcp:1; /* TCP packet */
308 uint32 ipc:1; /* IP Checksum Correct */
309 uint32 v6:1; /* IPv6 */
310 uint32 v4:1; /* IPv4 */
311 uint32 frg:1; /* IP Fragment */
312 uint32 fcs:1; /* Frame CRC correct */
313 uint32 type:7; /* completion type */
314 uint32 gen:1; /* generation bit */
315 #endif /* __BIG_ENDIAN_BITFIELD */
317 #include "vmware_pack_end.h"
321 #include "vmware_pack_begin.h"
322 struct Vmxnet3_RxCompDescExt {
324 uint8 segCnt; /* Number of aggregated packets */
325 uint8 dupAckCnt; /* Number of duplicate Acks */
326 __le16 tsDelta; /* TCP timestamp difference */
329 #include "vmware_pack_end.h"
330 Vmxnet3_RxCompDescExt;
332 /* fields in RxCompDesc we access via Vmxnet3_GenericDesc.dword[3] */
333 #define VMXNET3_RCD_TUC_SHIFT 16
334 #define VMXNET3_RCD_IPC_SHIFT 19
336 /* fields in RxCompDesc we access via Vmxnet3_GenericDesc.qword[1] */
337 #define VMXNET3_RCD_TYPE_SHIFT 56
338 #define VMXNET3_RCD_GEN_SHIFT 63
340 /* csum OK for TCP/UDP pkts over IP */
341 #define VMXNET3_RCD_CSUM_OK (1 << VMXNET3_RCD_TUC_SHIFT | 1 << VMXNET3_RCD_IPC_SHIFT)
343 /* value of RxCompDesc.rssType */
344 #define VMXNET3_RCD_RSS_TYPE_NONE 0
345 #define VMXNET3_RCD_RSS_TYPE_IPV4 1
346 #define VMXNET3_RCD_RSS_TYPE_TCPIPV4 2
347 #define VMXNET3_RCD_RSS_TYPE_IPV6 3
348 #define VMXNET3_RCD_RSS_TYPE_TCPIPV6 4
350 /* a union for accessing all cmd/completion descriptors */
351 typedef union Vmxnet3_GenericDesc {
357 Vmxnet3_TxCompDesc tcd;
358 Vmxnet3_RxCompDesc rcd;
359 Vmxnet3_RxCompDescExt rcdExt;
360 } Vmxnet3_GenericDesc;
362 #define VMXNET3_INIT_GEN 1
364 /* Max size of a single tx buffer */
365 #define VMXNET3_MAX_TX_BUF_SIZE (1 << 14)
367 /* # of tx desc needed for a tx buffer size */
368 #define VMXNET3_TXD_NEEDED(size) (((size) + VMXNET3_MAX_TX_BUF_SIZE - 1) / VMXNET3_MAX_TX_BUF_SIZE)
370 /* max # of tx descs for a non-tso pkt */
371 #define VMXNET3_MAX_TXD_PER_PKT 16
373 /* Max size of a single rx buffer */
374 #define VMXNET3_MAX_RX_BUF_SIZE ((1 << 14) - 1)
375 /* Minimum size of a type 0 buffer */
376 #define VMXNET3_MIN_T0_BUF_SIZE 128
377 #define VMXNET3_MAX_CSUM_OFFSET 1024
379 /* Ring base address alignment */
380 #define VMXNET3_RING_BA_ALIGN 512
381 #define VMXNET3_RING_BA_MASK (VMXNET3_RING_BA_ALIGN - 1)
383 /* Ring size must be a multiple of 32 */
384 #define VMXNET3_RING_SIZE_ALIGN 32
385 #define VMXNET3_RING_SIZE_MASK (VMXNET3_RING_SIZE_ALIGN - 1)
387 /* Tx Data Ring buffer size must be a multiple of 64 */
388 #define VMXNET3_TXDATA_DESC_SIZE_ALIGN 64
389 #define VMXNET3_TXDATA_DESC_SIZE_MASK (VMXNET3_TXDATA_DESC_SIZE_ALIGN - 1)
391 /* Rx Data Ring buffer size must be a multiple of 64 */
392 #define VMXNET3_RXDATA_DESC_SIZE_ALIGN 64
393 #define VMXNET3_RXDATA_DESC_SIZE_MASK (VMXNET3_RXDATA_DESC_SIZE_ALIGN - 1)
396 #define VMXNET3_TX_RING_MAX_SIZE 4096
397 #define VMXNET3_TC_RING_MAX_SIZE 4096
398 #define VMXNET3_RX_RING_MAX_SIZE 4096
399 #define VMXNET3_RC_RING_MAX_SIZE 8192
401 #define VMXNET3_TXDATA_DESC_MIN_SIZE 128
402 #define VMXNET3_TXDATA_DESC_MAX_SIZE 2048
404 #define VMXNET3_RXDATA_DESC_MAX_SIZE 2048
406 /* a list of reasons for queue stop */
408 #define VMXNET3_ERR_NOEOP 0x80000000 /* cannot find the EOP desc of a pkt */
409 #define VMXNET3_ERR_TXD_REUSE 0x80000001 /* reuse a TxDesc before tx completion */
410 #define VMXNET3_ERR_BIG_PKT 0x80000002 /* too many TxDesc for a pkt */
411 #define VMXNET3_ERR_DESC_NOT_SPT 0x80000003 /* descriptor type not supported */
412 #define VMXNET3_ERR_SMALL_BUF 0x80000004 /* type 0 buffer too small */
413 #define VMXNET3_ERR_STRESS 0x80000005 /* stress option firing in vmkernel */
414 #define VMXNET3_ERR_SWITCH 0x80000006 /* mode switch failure */
415 #define VMXNET3_ERR_TXD_INVALID 0x80000007 /* invalid TxDesc */
417 /* completion descriptor types */
418 #define VMXNET3_CDTYPE_TXCOMP 0 /* Tx Completion Descriptor */
419 #define VMXNET3_CDTYPE_RXCOMP 3 /* Rx Completion Descriptor */
420 #define VMXNET3_CDTYPE_RXCOMP_LRO 4 /* Rx Completion Descriptor for LRO */
422 #define VMXNET3_GOS_BITS_UNK 0 /* unknown */
423 #define VMXNET3_GOS_BITS_32 1
424 #define VMXNET3_GOS_BITS_64 2
426 #define VMXNET3_GOS_TYPE_UNK 0 /* unknown */
427 #define VMXNET3_GOS_TYPE_LINUX 1
428 #define VMXNET3_GOS_TYPE_WIN 2
429 #define VMXNET3_GOS_TYPE_SOLARIS 3
430 #define VMXNET3_GOS_TYPE_FREEBSD 4
431 #define VMXNET3_GOS_TYPE_PXE 5
433 /* All structures in DriverShared are padded to multiples of 8 bytes */
436 #include "vmware_pack_begin.h"
437 struct Vmxnet3_GOSInfo {
438 #ifdef __BIG_ENDIAN_BITFIELD
439 uint32 gosMisc: 10; /* other info about gos */
440 uint32 gosVer: 16; /* gos version */
441 uint32 gosType: 4; /* which guest */
442 uint32 gosBits: 2; /* 32-bit or 64-bit? */
444 uint32 gosBits: 2; /* 32-bit or 64-bit? */
445 uint32 gosType: 4; /* which guest */
446 uint32 gosVer: 16; /* gos version */
447 uint32 gosMisc: 10; /* other info about gos */
448 #endif /* __BIG_ENDIAN_BITFIELD */
450 #include "vmware_pack_end.h"
454 #include "vmware_pack_begin.h"
455 struct Vmxnet3_DriverInfo {
456 __le32 version; /* driver version */
458 __le32 vmxnet3RevSpt; /* vmxnet3 revision supported */
459 __le32 uptVerSpt; /* upt version supported */
461 #include "vmware_pack_end.h"
464 #define VMXNET3_REV1_MAGIC 0xbabefee1
467 * QueueDescPA must be 128 bytes aligned. It points to an array of
468 * Vmxnet3_TxQueueDesc followed by an array of Vmxnet3_RxQueueDesc.
469 * The number of Vmxnet3_TxQueueDesc/Vmxnet3_RxQueueDesc are specified by
470 * Vmxnet3_MiscConf.numTxQueues/numRxQueues, respectively.
472 #define VMXNET3_QUEUE_DESC_ALIGN 128
475 #include "vmware_pack_begin.h"
476 struct Vmxnet3_MiscConf {
477 Vmxnet3_DriverInfo driverInfo;
479 __le64 ddPA; /* driver data PA */
480 __le64 queueDescPA; /* queue descriptor table PA */
481 __le32 ddLen; /* driver data len */
482 __le32 queueDescLen; /* queue descriptor table len, in bytes */
489 #include "vmware_pack_end.h"
493 #include "vmware_pack_begin.h"
494 struct Vmxnet3_TxQueueConf {
496 __le64 dataRingBasePA;
497 __le64 compRingBasePA;
498 __le64 ddPA; /* driver data */
500 __le32 txRingSize; /* # of tx desc */
501 __le32 dataRingSize; /* # of data desc */
502 __le32 compRingSize; /* # of comp desc */
503 __le32 ddLen; /* size of driver data */
506 __le16 txDataRingDescSize;
509 #include "vmware_pack_end.h"
513 #include "vmware_pack_begin.h"
514 struct Vmxnet3_RxQueueConf {
515 __le64 rxRingBasePA[2];
516 __le64 compRingBasePA;
517 __le64 ddPA; /* driver data */
518 __le64 rxDataRingBasePA;
519 __le32 rxRingSize[2]; /* # of rx desc */
520 __le32 compRingSize; /* # of rx comp desc */
521 __le32 ddLen; /* size of driver data */
524 __le16 rxDataRingDescSize; /* size of rx data ring buffer */
527 #include "vmware_pack_end.h"
530 enum vmxnet3_intr_mask_mode {
531 VMXNET3_IMM_AUTO = 0,
532 VMXNET3_IMM_ACTIVE = 1,
536 enum vmxnet3_intr_type {
543 #define VMXNET3_MAX_TX_QUEUES 8
544 #define VMXNET3_MAX_RX_QUEUES 16
545 /* addition 1 for events */
546 #define VMXNET3_MAX_INTRS 25
548 /* value of intrCtrl */
549 #define VMXNET3_IC_DISABLE_ALL 0x1 /* bit 0 */
552 #include "vmware_pack_begin.h"
553 struct Vmxnet3_IntrConf {
555 uint8 numIntrs; /* # of interrupts */
557 uint8 modLevels[VMXNET3_MAX_INTRS]; /* moderation level for each intr */
561 #include "vmware_pack_end.h"
564 /* one bit per VLAN ID, the size is in the units of uint32 */
565 #define VMXNET3_VFT_SIZE (4096 / (sizeof(uint32) * 8))
568 #include "vmware_pack_begin.h"
569 struct Vmxnet3_QueueStatus {
574 #include "vmware_pack_end.h"
578 #include "vmware_pack_begin.h"
579 struct Vmxnet3_TxQueueCtrl {
580 __le32 txNumDeferred;
584 #include "vmware_pack_end.h"
588 #include "vmware_pack_begin.h"
589 struct Vmxnet3_RxQueueCtrl {
594 #include "vmware_pack_end.h"
597 #define VMXNET3_RXM_UCAST 0x01 /* unicast only */
598 #define VMXNET3_RXM_MCAST 0x02 /* multicast passing the filters */
599 #define VMXNET3_RXM_BCAST 0x04 /* broadcast only */
600 #define VMXNET3_RXM_ALL_MULTI 0x08 /* all multicast */
601 #define VMXNET3_RXM_PROMISC 0x10 /* promiscuous */
604 #include "vmware_pack_begin.h"
605 struct Vmxnet3_RxFilterConf {
606 __le32 rxMode; /* VMXNET3_RXM_xxx */
607 __le16 mfTableLen; /* size of the multicast filter table */
609 __le64 mfTablePA; /* PA of the multicast filters table */
610 __le32 vfTable[VMXNET3_VFT_SIZE]; /* vlan filter */
612 #include "vmware_pack_end.h"
613 Vmxnet3_RxFilterConf;
615 #define VMXNET3_PM_MAX_FILTERS 6
616 #define VMXNET3_PM_MAX_PATTERN_SIZE 128
617 #define VMXNET3_PM_MAX_MASK_SIZE (VMXNET3_PM_MAX_PATTERN_SIZE / 8)
619 #define VMXNET3_PM_WAKEUP_MAGIC 0x01 /* wake up on magic pkts */
620 #define VMXNET3_PM_WAKEUP_FILTER 0x02 /* wake up on pkts matching filters */
623 #include "vmware_pack_begin.h"
624 struct Vmxnet3_PM_PktFilter {
627 uint8 mask[VMXNET3_PM_MAX_MASK_SIZE];
628 uint8 pattern[VMXNET3_PM_MAX_PATTERN_SIZE];
631 #include "vmware_pack_end.h"
632 Vmxnet3_PM_PktFilter;
635 #include "vmware_pack_begin.h"
636 struct Vmxnet3_PMConf {
637 __le16 wakeUpEvents; /* VMXNET3_PM_WAKEUP_xxx */
640 Vmxnet3_PM_PktFilter filters[VMXNET3_PM_MAX_FILTERS];
642 #include "vmware_pack_end.h"
646 #include "vmware_pack_begin.h"
647 struct Vmxnet3_VariableLenConfDesc {
652 #include "vmware_pack_end.h"
653 Vmxnet3_VariableLenConfDesc;
656 #include "vmware_pack_begin.h"
657 struct Vmxnet3_DSDevRead {
658 /* read-only region for device, read by dev in response to a SET cmd */
659 Vmxnet3_MiscConf misc;
660 Vmxnet3_IntrConf intrConf;
661 Vmxnet3_RxFilterConf rxFilterConf;
662 Vmxnet3_VariableLenConfDesc rssConfDesc;
663 Vmxnet3_VariableLenConfDesc pmConfDesc;
664 Vmxnet3_VariableLenConfDesc pluginConfDesc;
666 #include "vmware_pack_end.h"
670 #include "vmware_pack_begin.h"
671 struct Vmxnet3_TxQueueDesc {
672 Vmxnet3_TxQueueCtrl ctrl;
673 Vmxnet3_TxQueueConf conf;
674 /* Driver read after a GET command */
675 Vmxnet3_QueueStatus status;
677 uint8 _pad[88]; /* 128 aligned */
679 #include "vmware_pack_end.h"
683 #include "vmware_pack_begin.h"
684 struct Vmxnet3_RxQueueDesc {
685 Vmxnet3_RxQueueCtrl ctrl;
686 Vmxnet3_RxQueueConf conf;
687 /* Driver read after a GET command */
688 Vmxnet3_QueueStatus status;
690 uint8 _pad[88]; /* 128 aligned */
692 #include "vmware_pack_end.h"
696 #include "vmware_pack_begin.h"
697 struct Vmxnet3_SetPolling {
700 #include "vmware_pack_end.h"
704 #include "vmware_pack_begin.h"
705 struct Vmxnet3_MemoryRegion {
708 __le16 txQueueBits; /* bit n corresponding to tx queue n */
709 __le16 rxQueueBits; /* bit n corresponding to rx queue n */
711 #include "vmware_pack_end.h"
712 Vmxnet3_MemoryRegion;
714 #define MAX_MEMORY_REGION_PER_QUEUE 16
715 #define MAX_MEMORY_REGION_PER_DEVICE 256
718 #include "vmware_pack_begin.h"
719 struct Vmxnet3_MemRegs {
722 Vmxnet3_MemoryRegion memRegs[1];
724 #include "vmware_pack_end.h"
728 * If the command data <= 16 bytes, use the shared memory direcly.
729 * Otherwise, use the variable length configuration descriptor.
732 #include "vmware_pack_begin.h"
733 union Vmxnet3_CmdInfo {
734 Vmxnet3_VariableLenConfDesc varConf;
735 Vmxnet3_SetPolling setPolling;
738 #include "vmware_pack_end.h"
742 #include "vmware_pack_begin.h"
743 struct Vmxnet3_DriverShared {
745 __le32 pad; /* make devRead start at 64-bit boundaries */
746 Vmxnet3_DSDevRead devRead;
752 Vmxnet3_CmdInfo cmdInfo; /* only valid in the context of executing the
757 #include "vmware_pack_end.h"
758 Vmxnet3_DriverShared;
760 #define VMXNET3_ECR_RQERR (1 << 0)
761 #define VMXNET3_ECR_TQERR (1 << 1)
762 #define VMXNET3_ECR_LINK (1 << 2)
763 #define VMXNET3_ECR_DIC (1 << 3)
764 #define VMXNET3_ECR_DEBUG (1 << 4)
766 /* flip the gen bit of a ring */
767 #define VMXNET3_FLIP_RING_GEN(gen) ((gen) = (gen) ^ 0x1)
769 /* only use this if moving the idx won't affect the gen bit */
770 #define VMXNET3_INC_RING_IDX_ONLY(idx, ring_size) \
773 if (UNLIKELY((idx) == (ring_size))) {\
778 #define VMXNET3_SET_VFTABLE_ENTRY(vfTable, vid) \
779 vfTable[vid >> 5] |= (1 << (vid & 31))
780 #define VMXNET3_CLEAR_VFTABLE_ENTRY(vfTable, vid) \
781 vfTable[vid >> 5] &= ~(1 << (vid & 31))
783 #define VMXNET3_VFTABLE_ENTRY_IS_SET(vfTable, vid) \
784 ((vfTable[vid >> 5] & (1 << (vid & 31))) != 0)
786 #define VMXNET3_MAX_MTU 9000
787 #define VMXNET3_MIN_MTU 60
789 #define VMXNET3_LINK_UP (10000 << 16 | 1) // 10 Gbps, up
790 #define VMXNET3_LINK_DOWN 0
792 #define VMXWIFI_DRIVER_SHARED_LEN 8192
794 #define VMXNET3_DID_PASSTHRU 0xFFFF
796 #endif /* _VMXNET3_DEFS_H_ */