1 /*********************************************************
2 * Copyright (C) 2007 VMware, Inc. All rights reserved.
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 *********************************************************/
31 * Definitions shared by device emulation and guest drivers for
35 #ifndef _VMXNET3_DEFS_H_
36 #define _VMXNET3_DEFS_H_
38 #include "vmxnet3_osdep.h"
39 #include "upt1_defs.h"
41 /* all registers are 32 bit wide */
43 #define VMXNET3_REG_VRRS 0x0 /* Vmxnet3 Revision Report Selection */
44 #define VMXNET3_REG_UVRS 0x8 /* UPT Version Report Selection */
45 #define VMXNET3_REG_DSAL 0x10 /* Driver Shared Address Low */
46 #define VMXNET3_REG_DSAH 0x18 /* Driver Shared Address High */
47 #define VMXNET3_REG_CMD 0x20 /* Command */
48 #define VMXNET3_REG_MACL 0x28 /* MAC Address Low */
49 #define VMXNET3_REG_MACH 0x30 /* MAC Address High */
50 #define VMXNET3_REG_ICR 0x38 /* Interrupt Cause Register */
51 #define VMXNET3_REG_ECR 0x40 /* Event Cause Register */
53 #define VMXNET3_REG_WSAL 0xF00 /* Wireless Shared Address Lo */
54 #define VMXNET3_REG_WSAH 0xF08 /* Wireless Shared Address Hi */
55 #define VMXNET3_REG_WCMD 0xF18 /* Wireless Command */
58 #define VMXNET3_REG_IMR 0x0 /* Interrupt Mask Register */
59 #define VMXNET3_REG_TXPROD 0x600 /* Tx Producer Index */
60 #define VMXNET3_REG_RXPROD 0x800 /* Rx Producer Index for ring 1 */
61 #define VMXNET3_REG_RXPROD2 0xA00 /* Rx Producer Index for ring 2 */
63 #define VMXNET3_PT_REG_SIZE 4096 /* BAR 0 */
64 #define VMXNET3_VD_REG_SIZE 4096 /* BAR 1 */
67 * The two Vmxnet3 MMIO Register PCI BARs (BAR 0 at offset 10h and BAR 1 at
68 * offset 14h) as well as the MSI-X BAR are combined into one PhysMem region:
69 * <-VMXNET3_PT_REG_SIZE-><-VMXNET3_VD_REG_SIZE-><-VMXNET3_MSIX_BAR_SIZE-->
70 * -------------------------------------------------------------------------
71 * |Pass Thru Registers | Virtual Dev Registers | MSI-X Vector/PBA Table |
72 * -------------------------------------------------------------------------
73 * VMXNET3_MSIX_BAR_SIZE is defined in "vmxnet3Int.h"
75 #define VMXNET3_PHYSMEM_PAGES 4
77 #define VMXNET3_REG_ALIGN 8 /* All registers are 8-byte aligned. */
78 #define VMXNET3_REG_ALIGN_MASK 0x7
80 /* I/O Mapped access to registers */
81 #define VMXNET3_IO_TYPE_PT 0
82 #define VMXNET3_IO_TYPE_VD 1
83 #define VMXNET3_IO_ADDR(type, reg) (((type) << 24) | ((reg) & 0xFFFFFF))
84 #define VMXNET3_IO_TYPE(addr) ((addr) >> 24)
85 #define VMXNET3_IO_REG(addr) ((addr) & 0xFFFFFF)
98 VMXNET3_CMD_FIRST_SET = 0xCAFE0000,
99 VMXNET3_CMD_ACTIVATE_DEV = VMXNET3_CMD_FIRST_SET,
100 VMXNET3_CMD_QUIESCE_DEV,
101 VMXNET3_CMD_RESET_DEV,
102 VMXNET3_CMD_UPDATE_RX_MODE,
103 VMXNET3_CMD_UPDATE_MAC_FILTERS,
104 VMXNET3_CMD_UPDATE_VLAN_FILTERS,
105 VMXNET3_CMD_UPDATE_RSSIDT,
106 VMXNET3_CMD_UPDATE_IML,
107 VMXNET3_CMD_UPDATE_PMCFG,
108 VMXNET3_CMD_UPDATE_FEATURE,
109 VMXNET3_CMD_STOP_EMULATION,
110 VMXNET3_CMD_LOAD_PLUGIN,
111 VMXNET3_CMD_ACTIVATE_VF,
112 VMXNET3_CMD_RESERVED3,
113 VMXNET3_CMD_RESERVED4,
114 VMXNET3_CMD_REGISTER_MEMREGS,
116 VMXNET3_CMD_FIRST_GET = 0xF00D0000,
117 VMXNET3_CMD_GET_QUEUE_STATUS = VMXNET3_CMD_FIRST_GET,
118 VMXNET3_CMD_GET_STATS,
119 VMXNET3_CMD_GET_LINK,
120 VMXNET3_CMD_GET_PERM_MAC_LO,
121 VMXNET3_CMD_GET_PERM_MAC_HI,
122 VMXNET3_CMD_GET_DID_LO,
123 VMXNET3_CMD_GET_DID_HI,
124 VMXNET3_CMD_GET_DEV_EXTRA_INFO,
125 VMXNET3_CMD_GET_CONF_INTR,
126 VMXNET3_CMD_GET_ADAPTIVE_RING_INFO,
127 VMXNET3_CMD_GET_TXDATA_DESC_SIZE,
128 VMXNET3_CMD_RESERVED5,
131 /* Adaptive Ring Info Flags */
132 #define VMXNET3_DISABLE_ADAPTIVE_RING 1
135 * Little Endian layout of bitfields -
136 * Byte 0 : 7.....len.....0
137 * Byte 1 : rsvd gen 13.len.8
138 * Byte 2 : 5.msscof.0 ext1 dtype
139 * Byte 3 : 13...msscof...6
141 * Big Endian layout of bitfields -
142 * Byte 0: 13...msscof...6
143 * Byte 1 : 5.msscof.0 ext1 dtype
144 * Byte 2 : rsvd gen 13.len.8
145 * Byte 3 : 7.....len.....0
147 * Thus, le32_to_cpu on the dword will allow the big endian driver to read
148 * the bit fields correctly. And cpu_to_le32 will convert bitfields
149 * bit fields written by big endian driver to format required by device.
153 #include "vmware_pack_begin.h"
154 struct Vmxnet3_TxDesc {
157 #ifdef __BIG_ENDIAN_BITFIELD
158 uint32 msscof:14; /* MSS, checksum offset, flags */
160 uint32 dtype:1; /* descriptor type */
162 uint32 gen:1; /* generation bit */
166 uint32 gen:1; /* generation bit */
168 uint32 dtype:1; /* descriptor type */
170 uint32 msscof:14; /* MSS, checksum offset, flags */
171 #endif /* __BIG_ENDIAN_BITFIELD */
173 #ifdef __BIG_ENDIAN_BITFIELD
174 uint32 tci:16; /* Tag to Insert */
175 uint32 ti:1; /* VLAN Tag Insertion */
177 uint32 cq:1; /* completion request */
178 uint32 eop:1; /* End Of Packet */
179 uint32 om:2; /* offload mode */
180 uint32 hlen:10; /* header len */
182 uint32 hlen:10; /* header len */
183 uint32 om:2; /* offload mode */
184 uint32 eop:1; /* End Of Packet */
185 uint32 cq:1; /* completion request */
187 uint32 ti:1; /* VLAN Tag Insertion */
188 uint32 tci:16; /* Tag to Insert */
189 #endif /* __BIG_ENDIAN_BITFIELD */
191 #include "vmware_pack_end.h"
194 /* TxDesc.OM values */
195 #define VMXNET3_OM_NONE 0
196 #define VMXNET3_OM_CSUM 2
197 #define VMXNET3_OM_TSO 3
199 /* fields in TxDesc we access w/o using bit fields */
200 #define VMXNET3_TXD_EOP_SHIFT 12
201 #define VMXNET3_TXD_CQ_SHIFT 13
202 #define VMXNET3_TXD_GEN_SHIFT 14
203 #define VMXNET3_TXD_EOP_DWORD_SHIFT 3
204 #define VMXNET3_TXD_GEN_DWORD_SHIFT 2
206 #define VMXNET3_TXD_CQ (1 << VMXNET3_TXD_CQ_SHIFT)
207 #define VMXNET3_TXD_EOP (1 << VMXNET3_TXD_EOP_SHIFT)
208 #define VMXNET3_TXD_GEN (1 << VMXNET3_TXD_GEN_SHIFT)
210 #define VMXNET3_TXD_GEN_SIZE 1
211 #define VMXNET3_TXD_EOP_SIZE 1
213 #define VMXNET3_HDR_COPY_SIZE 128
216 #include "vmware_pack_begin.h"
217 struct Vmxnet3_TxDataDesc {
218 uint8 data[VMXNET3_HDR_COPY_SIZE];
220 #include "vmware_pack_end.h"
223 #define VMXNET3_TCD_GEN_SHIFT 31
224 #define VMXNET3_TCD_GEN_SIZE 1
225 #define VMXNET3_TCD_TXIDX_SHIFT 0
226 #define VMXNET3_TCD_TXIDX_SIZE 12
227 #define VMXNET3_TCD_GEN_DWORD_SHIFT 3
230 #include "vmware_pack_begin.h"
231 struct Vmxnet3_TxCompDesc {
232 uint32 txdIdx:12; /* Index of the EOP TxDesc */
239 uint32 type:7; /* completion type */
240 uint32 gen:1; /* generation bit */
242 #include "vmware_pack_end.h"
246 #include "vmware_pack_begin.h"
247 struct Vmxnet3_RxDesc {
250 #ifdef __BIG_ENDIAN_BITFIELD
251 uint32 gen:1; /* Generation bit */
253 uint32 dtype:1; /* Descriptor type */
254 uint32 btype:1; /* Buffer Type */
258 uint32 btype:1; /* Buffer Type */
259 uint32 dtype:1; /* Descriptor type */
261 uint32 gen:1; /* Generation bit */
265 #include "vmware_pack_end.h"
268 /* values of RXD.BTYPE */
269 #define VMXNET3_RXD_BTYPE_HEAD 0 /* head only */
270 #define VMXNET3_RXD_BTYPE_BODY 1 /* body only */
272 /* fields in RxDesc we access w/o using bit fields */
273 #define VMXNET3_RXD_BTYPE_SHIFT 14
274 #define VMXNET3_RXD_GEN_SHIFT 31
277 #include "vmware_pack_begin.h"
278 struct Vmxnet3_RxCompDesc {
279 #ifdef __BIG_ENDIAN_BITFIELD
281 uint32 cnc:1; /* Checksum Not Calculated */
282 uint32 rssType:4; /* RSS hash type used */
283 uint32 rqID:10; /* rx queue/ring ID */
284 uint32 sop:1; /* Start of Packet */
285 uint32 eop:1; /* End of Packet */
287 uint32 rxdIdx:12; /* Index of the RxDesc */
289 uint32 rxdIdx:12; /* Index of the RxDesc */
291 uint32 eop:1; /* End of Packet */
292 uint32 sop:1; /* Start of Packet */
293 uint32 rqID:10; /* rx queue/ring ID */
294 uint32 rssType:4; /* RSS hash type used */
295 uint32 cnc:1; /* Checksum Not Calculated */
297 #endif /* __BIG_ENDIAN_BITFIELD */
299 __le32 rssHash; /* RSS hash value */
301 #ifdef __BIG_ENDIAN_BITFIELD
302 uint32 tci:16; /* Tag stripped */
303 uint32 ts:1; /* Tag is stripped */
304 uint32 err:1; /* Error */
305 uint32 len:14; /* data length */
307 uint32 len:14; /* data length */
308 uint32 err:1; /* Error */
309 uint32 ts:1; /* Tag is stripped */
310 uint32 tci:16; /* Tag stripped */
311 #endif /* __BIG_ENDIAN_BITFIELD */
314 #ifdef __BIG_ENDIAN_BITFIELD
315 uint32 gen:1; /* generation bit */
316 uint32 type:7; /* completion type */
317 uint32 fcs:1; /* Frame CRC correct */
318 uint32 frg:1; /* IP Fragment */
319 uint32 v4:1; /* IPv4 */
320 uint32 v6:1; /* IPv6 */
321 uint32 ipc:1; /* IP Checksum Correct */
322 uint32 tcp:1; /* TCP packet */
323 uint32 udp:1; /* UDP packet */
324 uint32 tuc:1; /* TCP/UDP Checksum Correct */
328 uint32 tuc:1; /* TCP/UDP Checksum Correct */
329 uint32 udp:1; /* UDP packet */
330 uint32 tcp:1; /* TCP packet */
331 uint32 ipc:1; /* IP Checksum Correct */
332 uint32 v6:1; /* IPv6 */
333 uint32 v4:1; /* IPv4 */
334 uint32 frg:1; /* IP Fragment */
335 uint32 fcs:1; /* Frame CRC correct */
336 uint32 type:7; /* completion type */
337 uint32 gen:1; /* generation bit */
338 #endif /* __BIG_ENDIAN_BITFIELD */
340 #include "vmware_pack_end.h"
344 #include "vmware_pack_begin.h"
345 struct Vmxnet3_RxCompDescExt {
347 uint8 segCnt; /* Number of aggregated packets */
348 uint8 dupAckCnt; /* Number of duplicate Acks */
349 __le16 tsDelta; /* TCP timestamp difference */
352 #include "vmware_pack_end.h"
353 Vmxnet3_RxCompDescExt;
355 /* fields in RxCompDesc we access via Vmxnet3_GenericDesc.dword[3] */
356 #define VMXNET3_RCD_TUC_SHIFT 16
357 #define VMXNET3_RCD_IPC_SHIFT 19
359 /* fields in RxCompDesc we access via Vmxnet3_GenericDesc.qword[1] */
360 #define VMXNET3_RCD_TYPE_SHIFT 56
361 #define VMXNET3_RCD_GEN_SHIFT 63
363 /* csum OK for TCP/UDP pkts over IP */
364 #define VMXNET3_RCD_CSUM_OK (1 << VMXNET3_RCD_TUC_SHIFT | 1 << VMXNET3_RCD_IPC_SHIFT)
366 /* value of RxCompDesc.rssType */
367 #define VMXNET3_RCD_RSS_TYPE_NONE 0
368 #define VMXNET3_RCD_RSS_TYPE_IPV4 1
369 #define VMXNET3_RCD_RSS_TYPE_TCPIPV4 2
370 #define VMXNET3_RCD_RSS_TYPE_IPV6 3
371 #define VMXNET3_RCD_RSS_TYPE_TCPIPV6 4
373 /* a union for accessing all cmd/completion descriptors */
374 typedef union Vmxnet3_GenericDesc {
380 Vmxnet3_TxCompDesc tcd;
381 Vmxnet3_RxCompDesc rcd;
382 Vmxnet3_RxCompDescExt rcdExt;
383 } Vmxnet3_GenericDesc;
385 #define VMXNET3_INIT_GEN 1
387 /* Max size of a single tx buffer */
388 #define VMXNET3_MAX_TX_BUF_SIZE (1 << 14)
390 /* # of tx desc needed for a tx buffer size */
391 #define VMXNET3_TXD_NEEDED(size) (((size) + VMXNET3_MAX_TX_BUF_SIZE - 1) / VMXNET3_MAX_TX_BUF_SIZE)
393 /* max # of tx descs for a non-tso pkt */
394 #define VMXNET3_MAX_TXD_PER_PKT 16
396 /* Max size of a single rx buffer */
397 #define VMXNET3_MAX_RX_BUF_SIZE ((1 << 14) - 1)
398 /* Minimum size of a type 0 buffer */
399 #define VMXNET3_MIN_T0_BUF_SIZE 128
400 #define VMXNET3_MAX_CSUM_OFFSET 1024
402 /* Ring base address alignment */
403 #define VMXNET3_RING_BA_ALIGN 512
404 #define VMXNET3_RING_BA_MASK (VMXNET3_RING_BA_ALIGN - 1)
406 /* Ring size must be a multiple of 32 */
407 #define VMXNET3_RING_SIZE_ALIGN 32
408 #define VMXNET3_RING_SIZE_MASK (VMXNET3_RING_SIZE_ALIGN - 1)
410 /* Tx Data Ring buffer size must be a multiple of 64 */
411 #define VMXNET3_TXDATA_DESC_SIZE_ALIGN 64
412 #define VMXNET3_TXDATA_DESC_SIZE_MASK (VMXNET3_TXDATA_DESC_SIZE_ALIGN - 1)
414 /* Rx Data Ring buffer size must be a multiple of 64 */
415 #define VMXNET3_RXDATA_DESC_SIZE_ALIGN 64
416 #define VMXNET3_RXDATA_DESC_SIZE_MASK (VMXNET3_RXDATA_DESC_SIZE_ALIGN - 1)
419 #define VMXNET3_TX_RING_MAX_SIZE 4096
420 #define VMXNET3_TC_RING_MAX_SIZE 4096
421 #define VMXNET3_RX_RING_MAX_SIZE 4096
422 #define VMXNET3_RC_RING_MAX_SIZE 8192
424 #define VMXNET3_TXDATA_DESC_MIN_SIZE 128
425 #define VMXNET3_TXDATA_DESC_MAX_SIZE 2048
427 #define VMXNET3_RXDATA_DESC_MAX_SIZE 2048
429 /* a list of reasons for queue stop */
431 #define VMXNET3_ERR_NOEOP 0x80000000 /* cannot find the EOP desc of a pkt */
432 #define VMXNET3_ERR_TXD_REUSE 0x80000001 /* reuse a TxDesc before tx completion */
433 #define VMXNET3_ERR_BIG_PKT 0x80000002 /* too many TxDesc for a pkt */
434 #define VMXNET3_ERR_DESC_NOT_SPT 0x80000003 /* descriptor type not supported */
435 #define VMXNET3_ERR_SMALL_BUF 0x80000004 /* type 0 buffer too small */
436 #define VMXNET3_ERR_STRESS 0x80000005 /* stress option firing in vmkernel */
437 #define VMXNET3_ERR_SWITCH 0x80000006 /* mode switch failure */
438 #define VMXNET3_ERR_TXD_INVALID 0x80000007 /* invalid TxDesc */
440 /* completion descriptor types */
441 #define VMXNET3_CDTYPE_TXCOMP 0 /* Tx Completion Descriptor */
442 #define VMXNET3_CDTYPE_RXCOMP 3 /* Rx Completion Descriptor */
443 #define VMXNET3_CDTYPE_RXCOMP_LRO 4 /* Rx Completion Descriptor for LRO */
445 #define VMXNET3_GOS_BITS_UNK 0 /* unknown */
446 #define VMXNET3_GOS_BITS_32 1
447 #define VMXNET3_GOS_BITS_64 2
449 #define VMXNET3_GOS_TYPE_UNK 0 /* unknown */
450 #define VMXNET3_GOS_TYPE_LINUX 1
451 #define VMXNET3_GOS_TYPE_WIN 2
452 #define VMXNET3_GOS_TYPE_SOLARIS 3
453 #define VMXNET3_GOS_TYPE_FREEBSD 4
454 #define VMXNET3_GOS_TYPE_PXE 5
456 /* All structures in DriverShared are padded to multiples of 8 bytes */
459 #include "vmware_pack_begin.h"
460 struct Vmxnet3_GOSInfo {
461 #ifdef __BIG_ENDIAN_BITFIELD
462 uint32 gosMisc: 10; /* other info about gos */
463 uint32 gosVer: 16; /* gos version */
464 uint32 gosType: 4; /* which guest */
465 uint32 gosBits: 2; /* 32-bit or 64-bit? */
467 uint32 gosBits: 2; /* 32-bit or 64-bit? */
468 uint32 gosType: 4; /* which guest */
469 uint32 gosVer: 16; /* gos version */
470 uint32 gosMisc: 10; /* other info about gos */
471 #endif /* __BIG_ENDIAN_BITFIELD */
473 #include "vmware_pack_end.h"
477 #include "vmware_pack_begin.h"
478 struct Vmxnet3_DriverInfo {
479 __le32 version; /* driver version */
481 __le32 vmxnet3RevSpt; /* vmxnet3 revision supported */
482 __le32 uptVerSpt; /* upt version supported */
484 #include "vmware_pack_end.h"
487 #define VMXNET3_REV1_MAGIC 0xbabefee1
490 * QueueDescPA must be 128 bytes aligned. It points to an array of
491 * Vmxnet3_TxQueueDesc followed by an array of Vmxnet3_RxQueueDesc.
492 * The number of Vmxnet3_TxQueueDesc/Vmxnet3_RxQueueDesc are specified by
493 * Vmxnet3_MiscConf.numTxQueues/numRxQueues, respectively.
495 #define VMXNET3_QUEUE_DESC_ALIGN 128
498 #include "vmware_pack_begin.h"
499 struct Vmxnet3_MiscConf {
500 Vmxnet3_DriverInfo driverInfo;
502 __le64 ddPA; /* driver data PA */
503 __le64 queueDescPA; /* queue descriptor table PA */
504 __le32 ddLen; /* driver data len */
505 __le32 queueDescLen; /* queue descriptor table len, in bytes */
512 #include "vmware_pack_end.h"
516 #include "vmware_pack_begin.h"
517 struct Vmxnet3_TxQueueConf {
519 __le64 dataRingBasePA;
520 __le64 compRingBasePA;
521 __le64 ddPA; /* driver data */
523 __le32 txRingSize; /* # of tx desc */
524 __le32 dataRingSize; /* # of data desc */
525 __le32 compRingSize; /* # of comp desc */
526 __le32 ddLen; /* size of driver data */
529 __le16 txDataRingDescSize;
532 #include "vmware_pack_end.h"
536 #include "vmware_pack_begin.h"
537 struct Vmxnet3_RxQueueConf {
538 __le64 rxRingBasePA[2];
539 __le64 compRingBasePA;
540 __le64 ddPA; /* driver data */
541 __le64 rxDataRingBasePA;
542 __le32 rxRingSize[2]; /* # of rx desc */
543 __le32 compRingSize; /* # of rx comp desc */
544 __le32 ddLen; /* size of driver data */
547 __le16 rxDataRingDescSize; /* size of rx data ring buffer */
550 #include "vmware_pack_end.h"
553 enum vmxnet3_intr_mask_mode {
554 VMXNET3_IMM_AUTO = 0,
555 VMXNET3_IMM_ACTIVE = 1,
559 enum vmxnet3_intr_type {
566 #define VMXNET3_MAX_TX_QUEUES 8
567 #define VMXNET3_MAX_RX_QUEUES 16
568 /* addition 1 for events */
569 #define VMXNET3_MAX_INTRS 25
571 /* value of intrCtrl */
572 #define VMXNET3_IC_DISABLE_ALL 0x1 /* bit 0 */
575 #include "vmware_pack_begin.h"
576 struct Vmxnet3_IntrConf {
578 uint8 numIntrs; /* # of interrupts */
580 uint8 modLevels[VMXNET3_MAX_INTRS]; /* moderation level for each intr */
584 #include "vmware_pack_end.h"
587 /* one bit per VLAN ID, the size is in the units of uint32 */
588 #define VMXNET3_VFT_SIZE (4096 / (sizeof(uint32) * 8))
591 #include "vmware_pack_begin.h"
592 struct Vmxnet3_QueueStatus {
597 #include "vmware_pack_end.h"
601 #include "vmware_pack_begin.h"
602 struct Vmxnet3_TxQueueCtrl {
603 __le32 txNumDeferred;
607 #include "vmware_pack_end.h"
611 #include "vmware_pack_begin.h"
612 struct Vmxnet3_RxQueueCtrl {
617 #include "vmware_pack_end.h"
620 #define VMXNET3_RXM_UCAST 0x01 /* unicast only */
621 #define VMXNET3_RXM_MCAST 0x02 /* multicast passing the filters */
622 #define VMXNET3_RXM_BCAST 0x04 /* broadcast only */
623 #define VMXNET3_RXM_ALL_MULTI 0x08 /* all multicast */
624 #define VMXNET3_RXM_PROMISC 0x10 /* promiscuous */
627 #include "vmware_pack_begin.h"
628 struct Vmxnet3_RxFilterConf {
629 __le32 rxMode; /* VMXNET3_RXM_xxx */
630 __le16 mfTableLen; /* size of the multicast filter table */
632 __le64 mfTablePA; /* PA of the multicast filters table */
633 __le32 vfTable[VMXNET3_VFT_SIZE]; /* vlan filter */
635 #include "vmware_pack_end.h"
636 Vmxnet3_RxFilterConf;
638 #define VMXNET3_PM_MAX_FILTERS 6
639 #define VMXNET3_PM_MAX_PATTERN_SIZE 128
640 #define VMXNET3_PM_MAX_MASK_SIZE (VMXNET3_PM_MAX_PATTERN_SIZE / 8)
642 #define VMXNET3_PM_WAKEUP_MAGIC 0x01 /* wake up on magic pkts */
643 #define VMXNET3_PM_WAKEUP_FILTER 0x02 /* wake up on pkts matching filters */
646 #include "vmware_pack_begin.h"
647 struct Vmxnet3_PM_PktFilter {
650 uint8 mask[VMXNET3_PM_MAX_MASK_SIZE];
651 uint8 pattern[VMXNET3_PM_MAX_PATTERN_SIZE];
654 #include "vmware_pack_end.h"
655 Vmxnet3_PM_PktFilter;
658 #include "vmware_pack_begin.h"
659 struct Vmxnet3_PMConf {
660 __le16 wakeUpEvents; /* VMXNET3_PM_WAKEUP_xxx */
663 Vmxnet3_PM_PktFilter filters[VMXNET3_PM_MAX_FILTERS];
665 #include "vmware_pack_end.h"
669 #include "vmware_pack_begin.h"
670 struct Vmxnet3_VariableLenConfDesc {
675 #include "vmware_pack_end.h"
676 Vmxnet3_VariableLenConfDesc;
679 #include "vmware_pack_begin.h"
680 struct Vmxnet3_DSDevRead {
681 /* read-only region for device, read by dev in response to a SET cmd */
682 Vmxnet3_MiscConf misc;
683 Vmxnet3_IntrConf intrConf;
684 Vmxnet3_RxFilterConf rxFilterConf;
685 Vmxnet3_VariableLenConfDesc rssConfDesc;
686 Vmxnet3_VariableLenConfDesc pmConfDesc;
687 Vmxnet3_VariableLenConfDesc pluginConfDesc;
689 #include "vmware_pack_end.h"
693 #include "vmware_pack_begin.h"
694 struct Vmxnet3_TxQueueDesc {
695 Vmxnet3_TxQueueCtrl ctrl;
696 Vmxnet3_TxQueueConf conf;
697 /* Driver read after a GET command */
698 Vmxnet3_QueueStatus status;
700 uint8 _pad[88]; /* 128 aligned */
702 #include "vmware_pack_end.h"
706 #include "vmware_pack_begin.h"
707 struct Vmxnet3_RxQueueDesc {
708 Vmxnet3_RxQueueCtrl ctrl;
709 Vmxnet3_RxQueueConf conf;
710 /* Driver read after a GET command */
711 Vmxnet3_QueueStatus status;
713 uint8 _pad[88]; /* 128 aligned */
715 #include "vmware_pack_end.h"
719 #include "vmware_pack_begin.h"
720 struct Vmxnet3_SetPolling {
723 #include "vmware_pack_end.h"
727 #include "vmware_pack_begin.h"
728 struct Vmxnet3_MemoryRegion {
731 __le16 txQueueBits; /* bit n corresponding to tx queue n */
732 __le16 rxQueueBits; /* bit n corresponding to rx queue n */
734 #include "vmware_pack_end.h"
735 Vmxnet3_MemoryRegion;
737 #define MAX_MEMORY_REGION_PER_QUEUE 16
738 #define MAX_MEMORY_REGION_PER_DEVICE 256
741 #include "vmware_pack_begin.h"
742 struct Vmxnet3_MemRegs {
745 Vmxnet3_MemoryRegion memRegs[1];
747 #include "vmware_pack_end.h"
751 * If the command data <= 16 bytes, use the shared memory direcly.
752 * Otherwise, use the variable length configuration descriptor.
755 #include "vmware_pack_begin.h"
756 union Vmxnet3_CmdInfo {
757 Vmxnet3_VariableLenConfDesc varConf;
758 Vmxnet3_SetPolling setPolling;
761 #include "vmware_pack_end.h"
765 #include "vmware_pack_begin.h"
766 struct Vmxnet3_DriverShared {
768 __le32 pad; /* make devRead start at 64-bit boundaries */
769 Vmxnet3_DSDevRead devRead;
775 Vmxnet3_CmdInfo cmdInfo; /* only valid in the context of executing the
780 #include "vmware_pack_end.h"
781 Vmxnet3_DriverShared;
783 #define VMXNET3_ECR_RQERR (1 << 0)
784 #define VMXNET3_ECR_TQERR (1 << 1)
785 #define VMXNET3_ECR_LINK (1 << 2)
786 #define VMXNET3_ECR_DIC (1 << 3)
787 #define VMXNET3_ECR_DEBUG (1 << 4)
789 /* flip the gen bit of a ring */
790 #define VMXNET3_FLIP_RING_GEN(gen) ((gen) = (gen) ^ 0x1)
792 /* only use this if moving the idx won't affect the gen bit */
793 #define VMXNET3_INC_RING_IDX_ONLY(idx, ring_size) \
796 if (UNLIKELY((idx) == (ring_size))) {\
801 #define VMXNET3_SET_VFTABLE_ENTRY(vfTable, vid) \
802 vfTable[vid >> 5] |= (1 << (vid & 31))
803 #define VMXNET3_CLEAR_VFTABLE_ENTRY(vfTable, vid) \
804 vfTable[vid >> 5] &= ~(1 << (vid & 31))
806 #define VMXNET3_VFTABLE_ENTRY_IS_SET(vfTable, vid) \
807 ((vfTable[vid >> 5] & (1 << (vid & 31))) != 0)
809 #define VMXNET3_MAX_MTU 9000
810 #define VMXNET3_MIN_MTU 60
812 #define VMXNET3_LINK_UP (10000 << 16 | 1) // 10 Gbps, up
813 #define VMXNET3_LINK_DOWN 0
815 #define VMXWIFI_DRIVER_SHARED_LEN 8192
817 #define VMXNET3_DID_PASSTHRU 0xFFFF
819 #endif /* _VMXNET3_DEFS_H_ */