1 /*********************************************************
2 * Copyright (C) 2007 VMware, Inc. All rights reserved.
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 *********************************************************/
31 * Definitions shared by device emulation and guest drivers for
35 #ifndef _VMXNET3_DEFS_H_
36 #define _VMXNET3_DEFS_H_
38 #include "vmxnet3_osdep.h"
39 #include "upt1_defs.h"
41 /* all registers are 32 bit wide */
43 #define VMXNET3_REG_VRRS 0x0 /* Vmxnet3 Revision Report Selection */
44 #define VMXNET3_REG_UVRS 0x8 /* UPT Version Report Selection */
45 #define VMXNET3_REG_DSAL 0x10 /* Driver Shared Address Low */
46 #define VMXNET3_REG_DSAH 0x18 /* Driver Shared Address High */
47 #define VMXNET3_REG_CMD 0x20 /* Command */
48 #define VMXNET3_REG_MACL 0x28 /* MAC Address Low */
49 #define VMXNET3_REG_MACH 0x30 /* MAC Address High */
50 #define VMXNET3_REG_ICR 0x38 /* Interrupt Cause Register */
51 #define VMXNET3_REG_ECR 0x40 /* Event Cause Register */
53 #define VMXNET3_REG_WSAL 0xF00 /* Wireless Shared Address Lo */
54 #define VMXNET3_REG_WSAH 0xF08 /* Wireless Shared Address Hi */
55 #define VMXNET3_REG_WCMD 0xF18 /* Wireless Command */
58 #define VMXNET3_REG_IMR 0x0 /* Interrupt Mask Register */
59 #define VMXNET3_REG_TXPROD 0x600 /* Tx Producer Index */
60 #define VMXNET3_REG_RXPROD 0x800 /* Rx Producer Index for ring 1 */
61 #define VMXNET3_REG_RXPROD2 0xA00 /* Rx Producer Index for ring 2 */
63 #define VMXNET3_PT_REG_SIZE 4096 /* BAR 0 */
64 #define VMXNET3_VD_REG_SIZE 4096 /* BAR 1 */
67 * The two Vmxnet3 MMIO Register PCI BARs (BAR 0 at offset 10h and BAR 1 at
68 * offset 14h) as well as the MSI-X BAR are combined into one PhysMem region:
69 * <-VMXNET3_PT_REG_SIZE-><-VMXNET3_VD_REG_SIZE-><-VMXNET3_MSIX_BAR_SIZE-->
70 * -------------------------------------------------------------------------
71 * |Pass Thru Registers | Virtual Dev Registers | MSI-X Vector/PBA Table |
72 * -------------------------------------------------------------------------
73 * VMXNET3_MSIX_BAR_SIZE is defined in "vmxnet3Int.h"
75 #define VMXNET3_PHYSMEM_PAGES 4
77 #define VMXNET3_REG_ALIGN 8 /* All registers are 8-byte aligned. */
78 #define VMXNET3_REG_ALIGN_MASK 0x7
80 /* I/O Mapped access to registers */
81 #define VMXNET3_IO_TYPE_PT 0
82 #define VMXNET3_IO_TYPE_VD 1
83 #define VMXNET3_IO_ADDR(type, reg) (((type) << 24) | ((reg) & 0xFFFFFF))
84 #define VMXNET3_IO_TYPE(addr) ((addr) >> 24)
85 #define VMXNET3_IO_REG(addr) ((addr) & 0xFFFFFF)
98 VMXNET3_CMD_FIRST_SET = 0xCAFE0000,
99 VMXNET3_CMD_ACTIVATE_DEV = VMXNET3_CMD_FIRST_SET,
100 VMXNET3_CMD_QUIESCE_DEV,
101 VMXNET3_CMD_RESET_DEV,
102 VMXNET3_CMD_UPDATE_RX_MODE,
103 VMXNET3_CMD_UPDATE_MAC_FILTERS,
104 VMXNET3_CMD_UPDATE_VLAN_FILTERS,
105 VMXNET3_CMD_UPDATE_RSSIDT,
106 VMXNET3_CMD_UPDATE_IML,
107 VMXNET3_CMD_UPDATE_PMCFG,
108 VMXNET3_CMD_UPDATE_FEATURE,
109 VMXNET3_CMD_STOP_EMULATION,
110 VMXNET3_CMD_LOAD_PLUGIN,
111 VMXNET3_CMD_ACTIVATE_VF,
112 VMXNET3_CMD_RESERVED3,
113 VMXNET3_CMD_RESERVED4,
115 VMXNET3_CMD_FIRST_GET = 0xF00D0000,
116 VMXNET3_CMD_GET_QUEUE_STATUS = VMXNET3_CMD_FIRST_GET,
117 VMXNET3_CMD_GET_STATS,
118 VMXNET3_CMD_GET_LINK,
119 VMXNET3_CMD_GET_PERM_MAC_LO,
120 VMXNET3_CMD_GET_PERM_MAC_HI,
121 VMXNET3_CMD_GET_DID_LO,
122 VMXNET3_CMD_GET_DID_HI,
123 VMXNET3_CMD_GET_DEV_EXTRA_INFO,
124 VMXNET3_CMD_GET_CONF_INTR,
125 VMXNET3_CMD_GET_ADAPTIVE_RING_INFO,
126 VMXNET3_CMD_GET_TXDATA_DESC_SIZE,
127 VMXNET3_CMD_RESERVED5,
130 /* Adaptive Ring Info Flags */
131 #define VMXNET3_DISABLE_ADAPTIVE_RING 1
134 * Little Endian layout of bitfields -
135 * Byte 0 : 7.....len.....0
136 * Byte 1 : rsvd gen 13.len.8
137 * Byte 2 : 5.msscof.0 ext1 dtype
138 * Byte 3 : 13...msscof...6
140 * Big Endian layout of bitfields -
141 * Byte 0: 13...msscof...6
142 * Byte 1 : 5.msscof.0 ext1 dtype
143 * Byte 2 : rsvd gen 13.len.8
144 * Byte 3 : 7.....len.....0
146 * Thus, le32_to_cpu on the dword will allow the big endian driver to read
147 * the bit fields correctly. And cpu_to_le32 will convert bitfields
148 * bit fields written by big endian driver to format required by device.
152 #include "vmware_pack_begin.h"
153 struct Vmxnet3_TxDesc {
156 #ifdef __BIG_ENDIAN_BITFIELD
157 uint32 msscof:14; /* MSS, checksum offset, flags */
159 uint32 dtype:1; /* descriptor type */
161 uint32 gen:1; /* generation bit */
165 uint32 gen:1; /* generation bit */
167 uint32 dtype:1; /* descriptor type */
169 uint32 msscof:14; /* MSS, checksum offset, flags */
170 #endif /* __BIG_ENDIAN_BITFIELD */
172 #ifdef __BIG_ENDIAN_BITFIELD
173 uint32 tci:16; /* Tag to Insert */
174 uint32 ti:1; /* VLAN Tag Insertion */
176 uint32 cq:1; /* completion request */
177 uint32 eop:1; /* End Of Packet */
178 uint32 om:2; /* offload mode */
179 uint32 hlen:10; /* header len */
181 uint32 hlen:10; /* header len */
182 uint32 om:2; /* offload mode */
183 uint32 eop:1; /* End Of Packet */
184 uint32 cq:1; /* completion request */
186 uint32 ti:1; /* VLAN Tag Insertion */
187 uint32 tci:16; /* Tag to Insert */
188 #endif /* __BIG_ENDIAN_BITFIELD */
190 #include "vmware_pack_end.h"
193 /* TxDesc.OM values */
194 #define VMXNET3_OM_NONE 0
195 #define VMXNET3_OM_CSUM 2
196 #define VMXNET3_OM_TSO 3
198 /* fields in TxDesc we access w/o using bit fields */
199 #define VMXNET3_TXD_EOP_SHIFT 12
200 #define VMXNET3_TXD_CQ_SHIFT 13
201 #define VMXNET3_TXD_GEN_SHIFT 14
202 #define VMXNET3_TXD_EOP_DWORD_SHIFT 3
203 #define VMXNET3_TXD_GEN_DWORD_SHIFT 2
205 #define VMXNET3_TXD_CQ (1 << VMXNET3_TXD_CQ_SHIFT)
206 #define VMXNET3_TXD_EOP (1 << VMXNET3_TXD_EOP_SHIFT)
207 #define VMXNET3_TXD_GEN (1 << VMXNET3_TXD_GEN_SHIFT)
209 #define VMXNET3_TXD_GEN_SIZE 1
210 #define VMXNET3_TXD_EOP_SIZE 1
212 #define VMXNET3_HDR_COPY_SIZE 128
215 #include "vmware_pack_begin.h"
216 struct Vmxnet3_TxDataDesc {
217 uint8 data[VMXNET3_HDR_COPY_SIZE];
219 #include "vmware_pack_end.h"
222 #define VMXNET3_TCD_GEN_SHIFT 31
223 #define VMXNET3_TCD_GEN_SIZE 1
224 #define VMXNET3_TCD_TXIDX_SHIFT 0
225 #define VMXNET3_TCD_TXIDX_SIZE 12
226 #define VMXNET3_TCD_GEN_DWORD_SHIFT 3
229 #include "vmware_pack_begin.h"
230 struct Vmxnet3_TxCompDesc {
231 uint32 txdIdx:12; /* Index of the EOP TxDesc */
238 uint32 type:7; /* completion type */
239 uint32 gen:1; /* generation bit */
241 #include "vmware_pack_end.h"
245 #include "vmware_pack_begin.h"
246 struct Vmxnet3_RxDesc {
249 #ifdef __BIG_ENDIAN_BITFIELD
250 uint32 gen:1; /* Generation bit */
252 uint32 dtype:1; /* Descriptor type */
253 uint32 btype:1; /* Buffer Type */
257 uint32 btype:1; /* Buffer Type */
258 uint32 dtype:1; /* Descriptor type */
260 uint32 gen:1; /* Generation bit */
264 #include "vmware_pack_end.h"
267 /* values of RXD.BTYPE */
268 #define VMXNET3_RXD_BTYPE_HEAD 0 /* head only */
269 #define VMXNET3_RXD_BTYPE_BODY 1 /* body only */
271 /* fields in RxDesc we access w/o using bit fields */
272 #define VMXNET3_RXD_BTYPE_SHIFT 14
273 #define VMXNET3_RXD_GEN_SHIFT 31
276 #include "vmware_pack_begin.h"
277 struct Vmxnet3_RxCompDesc {
278 #ifdef __BIG_ENDIAN_BITFIELD
280 uint32 cnc:1; /* Checksum Not Calculated */
281 uint32 rssType:4; /* RSS hash type used */
282 uint32 rqID:10; /* rx queue/ring ID */
283 uint32 sop:1; /* Start of Packet */
284 uint32 eop:1; /* End of Packet */
286 uint32 rxdIdx:12; /* Index of the RxDesc */
288 uint32 rxdIdx:12; /* Index of the RxDesc */
290 uint32 eop:1; /* End of Packet */
291 uint32 sop:1; /* Start of Packet */
292 uint32 rqID:10; /* rx queue/ring ID */
293 uint32 rssType:4; /* RSS hash type used */
294 uint32 cnc:1; /* Checksum Not Calculated */
296 #endif /* __BIG_ENDIAN_BITFIELD */
298 __le32 rssHash; /* RSS hash value */
300 #ifdef __BIG_ENDIAN_BITFIELD
301 uint32 tci:16; /* Tag stripped */
302 uint32 ts:1; /* Tag is stripped */
303 uint32 err:1; /* Error */
304 uint32 len:14; /* data length */
306 uint32 len:14; /* data length */
307 uint32 err:1; /* Error */
308 uint32 ts:1; /* Tag is stripped */
309 uint32 tci:16; /* Tag stripped */
310 #endif /* __BIG_ENDIAN_BITFIELD */
313 #ifdef __BIG_ENDIAN_BITFIELD
314 uint32 gen:1; /* generation bit */
315 uint32 type:7; /* completion type */
316 uint32 fcs:1; /* Frame CRC correct */
317 uint32 frg:1; /* IP Fragment */
318 uint32 v4:1; /* IPv4 */
319 uint32 v6:1; /* IPv6 */
320 uint32 ipc:1; /* IP Checksum Correct */
321 uint32 tcp:1; /* TCP packet */
322 uint32 udp:1; /* UDP packet */
323 uint32 tuc:1; /* TCP/UDP Checksum Correct */
327 uint32 tuc:1; /* TCP/UDP Checksum Correct */
328 uint32 udp:1; /* UDP packet */
329 uint32 tcp:1; /* TCP packet */
330 uint32 ipc:1; /* IP Checksum Correct */
331 uint32 v6:1; /* IPv6 */
332 uint32 v4:1; /* IPv4 */
333 uint32 frg:1; /* IP Fragment */
334 uint32 fcs:1; /* Frame CRC correct */
335 uint32 type:7; /* completion type */
336 uint32 gen:1; /* generation bit */
337 #endif /* __BIG_ENDIAN_BITFIELD */
339 #include "vmware_pack_end.h"
343 #include "vmware_pack_begin.h"
344 struct Vmxnet3_RxCompDescExt {
346 uint8 segCnt; /* Number of aggregated packets */
347 uint8 dupAckCnt; /* Number of duplicate Acks */
348 __le16 tsDelta; /* TCP timestamp difference */
351 #include "vmware_pack_end.h"
352 Vmxnet3_RxCompDescExt;
354 /* fields in RxCompDesc we access via Vmxnet3_GenericDesc.dword[3] */
355 #define VMXNET3_RCD_TUC_SHIFT 16
356 #define VMXNET3_RCD_IPC_SHIFT 19
358 /* fields in RxCompDesc we access via Vmxnet3_GenericDesc.qword[1] */
359 #define VMXNET3_RCD_TYPE_SHIFT 56
360 #define VMXNET3_RCD_GEN_SHIFT 63
362 /* csum OK for TCP/UDP pkts over IP */
363 #define VMXNET3_RCD_CSUM_OK (1 << VMXNET3_RCD_TUC_SHIFT | 1 << VMXNET3_RCD_IPC_SHIFT)
365 /* value of RxCompDesc.rssType */
366 #define VMXNET3_RCD_RSS_TYPE_NONE 0
367 #define VMXNET3_RCD_RSS_TYPE_IPV4 1
368 #define VMXNET3_RCD_RSS_TYPE_TCPIPV4 2
369 #define VMXNET3_RCD_RSS_TYPE_IPV6 3
370 #define VMXNET3_RCD_RSS_TYPE_TCPIPV6 4
372 /* a union for accessing all cmd/completion descriptors */
373 typedef union Vmxnet3_GenericDesc {
379 Vmxnet3_TxCompDesc tcd;
380 Vmxnet3_RxCompDesc rcd;
381 Vmxnet3_RxCompDescExt rcdExt;
382 } Vmxnet3_GenericDesc;
384 #define VMXNET3_INIT_GEN 1
386 /* Max size of a single tx buffer */
387 #define VMXNET3_MAX_TX_BUF_SIZE (1 << 14)
389 /* # of tx desc needed for a tx buffer size */
390 #define VMXNET3_TXD_NEEDED(size) (((size) + VMXNET3_MAX_TX_BUF_SIZE - 1) / VMXNET3_MAX_TX_BUF_SIZE)
392 /* max # of tx descs for a non-tso pkt */
393 #define VMXNET3_MAX_TXD_PER_PKT 16
395 /* Max size of a single rx buffer */
396 #define VMXNET3_MAX_RX_BUF_SIZE ((1 << 14) - 1)
397 /* Minimum size of a type 0 buffer */
398 #define VMXNET3_MIN_T0_BUF_SIZE 128
399 #define VMXNET3_MAX_CSUM_OFFSET 1024
401 /* Ring base address alignment */
402 #define VMXNET3_RING_BA_ALIGN 512
403 #define VMXNET3_RING_BA_MASK (VMXNET3_RING_BA_ALIGN - 1)
405 /* Ring size must be a multiple of 32 */
406 #define VMXNET3_RING_SIZE_ALIGN 32
407 #define VMXNET3_RING_SIZE_MASK (VMXNET3_RING_SIZE_ALIGN - 1)
409 /* Tx Data Ring buffer size must be a multiple of 64 */
410 #define VMXNET3_TXDATA_DESC_SIZE_ALIGN 64
411 #define VMXNET3_TXDATA_DESC_SIZE_MASK (VMXNET3_TXDATA_DESC_SIZE_ALIGN - 1)
413 /* Rx Data Ring buffer size must be a multiple of 64 */
414 #define VMXNET3_RXDATA_DESC_SIZE_ALIGN 64
415 #define VMXNET3_RXDATA_DESC_SIZE_MASK (VMXNET3_RXDATA_DESC_SIZE_ALIGN - 1)
418 #define VMXNET3_TX_RING_MAX_SIZE 4096
419 #define VMXNET3_TC_RING_MAX_SIZE 4096
420 #define VMXNET3_RX_RING_MAX_SIZE 4096
421 #define VMXNET3_RC_RING_MAX_SIZE 8192
423 #define VMXNET3_TXDATA_DESC_MIN_SIZE 128
424 #define VMXNET3_TXDATA_DESC_MAX_SIZE 2048
426 #define VMXNET3_RXDATA_DESC_MAX_SIZE 2048
428 /* a list of reasons for queue stop */
430 #define VMXNET3_ERR_NOEOP 0x80000000 /* cannot find the EOP desc of a pkt */
431 #define VMXNET3_ERR_TXD_REUSE 0x80000001 /* reuse a TxDesc before tx completion */
432 #define VMXNET3_ERR_BIG_PKT 0x80000002 /* too many TxDesc for a pkt */
433 #define VMXNET3_ERR_DESC_NOT_SPT 0x80000003 /* descriptor type not supported */
434 #define VMXNET3_ERR_SMALL_BUF 0x80000004 /* type 0 buffer too small */
435 #define VMXNET3_ERR_STRESS 0x80000005 /* stress option firing in vmkernel */
436 #define VMXNET3_ERR_SWITCH 0x80000006 /* mode switch failure */
437 #define VMXNET3_ERR_TXD_INVALID 0x80000007 /* invalid TxDesc */
439 /* completion descriptor types */
440 #define VMXNET3_CDTYPE_TXCOMP 0 /* Tx Completion Descriptor */
441 #define VMXNET3_CDTYPE_RXCOMP 3 /* Rx Completion Descriptor */
442 #define VMXNET3_CDTYPE_RXCOMP_LRO 4 /* Rx Completion Descriptor for LRO */
444 #define VMXNET3_GOS_BITS_UNK 0 /* unknown */
445 #define VMXNET3_GOS_BITS_32 1
446 #define VMXNET3_GOS_BITS_64 2
448 #define VMXNET3_GOS_TYPE_UNK 0 /* unknown */
449 #define VMXNET3_GOS_TYPE_LINUX 1
450 #define VMXNET3_GOS_TYPE_WIN 2
451 #define VMXNET3_GOS_TYPE_SOLARIS 3
452 #define VMXNET3_GOS_TYPE_FREEBSD 4
453 #define VMXNET3_GOS_TYPE_PXE 5
455 /* All structures in DriverShared are padded to multiples of 8 bytes */
458 #include "vmware_pack_begin.h"
459 struct Vmxnet3_GOSInfo {
460 #ifdef __BIG_ENDIAN_BITFIELD
461 uint32 gosMisc: 10; /* other info about gos */
462 uint32 gosVer: 16; /* gos version */
463 uint32 gosType: 4; /* which guest */
464 uint32 gosBits: 2; /* 32-bit or 64-bit? */
466 uint32 gosBits: 2; /* 32-bit or 64-bit? */
467 uint32 gosType: 4; /* which guest */
468 uint32 gosVer: 16; /* gos version */
469 uint32 gosMisc: 10; /* other info about gos */
470 #endif /* __BIG_ENDIAN_BITFIELD */
472 #include "vmware_pack_end.h"
476 #include "vmware_pack_begin.h"
477 struct Vmxnet3_DriverInfo {
478 __le32 version; /* driver version */
480 __le32 vmxnet3RevSpt; /* vmxnet3 revision supported */
481 __le32 uptVerSpt; /* upt version supported */
483 #include "vmware_pack_end.h"
486 #define VMXNET3_REV1_MAGIC 0xbabefee1
489 * QueueDescPA must be 128 bytes aligned. It points to an array of
490 * Vmxnet3_TxQueueDesc followed by an array of Vmxnet3_RxQueueDesc.
491 * The number of Vmxnet3_TxQueueDesc/Vmxnet3_RxQueueDesc are specified by
492 * Vmxnet3_MiscConf.numTxQueues/numRxQueues, respectively.
494 #define VMXNET3_QUEUE_DESC_ALIGN 128
497 #include "vmware_pack_begin.h"
498 struct Vmxnet3_MiscConf {
499 Vmxnet3_DriverInfo driverInfo;
501 __le64 ddPA; /* driver data PA */
502 __le64 queueDescPA; /* queue descriptor table PA */
503 __le32 ddLen; /* driver data len */
504 __le32 queueDescLen; /* queue descriptor table len, in bytes */
511 #include "vmware_pack_end.h"
515 #include "vmware_pack_begin.h"
516 struct Vmxnet3_TxQueueConf {
518 __le64 dataRingBasePA;
519 __le64 compRingBasePA;
520 __le64 ddPA; /* driver data */
522 __le32 txRingSize; /* # of tx desc */
523 __le32 dataRingSize; /* # of data desc */
524 __le32 compRingSize; /* # of comp desc */
525 __le32 ddLen; /* size of driver data */
528 __le16 txDataRingDescSize;
531 #include "vmware_pack_end.h"
535 #include "vmware_pack_begin.h"
536 struct Vmxnet3_RxQueueConf {
537 __le64 rxRingBasePA[2];
538 __le64 compRingBasePA;
539 __le64 ddPA; /* driver data */
540 __le64 rxDataRingBasePA;
541 __le32 rxRingSize[2]; /* # of rx desc */
542 __le32 compRingSize; /* # of rx comp desc */
543 __le32 ddLen; /* size of driver data */
546 __le16 rxDataRingDescSize; /* size of rx data ring buffer */
549 #include "vmware_pack_end.h"
552 enum vmxnet3_intr_mask_mode {
553 VMXNET3_IMM_AUTO = 0,
554 VMXNET3_IMM_ACTIVE = 1,
558 enum vmxnet3_intr_type {
565 #define VMXNET3_MAX_TX_QUEUES 8
566 #define VMXNET3_MAX_RX_QUEUES 16
567 /* addition 1 for events */
568 #define VMXNET3_MAX_INTRS 25
570 /* value of intrCtrl */
571 #define VMXNET3_IC_DISABLE_ALL 0x1 /* bit 0 */
574 #include "vmware_pack_begin.h"
575 struct Vmxnet3_IntrConf {
577 uint8 numIntrs; /* # of interrupts */
579 uint8 modLevels[VMXNET3_MAX_INTRS]; /* moderation level for each intr */
583 #include "vmware_pack_end.h"
586 /* one bit per VLAN ID, the size is in the units of uint32 */
587 #define VMXNET3_VFT_SIZE (4096 / (sizeof(uint32) * 8))
590 #include "vmware_pack_begin.h"
591 struct Vmxnet3_QueueStatus {
596 #include "vmware_pack_end.h"
600 #include "vmware_pack_begin.h"
601 struct Vmxnet3_TxQueueCtrl {
602 __le32 txNumDeferred;
606 #include "vmware_pack_end.h"
610 #include "vmware_pack_begin.h"
611 struct Vmxnet3_RxQueueCtrl {
616 #include "vmware_pack_end.h"
619 #define VMXNET3_RXM_UCAST 0x01 /* unicast only */
620 #define VMXNET3_RXM_MCAST 0x02 /* multicast passing the filters */
621 #define VMXNET3_RXM_BCAST 0x04 /* broadcast only */
622 #define VMXNET3_RXM_ALL_MULTI 0x08 /* all multicast */
623 #define VMXNET3_RXM_PROMISC 0x10 /* promiscuous */
626 #include "vmware_pack_begin.h"
627 struct Vmxnet3_RxFilterConf {
628 __le32 rxMode; /* VMXNET3_RXM_xxx */
629 __le16 mfTableLen; /* size of the multicast filter table */
631 __le64 mfTablePA; /* PA of the multicast filters table */
632 __le32 vfTable[VMXNET3_VFT_SIZE]; /* vlan filter */
634 #include "vmware_pack_end.h"
635 Vmxnet3_RxFilterConf;
637 #define VMXNET3_PM_MAX_FILTERS 6
638 #define VMXNET3_PM_MAX_PATTERN_SIZE 128
639 #define VMXNET3_PM_MAX_MASK_SIZE (VMXNET3_PM_MAX_PATTERN_SIZE / 8)
641 #define VMXNET3_PM_WAKEUP_MAGIC 0x01 /* wake up on magic pkts */
642 #define VMXNET3_PM_WAKEUP_FILTER 0x02 /* wake up on pkts matching filters */
645 #include "vmware_pack_begin.h"
646 struct Vmxnet3_PM_PktFilter {
649 uint8 mask[VMXNET3_PM_MAX_MASK_SIZE];
650 uint8 pattern[VMXNET3_PM_MAX_PATTERN_SIZE];
653 #include "vmware_pack_end.h"
654 Vmxnet3_PM_PktFilter;
657 #include "vmware_pack_begin.h"
658 struct Vmxnet3_PMConf {
659 __le16 wakeUpEvents; /* VMXNET3_PM_WAKEUP_xxx */
662 Vmxnet3_PM_PktFilter filters[VMXNET3_PM_MAX_FILTERS];
664 #include "vmware_pack_end.h"
668 #include "vmware_pack_begin.h"
669 struct Vmxnet3_VariableLenConfDesc {
674 #include "vmware_pack_end.h"
675 Vmxnet3_VariableLenConfDesc;
678 #include "vmware_pack_begin.h"
679 struct Vmxnet3_DSDevRead {
680 /* read-only region for device, read by dev in response to a SET cmd */
681 Vmxnet3_MiscConf misc;
682 Vmxnet3_IntrConf intrConf;
683 Vmxnet3_RxFilterConf rxFilterConf;
684 Vmxnet3_VariableLenConfDesc rssConfDesc;
685 Vmxnet3_VariableLenConfDesc pmConfDesc;
686 Vmxnet3_VariableLenConfDesc pluginConfDesc;
688 #include "vmware_pack_end.h"
692 #include "vmware_pack_begin.h"
693 struct Vmxnet3_TxQueueDesc {
694 Vmxnet3_TxQueueCtrl ctrl;
695 Vmxnet3_TxQueueConf conf;
696 /* Driver read after a GET command */
697 Vmxnet3_QueueStatus status;
699 uint8 _pad[88]; /* 128 aligned */
701 #include "vmware_pack_end.h"
705 #include "vmware_pack_begin.h"
706 struct Vmxnet3_RxQueueDesc {
707 Vmxnet3_RxQueueCtrl ctrl;
708 Vmxnet3_RxQueueConf conf;
709 /* Driver read after a GET command */
710 Vmxnet3_QueueStatus status;
712 uint8 _pad[88]; /* 128 aligned */
714 #include "vmware_pack_end.h"
718 #include "vmware_pack_begin.h"
719 struct Vmxnet3_SetPolling {
722 #include "vmware_pack_end.h"
726 * If the command data <= 16 bytes, use the shared memory direcly.
727 * Otherwise, use the variable length configuration descriptor.
730 #include "vmware_pack_begin.h"
731 union Vmxnet3_CmdInfo {
732 Vmxnet3_VariableLenConfDesc varConf;
733 Vmxnet3_SetPolling setPolling;
736 #include "vmware_pack_end.h"
740 #include "vmware_pack_begin.h"
741 struct Vmxnet3_DriverShared {
743 __le32 pad; /* make devRead start at 64-bit boundaries */
744 Vmxnet3_DSDevRead devRead;
750 Vmxnet3_CmdInfo cmdInfo; /* only valid in the context of executing the
755 #include "vmware_pack_end.h"
756 Vmxnet3_DriverShared;
758 #define VMXNET3_ECR_RQERR (1 << 0)
759 #define VMXNET3_ECR_TQERR (1 << 1)
760 #define VMXNET3_ECR_LINK (1 << 2)
761 #define VMXNET3_ECR_DIC (1 << 3)
762 #define VMXNET3_ECR_DEBUG (1 << 4)
764 /* flip the gen bit of a ring */
765 #define VMXNET3_FLIP_RING_GEN(gen) ((gen) = (gen) ^ 0x1)
767 /* only use this if moving the idx won't affect the gen bit */
768 #define VMXNET3_INC_RING_IDX_ONLY(idx, ring_size) \
771 if (UNLIKELY((idx) == (ring_size))) {\
776 #define VMXNET3_SET_VFTABLE_ENTRY(vfTable, vid) \
777 vfTable[vid >> 5] |= (1 << (vid & 31))
778 #define VMXNET3_CLEAR_VFTABLE_ENTRY(vfTable, vid) \
779 vfTable[vid >> 5] &= ~(1 << (vid & 31))
781 #define VMXNET3_VFTABLE_ENTRY_IS_SET(vfTable, vid) \
782 ((vfTable[vid >> 5] & (1 << (vid & 31))) != 0)
784 #define VMXNET3_MAX_MTU 9000
785 #define VMXNET3_MIN_MTU 60
787 #define VMXNET3_LINK_UP (10000 << 16 | 1) // 10 Gbps, up
788 #define VMXNET3_LINK_DOWN 0
790 #define VMXWIFI_DRIVER_SHARED_LEN 8192
792 #define VMXNET3_DID_PASSTHRU 0xFFFF
794 #endif /* _VMXNET3_DEFS_H_ */