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34 #include <sys/queue.h>
43 #include <rte_byteorder.h>
44 #include <rte_common.h>
45 #include <rte_cycles.h>
47 #include <rte_interrupts.h>
49 #include <rte_debug.h>
51 #include <rte_atomic.h>
52 #include <rte_branch_prediction.h>
53 #include <rte_memory.h>
54 #include <rte_memzone.h>
56 #include <rte_alarm.h>
57 #include <rte_ether.h>
58 #include <rte_ethdev.h>
59 #include <rte_atomic.h>
60 #include <rte_string_fns.h>
61 #include <rte_malloc.h>
64 #include "base/vmxnet3_defs.h"
66 #include "vmxnet3_ring.h"
67 #include "vmxnet3_logs.h"
68 #include "vmxnet3_ethdev.h"
70 #define PROCESS_SYS_EVENTS 0
72 #define VMXNET3_TX_MAX_SEG UINT8_MAX
74 static int eth_vmxnet3_dev_init(struct rte_eth_dev *eth_dev);
75 static int eth_vmxnet3_dev_uninit(struct rte_eth_dev *eth_dev);
76 static int vmxnet3_dev_configure(struct rte_eth_dev *dev);
77 static int vmxnet3_dev_start(struct rte_eth_dev *dev);
78 static void vmxnet3_dev_stop(struct rte_eth_dev *dev);
79 static void vmxnet3_dev_close(struct rte_eth_dev *dev);
80 static void vmxnet3_dev_set_rxmode(struct vmxnet3_hw *hw, uint32_t feature, int set);
81 static void vmxnet3_dev_promiscuous_enable(struct rte_eth_dev *dev);
82 static void vmxnet3_dev_promiscuous_disable(struct rte_eth_dev *dev);
83 static void vmxnet3_dev_allmulticast_enable(struct rte_eth_dev *dev);
84 static void vmxnet3_dev_allmulticast_disable(struct rte_eth_dev *dev);
85 static int vmxnet3_dev_link_update(struct rte_eth_dev *dev,
86 int wait_to_complete);
87 static void vmxnet3_dev_stats_get(struct rte_eth_dev *dev,
88 struct rte_eth_stats *stats);
89 static void vmxnet3_dev_info_get(struct rte_eth_dev *dev,
90 struct rte_eth_dev_info *dev_info);
91 static const uint32_t *
92 vmxnet3_dev_supported_ptypes_get(struct rte_eth_dev *dev);
93 static int vmxnet3_dev_vlan_filter_set(struct rte_eth_dev *dev,
94 uint16_t vid, int on);
95 static void vmxnet3_dev_vlan_offload_set(struct rte_eth_dev *dev, int mask);
96 static void vmxnet3_mac_addr_set(struct rte_eth_dev *dev,
97 struct ether_addr *mac_addr);
99 #if PROCESS_SYS_EVENTS == 1
100 static void vmxnet3_process_events(struct vmxnet3_hw *);
103 * The set of PCI devices this driver supports
105 #define VMWARE_PCI_VENDOR_ID 0x15AD
106 #define VMWARE_DEV_ID_VMXNET3 0x07B0
107 static const struct rte_pci_id pci_id_vmxnet3_map[] = {
108 { RTE_PCI_DEVICE(VMWARE_PCI_VENDOR_ID, VMWARE_DEV_ID_VMXNET3) },
109 { .vendor_id = 0, /* sentinel */ },
112 static const struct eth_dev_ops vmxnet3_eth_dev_ops = {
113 .dev_configure = vmxnet3_dev_configure,
114 .dev_start = vmxnet3_dev_start,
115 .dev_stop = vmxnet3_dev_stop,
116 .dev_close = vmxnet3_dev_close,
117 .promiscuous_enable = vmxnet3_dev_promiscuous_enable,
118 .promiscuous_disable = vmxnet3_dev_promiscuous_disable,
119 .allmulticast_enable = vmxnet3_dev_allmulticast_enable,
120 .allmulticast_disable = vmxnet3_dev_allmulticast_disable,
121 .link_update = vmxnet3_dev_link_update,
122 .stats_get = vmxnet3_dev_stats_get,
123 .mac_addr_set = vmxnet3_mac_addr_set,
124 .dev_infos_get = vmxnet3_dev_info_get,
125 .dev_supported_ptypes_get = vmxnet3_dev_supported_ptypes_get,
126 .vlan_filter_set = vmxnet3_dev_vlan_filter_set,
127 .vlan_offload_set = vmxnet3_dev_vlan_offload_set,
128 .rx_queue_setup = vmxnet3_dev_rx_queue_setup,
129 .rx_queue_release = vmxnet3_dev_rx_queue_release,
130 .tx_queue_setup = vmxnet3_dev_tx_queue_setup,
131 .tx_queue_release = vmxnet3_dev_tx_queue_release,
134 static const struct rte_memzone *
135 gpa_zone_reserve(struct rte_eth_dev *dev, uint32_t size,
136 const char *post_string, int socket_id,
137 uint16_t align, bool reuse)
139 char z_name[RTE_MEMZONE_NAMESIZE];
140 const struct rte_memzone *mz;
142 snprintf(z_name, sizeof(z_name), "%s_%d_%s",
143 dev->data->drv_name, dev->data->port_id, post_string);
145 mz = rte_memzone_lookup(z_name);
148 rte_memzone_free(mz);
149 return rte_memzone_reserve_aligned(z_name, size, socket_id,
156 return rte_memzone_reserve_aligned(z_name, size, socket_id, 0, align);
160 * Atomically reads the link status information from global
161 * structure rte_eth_dev.
164 * - Pointer to the structure rte_eth_dev to read from.
165 * - Pointer to the buffer to be saved with the link status.
168 * - On success, zero.
169 * - On failure, negative value.
173 vmxnet3_dev_atomic_read_link_status(struct rte_eth_dev *dev,
174 struct rte_eth_link *link)
176 struct rte_eth_link *dst = link;
177 struct rte_eth_link *src = &(dev->data->dev_link);
179 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
180 *(uint64_t *)src) == 0)
187 * Atomically writes the link status information into global
188 * structure rte_eth_dev.
191 * - Pointer to the structure rte_eth_dev to write to.
192 * - Pointer to the buffer to be saved with the link status.
195 * - On success, zero.
196 * - On failure, negative value.
199 vmxnet3_dev_atomic_write_link_status(struct rte_eth_dev *dev,
200 struct rte_eth_link *link)
202 struct rte_eth_link *dst = &(dev->data->dev_link);
203 struct rte_eth_link *src = link;
205 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
206 *(uint64_t *)src) == 0)
213 * This function is based on vmxnet3_disable_intr()
216 vmxnet3_disable_intr(struct vmxnet3_hw *hw)
220 PMD_INIT_FUNC_TRACE();
222 hw->shared->devRead.intrConf.intrCtrl |= VMXNET3_IC_DISABLE_ALL;
223 for (i = 0; i < VMXNET3_MAX_INTRS; i++)
224 VMXNET3_WRITE_BAR0_REG(hw, VMXNET3_REG_IMR + i * 8, 1);
228 * It returns 0 on success.
231 eth_vmxnet3_dev_init(struct rte_eth_dev *eth_dev)
233 struct rte_pci_device *pci_dev;
234 struct vmxnet3_hw *hw = eth_dev->data->dev_private;
235 uint32_t mac_hi, mac_lo, ver;
237 PMD_INIT_FUNC_TRACE();
239 eth_dev->dev_ops = &vmxnet3_eth_dev_ops;
240 eth_dev->rx_pkt_burst = &vmxnet3_recv_pkts;
241 eth_dev->tx_pkt_burst = &vmxnet3_xmit_pkts;
242 eth_dev->tx_pkt_prepare = vmxnet3_prep_pkts;
243 pci_dev = RTE_DEV_TO_PCI(eth_dev->device);
246 * for secondary processes, we don't initialize any further as primary
247 * has already done this work.
249 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
252 rte_eth_copy_pci_info(eth_dev, pci_dev);
253 eth_dev->data->dev_flags |= RTE_ETH_DEV_DETACHABLE;
255 /* Vendor and Device ID need to be set before init of shared code */
256 hw->device_id = pci_dev->id.device_id;
257 hw->vendor_id = pci_dev->id.vendor_id;
258 hw->hw_addr0 = (void *)pci_dev->mem_resource[0].addr;
259 hw->hw_addr1 = (void *)pci_dev->mem_resource[1].addr;
261 hw->num_rx_queues = 1;
262 hw->num_tx_queues = 1;
263 hw->bufs_per_pkt = 1;
265 /* Check h/w version compatibility with driver. */
266 ver = VMXNET3_READ_BAR1_REG(hw, VMXNET3_REG_VRRS);
267 PMD_INIT_LOG(DEBUG, "Hardware version : %d", ver);
269 if (ver & (1 << VMXNET3_REV_2)) {
270 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_VRRS,
272 hw->version = VMXNET3_REV_2 + 1;
273 } else if (ver & (1 << VMXNET3_REV_1)) {
274 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_VRRS,
276 hw->version = VMXNET3_REV_1 + 1;
278 PMD_INIT_LOG(ERR, "Incompatible hardware version: %d", ver);
282 PMD_INIT_LOG(DEBUG, "Using device version %d\n", hw->version);
284 /* Check UPT version compatibility with driver. */
285 ver = VMXNET3_READ_BAR1_REG(hw, VMXNET3_REG_UVRS);
286 PMD_INIT_LOG(DEBUG, "UPT hardware version : %d", ver);
288 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_UVRS, 1);
290 PMD_INIT_LOG(ERR, "Incompatible UPT version.");
294 /* Getting MAC Address */
295 mac_lo = VMXNET3_READ_BAR1_REG(hw, VMXNET3_REG_MACL);
296 mac_hi = VMXNET3_READ_BAR1_REG(hw, VMXNET3_REG_MACH);
297 memcpy(hw->perm_addr, &mac_lo, 4);
298 memcpy(hw->perm_addr + 4, &mac_hi, 2);
300 /* Allocate memory for storing MAC addresses */
301 eth_dev->data->mac_addrs = rte_zmalloc("vmxnet3", ETHER_ADDR_LEN *
302 VMXNET3_MAX_MAC_ADDRS, 0);
303 if (eth_dev->data->mac_addrs == NULL) {
305 "Failed to allocate %d bytes needed to store MAC addresses",
306 ETHER_ADDR_LEN * VMXNET3_MAX_MAC_ADDRS);
309 /* Copy the permanent MAC address */
310 ether_addr_copy((struct ether_addr *) hw->perm_addr,
311 ð_dev->data->mac_addrs[0]);
313 PMD_INIT_LOG(DEBUG, "MAC Address : %02x:%02x:%02x:%02x:%02x:%02x",
314 hw->perm_addr[0], hw->perm_addr[1], hw->perm_addr[2],
315 hw->perm_addr[3], hw->perm_addr[4], hw->perm_addr[5]);
317 /* Put device in Quiesce Mode */
318 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, VMXNET3_CMD_QUIESCE_DEV);
320 /* allow untagged pkts */
321 VMXNET3_SET_VFTABLE_ENTRY(hw->shadow_vfta, 0);
327 eth_vmxnet3_dev_uninit(struct rte_eth_dev *eth_dev)
329 struct vmxnet3_hw *hw = eth_dev->data->dev_private;
331 PMD_INIT_FUNC_TRACE();
333 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
336 if (hw->adapter_stopped == 0)
337 vmxnet3_dev_close(eth_dev);
339 eth_dev->dev_ops = NULL;
340 eth_dev->rx_pkt_burst = NULL;
341 eth_dev->tx_pkt_burst = NULL;
342 eth_dev->tx_pkt_prepare = NULL;
344 rte_free(eth_dev->data->mac_addrs);
345 eth_dev->data->mac_addrs = NULL;
350 static struct eth_driver rte_vmxnet3_pmd = {
352 .id_table = pci_id_vmxnet3_map,
353 .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
354 .probe = rte_eth_dev_pci_probe,
355 .remove = rte_eth_dev_pci_remove,
357 .eth_dev_init = eth_vmxnet3_dev_init,
358 .eth_dev_uninit = eth_vmxnet3_dev_uninit,
359 .dev_private_size = sizeof(struct vmxnet3_hw),
363 vmxnet3_dev_configure(struct rte_eth_dev *dev)
365 const struct rte_memzone *mz;
366 struct vmxnet3_hw *hw = dev->data->dev_private;
369 PMD_INIT_FUNC_TRACE();
371 if (dev->data->nb_tx_queues > VMXNET3_MAX_TX_QUEUES ||
372 dev->data->nb_rx_queues > VMXNET3_MAX_RX_QUEUES) {
373 PMD_INIT_LOG(ERR, "ERROR: Number of queues not supported");
377 if (!rte_is_power_of_2(dev->data->nb_rx_queues)) {
378 PMD_INIT_LOG(ERR, "ERROR: Number of rx queues not power of 2");
382 size = dev->data->nb_rx_queues * sizeof(struct Vmxnet3_TxQueueDesc) +
383 dev->data->nb_tx_queues * sizeof(struct Vmxnet3_RxQueueDesc);
385 if (size > UINT16_MAX)
388 hw->num_rx_queues = (uint8_t)dev->data->nb_rx_queues;
389 hw->num_tx_queues = (uint8_t)dev->data->nb_tx_queues;
392 * Allocate a memzone for Vmxnet3_DriverShared - Vmxnet3_DSDevRead
395 mz = gpa_zone_reserve(dev, sizeof(struct Vmxnet3_DriverShared),
396 "shared", rte_socket_id(), 8, 1);
399 PMD_INIT_LOG(ERR, "ERROR: Creating shared zone");
402 memset(mz->addr, 0, mz->len);
404 hw->shared = mz->addr;
405 hw->sharedPA = mz->phys_addr;
408 * Allocate a memzone for Vmxnet3_RxQueueDesc - Vmxnet3_TxQueueDesc
411 * We cannot reuse this memzone from previous allocation as its size
412 * depends on the number of tx and rx queues, which could be different
413 * from one config to another.
415 mz = gpa_zone_reserve(dev, size, "queuedesc", rte_socket_id(),
416 VMXNET3_QUEUE_DESC_ALIGN, 0);
418 PMD_INIT_LOG(ERR, "ERROR: Creating queue descriptors zone");
421 memset(mz->addr, 0, mz->len);
423 hw->tqd_start = (Vmxnet3_TxQueueDesc *)mz->addr;
424 hw->rqd_start = (Vmxnet3_RxQueueDesc *)(hw->tqd_start + hw->num_tx_queues);
426 hw->queueDescPA = mz->phys_addr;
427 hw->queue_desc_len = (uint16_t)size;
429 if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_RSS) {
430 /* Allocate memory structure for UPT1_RSSConf and configure */
431 mz = gpa_zone_reserve(dev, sizeof(struct VMXNET3_RSSConf),
432 "rss_conf", rte_socket_id(),
433 RTE_CACHE_LINE_SIZE, 1);
436 "ERROR: Creating rss_conf structure zone");
439 memset(mz->addr, 0, mz->len);
441 hw->rss_conf = mz->addr;
442 hw->rss_confPA = mz->phys_addr;
449 vmxnet3_write_mac(struct vmxnet3_hw *hw, const uint8_t *addr)
454 "Writing MAC Address : %02x:%02x:%02x:%02x:%02x:%02x",
455 addr[0], addr[1], addr[2],
456 addr[3], addr[4], addr[5]);
458 val = *(const uint32_t *)addr;
459 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_MACL, val);
461 val = (addr[5] << 8) | addr[4];
462 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_MACH, val);
466 vmxnet3_setup_driver_shared(struct rte_eth_dev *dev)
468 struct rte_eth_conf port_conf = dev->data->dev_conf;
469 struct vmxnet3_hw *hw = dev->data->dev_private;
470 uint32_t mtu = dev->data->mtu;
471 Vmxnet3_DriverShared *shared = hw->shared;
472 Vmxnet3_DSDevRead *devRead = &shared->devRead;
476 shared->magic = VMXNET3_REV1_MAGIC;
477 devRead->misc.driverInfo.version = VMXNET3_DRIVER_VERSION_NUM;
479 /* Setting up Guest OS information */
480 devRead->misc.driverInfo.gos.gosBits = sizeof(void *) == 4 ?
481 VMXNET3_GOS_BITS_32 : VMXNET3_GOS_BITS_64;
482 devRead->misc.driverInfo.gos.gosType = VMXNET3_GOS_TYPE_LINUX;
483 devRead->misc.driverInfo.vmxnet3RevSpt = 1;
484 devRead->misc.driverInfo.uptVerSpt = 1;
486 devRead->misc.mtu = rte_le_to_cpu_32(mtu);
487 devRead->misc.queueDescPA = hw->queueDescPA;
488 devRead->misc.queueDescLen = hw->queue_desc_len;
489 devRead->misc.numTxQueues = hw->num_tx_queues;
490 devRead->misc.numRxQueues = hw->num_rx_queues;
493 * Set number of interrupts to 1
494 * PMD disables all the interrupts but this is MUST to activate device
495 * It needs at least one interrupt for link events to handle
496 * So we'll disable it later after device activation if needed
498 devRead->intrConf.numIntrs = 1;
499 devRead->intrConf.intrCtrl |= VMXNET3_IC_DISABLE_ALL;
501 for (i = 0; i < hw->num_tx_queues; i++) {
502 Vmxnet3_TxQueueDesc *tqd = &hw->tqd_start[i];
503 vmxnet3_tx_queue_t *txq = dev->data->tx_queues[i];
505 tqd->ctrl.txNumDeferred = 0;
506 tqd->ctrl.txThreshold = 1;
507 tqd->conf.txRingBasePA = txq->cmd_ring.basePA;
508 tqd->conf.compRingBasePA = txq->comp_ring.basePA;
509 tqd->conf.dataRingBasePA = txq->data_ring.basePA;
511 tqd->conf.txRingSize = txq->cmd_ring.size;
512 tqd->conf.compRingSize = txq->comp_ring.size;
513 tqd->conf.dataRingSize = txq->data_ring.size;
514 tqd->conf.intrIdx = txq->comp_ring.intr_idx;
515 tqd->status.stopped = TRUE;
516 tqd->status.error = 0;
517 memset(&tqd->stats, 0, sizeof(tqd->stats));
520 for (i = 0; i < hw->num_rx_queues; i++) {
521 Vmxnet3_RxQueueDesc *rqd = &hw->rqd_start[i];
522 vmxnet3_rx_queue_t *rxq = dev->data->rx_queues[i];
524 rqd->conf.rxRingBasePA[0] = rxq->cmd_ring[0].basePA;
525 rqd->conf.rxRingBasePA[1] = rxq->cmd_ring[1].basePA;
526 rqd->conf.compRingBasePA = rxq->comp_ring.basePA;
528 rqd->conf.rxRingSize[0] = rxq->cmd_ring[0].size;
529 rqd->conf.rxRingSize[1] = rxq->cmd_ring[1].size;
530 rqd->conf.compRingSize = rxq->comp_ring.size;
531 rqd->conf.intrIdx = rxq->comp_ring.intr_idx;
532 rqd->status.stopped = TRUE;
533 rqd->status.error = 0;
534 memset(&rqd->stats, 0, sizeof(rqd->stats));
537 /* RxMode set to 0 of VMXNET3_RXM_xxx */
538 devRead->rxFilterConf.rxMode = 0;
540 /* Setting up feature flags */
541 if (dev->data->dev_conf.rxmode.hw_ip_checksum)
542 devRead->misc.uptFeatures |= VMXNET3_F_RXCSUM;
544 if (dev->data->dev_conf.rxmode.enable_lro) {
545 devRead->misc.uptFeatures |= VMXNET3_F_LRO;
546 devRead->misc.maxNumRxSG = 0;
549 if (port_conf.rxmode.mq_mode == ETH_MQ_RX_RSS) {
550 ret = vmxnet3_rss_configure(dev);
551 if (ret != VMXNET3_SUCCESS)
554 devRead->misc.uptFeatures |= VMXNET3_F_RSS;
555 devRead->rssConfDesc.confVer = 1;
556 devRead->rssConfDesc.confLen = sizeof(struct VMXNET3_RSSConf);
557 devRead->rssConfDesc.confPA = hw->rss_confPA;
560 vmxnet3_dev_vlan_offload_set(dev,
561 ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK);
563 vmxnet3_write_mac(hw, hw->perm_addr);
565 return VMXNET3_SUCCESS;
569 * Configure device link speed and setup link.
570 * Must be called after eth_vmxnet3_dev_init. Other wise it might fail
571 * It returns 0 on success.
574 vmxnet3_dev_start(struct rte_eth_dev *dev)
577 struct vmxnet3_hw *hw = dev->data->dev_private;
579 PMD_INIT_FUNC_TRACE();
581 ret = vmxnet3_setup_driver_shared(dev);
582 if (ret != VMXNET3_SUCCESS)
585 /* Exchange shared data with device */
586 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_DSAL,
587 VMXNET3_GET_ADDR_LO(hw->sharedPA));
588 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_DSAH,
589 VMXNET3_GET_ADDR_HI(hw->sharedPA));
591 /* Activate device by register write */
592 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, VMXNET3_CMD_ACTIVATE_DEV);
593 ret = VMXNET3_READ_BAR1_REG(hw, VMXNET3_REG_CMD);
596 PMD_INIT_LOG(ERR, "Device activation: UNSUCCESSFUL");
600 /* Disable interrupts */
601 vmxnet3_disable_intr(hw);
604 * Load RX queues with blank mbufs and update next2fill index for device
605 * Update RxMode of the device
607 ret = vmxnet3_dev_rxtx_init(dev);
608 if (ret != VMXNET3_SUCCESS) {
609 PMD_INIT_LOG(ERR, "Device queue init: UNSUCCESSFUL");
613 /* Setting proper Rx Mode and issue Rx Mode Update command */
614 vmxnet3_dev_set_rxmode(hw, VMXNET3_RXM_UCAST | VMXNET3_RXM_BCAST, 1);
617 * Don't need to handle events for now
619 #if PROCESS_SYS_EVENTS == 1
620 events = VMXNET3_READ_BAR1_REG(hw, VMXNET3_REG_ECR);
621 PMD_INIT_LOG(DEBUG, "Reading events: 0x%X", events);
622 vmxnet3_process_events(hw);
624 return VMXNET3_SUCCESS;
628 * Stop device: disable rx and tx functions to allow for reconfiguring.
631 vmxnet3_dev_stop(struct rte_eth_dev *dev)
633 struct rte_eth_link link;
634 struct vmxnet3_hw *hw = dev->data->dev_private;
636 PMD_INIT_FUNC_TRACE();
638 if (hw->adapter_stopped == 1) {
639 PMD_INIT_LOG(DEBUG, "Device already closed.");
643 /* disable interrupts */
644 vmxnet3_disable_intr(hw);
646 /* quiesce the device first */
647 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, VMXNET3_CMD_QUIESCE_DEV);
648 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_DSAL, 0);
649 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_DSAH, 0);
651 /* reset the device */
652 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, VMXNET3_CMD_RESET_DEV);
653 PMD_INIT_LOG(DEBUG, "Device reset.");
654 hw->adapter_stopped = 0;
656 vmxnet3_dev_clear_queues(dev);
658 /* Clear recorded link status */
659 memset(&link, 0, sizeof(link));
660 vmxnet3_dev_atomic_write_link_status(dev, &link);
664 * Reset and stop device.
667 vmxnet3_dev_close(struct rte_eth_dev *dev)
669 struct vmxnet3_hw *hw = dev->data->dev_private;
671 PMD_INIT_FUNC_TRACE();
673 vmxnet3_dev_stop(dev);
674 hw->adapter_stopped = 1;
678 vmxnet3_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
681 struct vmxnet3_hw *hw = dev->data->dev_private;
683 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, VMXNET3_CMD_GET_STATS);
685 RTE_BUILD_BUG_ON(RTE_ETHDEV_QUEUE_STAT_CNTRS < VMXNET3_MAX_TX_QUEUES);
686 for (i = 0; i < hw->num_tx_queues; i++) {
687 struct UPT1_TxStats *txStats = &hw->tqd_start[i].stats;
689 stats->q_opackets[i] = txStats->ucastPktsTxOK +
690 txStats->mcastPktsTxOK +
691 txStats->bcastPktsTxOK;
692 stats->q_obytes[i] = txStats->ucastBytesTxOK +
693 txStats->mcastBytesTxOK +
694 txStats->bcastBytesTxOK;
696 stats->opackets += stats->q_opackets[i];
697 stats->obytes += stats->q_obytes[i];
698 stats->oerrors += txStats->pktsTxError + txStats->pktsTxDiscard;
701 RTE_BUILD_BUG_ON(RTE_ETHDEV_QUEUE_STAT_CNTRS < VMXNET3_MAX_RX_QUEUES);
702 for (i = 0; i < hw->num_rx_queues; i++) {
703 struct UPT1_RxStats *rxStats = &hw->rqd_start[i].stats;
705 stats->q_ipackets[i] = rxStats->ucastPktsRxOK +
706 rxStats->mcastPktsRxOK +
707 rxStats->bcastPktsRxOK;
709 stats->q_ibytes[i] = rxStats->ucastBytesRxOK +
710 rxStats->mcastBytesRxOK +
711 rxStats->bcastBytesRxOK;
713 stats->ipackets += stats->q_ipackets[i];
714 stats->ibytes += stats->q_ibytes[i];
716 stats->q_errors[i] = rxStats->pktsRxError;
717 stats->ierrors += rxStats->pktsRxError;
718 stats->rx_nombuf += rxStats->pktsRxOutOfBuf;
723 vmxnet3_dev_info_get(struct rte_eth_dev *dev,
724 struct rte_eth_dev_info *dev_info)
726 dev_info->pci_dev = RTE_DEV_TO_PCI(dev->device);
728 dev_info->max_rx_queues = VMXNET3_MAX_RX_QUEUES;
729 dev_info->max_tx_queues = VMXNET3_MAX_TX_QUEUES;
730 dev_info->min_rx_bufsize = 1518 + RTE_PKTMBUF_HEADROOM;
731 dev_info->max_rx_pktlen = 16384; /* includes CRC, cf MAXFRS register */
732 dev_info->speed_capa = ETH_LINK_SPEED_10G;
733 dev_info->max_mac_addrs = VMXNET3_MAX_MAC_ADDRS;
735 dev_info->default_txconf.txq_flags = ETH_TXQ_FLAGS_NOXSUMSCTP;
736 dev_info->flow_type_rss_offloads = VMXNET3_RSS_OFFLOAD_ALL;
738 dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
739 .nb_max = VMXNET3_RX_RING_MAX_SIZE,
740 .nb_min = VMXNET3_DEF_RX_RING_SIZE,
744 dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
745 .nb_max = VMXNET3_TX_RING_MAX_SIZE,
746 .nb_min = VMXNET3_DEF_TX_RING_SIZE,
748 .nb_seg_max = VMXNET3_TX_MAX_SEG,
749 .nb_mtu_seg_max = VMXNET3_MAX_TXD_PER_PKT,
752 dev_info->rx_offload_capa =
753 DEV_RX_OFFLOAD_VLAN_STRIP |
754 DEV_RX_OFFLOAD_UDP_CKSUM |
755 DEV_RX_OFFLOAD_TCP_CKSUM |
756 DEV_RX_OFFLOAD_TCP_LRO;
758 dev_info->tx_offload_capa =
759 DEV_TX_OFFLOAD_VLAN_INSERT |
760 DEV_TX_OFFLOAD_TCP_CKSUM |
761 DEV_TX_OFFLOAD_UDP_CKSUM |
762 DEV_TX_OFFLOAD_TCP_TSO;
765 static const uint32_t *
766 vmxnet3_dev_supported_ptypes_get(struct rte_eth_dev *dev)
768 static const uint32_t ptypes[] = {
769 RTE_PTYPE_L3_IPV4_EXT,
774 if (dev->rx_pkt_burst == vmxnet3_recv_pkts)
780 vmxnet3_mac_addr_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr)
782 struct vmxnet3_hw *hw = dev->data->dev_private;
784 vmxnet3_write_mac(hw, mac_addr->addr_bytes);
787 /* return 0 means link status changed, -1 means not changed */
789 vmxnet3_dev_link_update(struct rte_eth_dev *dev,
790 __rte_unused int wait_to_complete)
792 struct vmxnet3_hw *hw = dev->data->dev_private;
793 struct rte_eth_link old, link;
796 /* Link status doesn't change for stopped dev */
797 if (dev->data->dev_started == 0)
800 memset(&link, 0, sizeof(link));
801 vmxnet3_dev_atomic_read_link_status(dev, &old);
803 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, VMXNET3_CMD_GET_LINK);
804 ret = VMXNET3_READ_BAR1_REG(hw, VMXNET3_REG_CMD);
807 link.link_status = ETH_LINK_UP;
808 link.link_duplex = ETH_LINK_FULL_DUPLEX;
809 link.link_speed = ETH_SPEED_NUM_10G;
810 link.link_autoneg = ETH_LINK_SPEED_FIXED;
813 vmxnet3_dev_atomic_write_link_status(dev, &link);
815 return (old.link_status == link.link_status) ? -1 : 0;
818 /* Updating rxmode through Vmxnet3_DriverShared structure in adapter */
820 vmxnet3_dev_set_rxmode(struct vmxnet3_hw *hw, uint32_t feature, int set)
822 struct Vmxnet3_RxFilterConf *rxConf = &hw->shared->devRead.rxFilterConf;
825 rxConf->rxMode = rxConf->rxMode | feature;
827 rxConf->rxMode = rxConf->rxMode & (~feature);
829 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, VMXNET3_CMD_UPDATE_RX_MODE);
832 /* Promiscuous supported only if Vmxnet3_DriverShared is initialized in adapter */
834 vmxnet3_dev_promiscuous_enable(struct rte_eth_dev *dev)
836 struct vmxnet3_hw *hw = dev->data->dev_private;
837 uint32_t *vf_table = hw->shared->devRead.rxFilterConf.vfTable;
839 memset(vf_table, 0, VMXNET3_VFT_TABLE_SIZE);
840 vmxnet3_dev_set_rxmode(hw, VMXNET3_RXM_PROMISC, 1);
842 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD,
843 VMXNET3_CMD_UPDATE_VLAN_FILTERS);
846 /* Promiscuous supported only if Vmxnet3_DriverShared is initialized in adapter */
848 vmxnet3_dev_promiscuous_disable(struct rte_eth_dev *dev)
850 struct vmxnet3_hw *hw = dev->data->dev_private;
851 uint32_t *vf_table = hw->shared->devRead.rxFilterConf.vfTable;
853 memcpy(vf_table, hw->shadow_vfta, VMXNET3_VFT_TABLE_SIZE);
854 vmxnet3_dev_set_rxmode(hw, VMXNET3_RXM_PROMISC, 0);
855 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD,
856 VMXNET3_CMD_UPDATE_VLAN_FILTERS);
859 /* Allmulticast supported only if Vmxnet3_DriverShared is initialized in adapter */
861 vmxnet3_dev_allmulticast_enable(struct rte_eth_dev *dev)
863 struct vmxnet3_hw *hw = dev->data->dev_private;
865 vmxnet3_dev_set_rxmode(hw, VMXNET3_RXM_ALL_MULTI, 1);
868 /* Allmulticast supported only if Vmxnet3_DriverShared is initialized in adapter */
870 vmxnet3_dev_allmulticast_disable(struct rte_eth_dev *dev)
872 struct vmxnet3_hw *hw = dev->data->dev_private;
874 vmxnet3_dev_set_rxmode(hw, VMXNET3_RXM_ALL_MULTI, 0);
877 /* Enable/disable filter on vlan */
879 vmxnet3_dev_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vid, int on)
881 struct vmxnet3_hw *hw = dev->data->dev_private;
882 struct Vmxnet3_RxFilterConf *rxConf = &hw->shared->devRead.rxFilterConf;
883 uint32_t *vf_table = rxConf->vfTable;
885 /* save state for restore */
887 VMXNET3_SET_VFTABLE_ENTRY(hw->shadow_vfta, vid);
889 VMXNET3_CLEAR_VFTABLE_ENTRY(hw->shadow_vfta, vid);
891 /* don't change active filter if in promiscuous mode */
892 if (rxConf->rxMode & VMXNET3_RXM_PROMISC)
895 /* set in hardware */
897 VMXNET3_SET_VFTABLE_ENTRY(vf_table, vid);
899 VMXNET3_CLEAR_VFTABLE_ENTRY(vf_table, vid);
901 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD,
902 VMXNET3_CMD_UPDATE_VLAN_FILTERS);
907 vmxnet3_dev_vlan_offload_set(struct rte_eth_dev *dev, int mask)
909 struct vmxnet3_hw *hw = dev->data->dev_private;
910 Vmxnet3_DSDevRead *devRead = &hw->shared->devRead;
911 uint32_t *vf_table = devRead->rxFilterConf.vfTable;
913 if (mask & ETH_VLAN_STRIP_MASK) {
914 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
915 devRead->misc.uptFeatures |= UPT1_F_RXVLAN;
917 devRead->misc.uptFeatures &= ~UPT1_F_RXVLAN;
919 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD,
920 VMXNET3_CMD_UPDATE_FEATURE);
923 if (mask & ETH_VLAN_FILTER_MASK) {
924 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
925 memcpy(vf_table, hw->shadow_vfta, VMXNET3_VFT_TABLE_SIZE);
927 memset(vf_table, 0xff, VMXNET3_VFT_TABLE_SIZE);
929 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD,
930 VMXNET3_CMD_UPDATE_VLAN_FILTERS);
934 #if PROCESS_SYS_EVENTS == 1
936 vmxnet3_process_events(struct vmxnet3_hw *hw)
938 uint32_t events = hw->shared->ecr;
941 PMD_INIT_LOG(ERR, "No events to process");
946 * ECR bits when written with 1b are cleared. Hence write
947 * events back to ECR so that the bits which were set will be reset.
949 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_ECR, events);
951 /* Check if link state has changed */
952 if (events & VMXNET3_ECR_LINK)
954 "Process events in %s(): VMXNET3_ECR_LINK event",
957 /* Check if there is an error on xmit/recv queues */
958 if (events & (VMXNET3_ECR_TQERR | VMXNET3_ECR_RQERR)) {
959 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD,
960 VMXNET3_CMD_GET_QUEUE_STATUS);
962 if (hw->tqd_start->status.stopped)
963 PMD_INIT_LOG(ERR, "tq error 0x%x",
964 hw->tqd_start->status.error);
966 if (hw->rqd_start->status.stopped)
967 PMD_INIT_LOG(ERR, "rq error 0x%x",
968 hw->rqd_start->status.error);
970 /* Reset the device */
971 /* Have to reset the device */
974 if (events & VMXNET3_ECR_DIC)
975 PMD_INIT_LOG(ERR, "Device implementation change event.");
977 if (events & VMXNET3_ECR_DEBUG)
978 PMD_INIT_LOG(ERR, "Debug event generated by device.");
982 RTE_PMD_REGISTER_PCI(net_vmxnet3, rte_vmxnet3_pmd.pci_drv);
983 RTE_PMD_REGISTER_PCI_TABLE(net_vmxnet3, pci_id_vmxnet3_map);
984 RTE_PMD_REGISTER_KMOD_DEP(net_vmxnet3, "* igb_uio | uio_pci_generic | vfio");