net/qede/base: support doorbell overflow recovery
[dpdk.git] / drivers / net / vmxnet3 / vmxnet3_ethdev.c
1 /*-
2  *   BSD LICENSE
3  *
4  *   Copyright(c) 2010-2015 Intel Corporation. All rights reserved.
5  *   All rights reserved.
6  *
7  *   Redistribution and use in source and binary forms, with or without
8  *   modification, are permitted provided that the following conditions
9  *   are met:
10  *
11  *     * Redistributions of source code must retain the above copyright
12  *       notice, this list of conditions and the following disclaimer.
13  *     * Redistributions in binary form must reproduce the above copyright
14  *       notice, this list of conditions and the following disclaimer in
15  *       the documentation and/or other materials provided with the
16  *       distribution.
17  *     * Neither the name of Intel Corporation nor the names of its
18  *       contributors may be used to endorse or promote products derived
19  *       from this software without specific prior written permission.
20  *
21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32  */
33
34 #include <sys/queue.h>
35 #include <stdio.h>
36 #include <errno.h>
37 #include <stdint.h>
38 #include <string.h>
39 #include <unistd.h>
40 #include <stdarg.h>
41 #include <fcntl.h>
42 #include <inttypes.h>
43 #include <rte_byteorder.h>
44 #include <rte_common.h>
45 #include <rte_cycles.h>
46
47 #include <rte_interrupts.h>
48 #include <rte_log.h>
49 #include <rte_debug.h>
50 #include <rte_pci.h>
51 #include <rte_atomic.h>
52 #include <rte_branch_prediction.h>
53 #include <rte_memory.h>
54 #include <rte_memzone.h>
55 #include <rte_eal.h>
56 #include <rte_alarm.h>
57 #include <rte_ether.h>
58 #include <rte_ethdev.h>
59 #include <rte_ethdev_pci.h>
60 #include <rte_string_fns.h>
61 #include <rte_malloc.h>
62 #include <rte_dev.h>
63
64 #include "base/vmxnet3_defs.h"
65
66 #include "vmxnet3_ring.h"
67 #include "vmxnet3_logs.h"
68 #include "vmxnet3_ethdev.h"
69
70 #define PROCESS_SYS_EVENTS 0
71
72 #define VMXNET3_TX_MAX_SEG      UINT8_MAX
73
74 static int eth_vmxnet3_dev_init(struct rte_eth_dev *eth_dev);
75 static int eth_vmxnet3_dev_uninit(struct rte_eth_dev *eth_dev);
76 static int vmxnet3_dev_configure(struct rte_eth_dev *dev);
77 static int vmxnet3_dev_start(struct rte_eth_dev *dev);
78 static void vmxnet3_dev_stop(struct rte_eth_dev *dev);
79 static void vmxnet3_dev_close(struct rte_eth_dev *dev);
80 static void vmxnet3_dev_set_rxmode(struct vmxnet3_hw *hw, uint32_t feature, int set);
81 static void vmxnet3_dev_promiscuous_enable(struct rte_eth_dev *dev);
82 static void vmxnet3_dev_promiscuous_disable(struct rte_eth_dev *dev);
83 static void vmxnet3_dev_allmulticast_enable(struct rte_eth_dev *dev);
84 static void vmxnet3_dev_allmulticast_disable(struct rte_eth_dev *dev);
85 static int __vmxnet3_dev_link_update(struct rte_eth_dev *dev,
86                                      int wait_to_complete);
87 static int vmxnet3_dev_link_update(struct rte_eth_dev *dev,
88                                    int wait_to_complete);
89 static void vmxnet3_hw_stats_save(struct vmxnet3_hw *hw);
90 static void vmxnet3_dev_stats_get(struct rte_eth_dev *dev,
91                                   struct rte_eth_stats *stats);
92 static int vmxnet3_dev_xstats_get_names(struct rte_eth_dev *dev,
93                                         struct rte_eth_xstat_name *xstats,
94                                         unsigned int n);
95 static int vmxnet3_dev_xstats_get(struct rte_eth_dev *dev,
96                                   struct rte_eth_xstat *xstats, unsigned int n);
97 static void vmxnet3_dev_info_get(struct rte_eth_dev *dev,
98                                  struct rte_eth_dev_info *dev_info);
99 static const uint32_t *
100 vmxnet3_dev_supported_ptypes_get(struct rte_eth_dev *dev);
101 static int vmxnet3_dev_vlan_filter_set(struct rte_eth_dev *dev,
102                                        uint16_t vid, int on);
103 static void vmxnet3_dev_vlan_offload_set(struct rte_eth_dev *dev, int mask);
104 static void vmxnet3_mac_addr_set(struct rte_eth_dev *dev,
105                                  struct ether_addr *mac_addr);
106 static void vmxnet3_interrupt_handler(void *param);
107
108 /*
109  * The set of PCI devices this driver supports
110  */
111 #define VMWARE_PCI_VENDOR_ID 0x15AD
112 #define VMWARE_DEV_ID_VMXNET3 0x07B0
113 static const struct rte_pci_id pci_id_vmxnet3_map[] = {
114         { RTE_PCI_DEVICE(VMWARE_PCI_VENDOR_ID, VMWARE_DEV_ID_VMXNET3) },
115         { .vendor_id = 0, /* sentinel */ },
116 };
117
118 static const struct eth_dev_ops vmxnet3_eth_dev_ops = {
119         .dev_configure        = vmxnet3_dev_configure,
120         .dev_start            = vmxnet3_dev_start,
121         .dev_stop             = vmxnet3_dev_stop,
122         .dev_close            = vmxnet3_dev_close,
123         .promiscuous_enable   = vmxnet3_dev_promiscuous_enable,
124         .promiscuous_disable  = vmxnet3_dev_promiscuous_disable,
125         .allmulticast_enable  = vmxnet3_dev_allmulticast_enable,
126         .allmulticast_disable = vmxnet3_dev_allmulticast_disable,
127         .link_update          = vmxnet3_dev_link_update,
128         .stats_get            = vmxnet3_dev_stats_get,
129         .xstats_get_names     = vmxnet3_dev_xstats_get_names,
130         .xstats_get           = vmxnet3_dev_xstats_get,
131         .mac_addr_set         = vmxnet3_mac_addr_set,
132         .dev_infos_get        = vmxnet3_dev_info_get,
133         .dev_supported_ptypes_get = vmxnet3_dev_supported_ptypes_get,
134         .vlan_filter_set      = vmxnet3_dev_vlan_filter_set,
135         .vlan_offload_set     = vmxnet3_dev_vlan_offload_set,
136         .rx_queue_setup       = vmxnet3_dev_rx_queue_setup,
137         .rx_queue_release     = vmxnet3_dev_rx_queue_release,
138         .tx_queue_setup       = vmxnet3_dev_tx_queue_setup,
139         .tx_queue_release     = vmxnet3_dev_tx_queue_release,
140 };
141
142 struct vmxnet3_xstats_name_off {
143         char name[RTE_ETH_XSTATS_NAME_SIZE];
144         unsigned int offset;
145 };
146
147 /* tx_qX_ is prepended to the name string here */
148 static const struct vmxnet3_xstats_name_off vmxnet3_txq_stat_strings[] = {
149         {"drop_total",         offsetof(struct vmxnet3_txq_stats, drop_total)},
150         {"drop_too_many_segs", offsetof(struct vmxnet3_txq_stats, drop_too_many_segs)},
151         {"drop_tso",           offsetof(struct vmxnet3_txq_stats, drop_tso)},
152         {"tx_ring_full",       offsetof(struct vmxnet3_txq_stats, tx_ring_full)},
153 };
154
155 /* rx_qX_ is prepended to the name string here */
156 static const struct vmxnet3_xstats_name_off vmxnet3_rxq_stat_strings[] = {
157         {"drop_total",           offsetof(struct vmxnet3_rxq_stats, drop_total)},
158         {"drop_err",             offsetof(struct vmxnet3_rxq_stats, drop_err)},
159         {"drop_fcs",             offsetof(struct vmxnet3_rxq_stats, drop_fcs)},
160         {"rx_buf_alloc_failure", offsetof(struct vmxnet3_rxq_stats, rx_buf_alloc_failure)},
161 };
162
163 static const struct rte_memzone *
164 gpa_zone_reserve(struct rte_eth_dev *dev, uint32_t size,
165                  const char *post_string, int socket_id,
166                  uint16_t align, bool reuse)
167 {
168         char z_name[RTE_MEMZONE_NAMESIZE];
169         const struct rte_memzone *mz;
170
171         snprintf(z_name, sizeof(z_name), "%s_%d_%s",
172                  dev->device->driver->name, dev->data->port_id, post_string);
173
174         mz = rte_memzone_lookup(z_name);
175         if (!reuse) {
176                 if (mz)
177                         rte_memzone_free(mz);
178                 return rte_memzone_reserve_aligned(z_name, size, socket_id,
179                                                    0, align);
180         }
181
182         if (mz)
183                 return mz;
184
185         return rte_memzone_reserve_aligned(z_name, size, socket_id, 0, align);
186 }
187
188 /**
189  * Atomically reads the link status information from global
190  * structure rte_eth_dev.
191  *
192  * @param dev
193  *   - Pointer to the structure rte_eth_dev to read from.
194  *   - Pointer to the buffer to be saved with the link status.
195  *
196  * @return
197  *   - On success, zero.
198  *   - On failure, negative value.
199  */
200
201 static int
202 vmxnet3_dev_atomic_read_link_status(struct rte_eth_dev *dev,
203                                     struct rte_eth_link *link)
204 {
205         struct rte_eth_link *dst = link;
206         struct rte_eth_link *src = &(dev->data->dev_link);
207
208         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
209                                 *(uint64_t *)src) == 0)
210                 return -1;
211
212         return 0;
213 }
214
215 /**
216  * Atomically writes the link status information into global
217  * structure rte_eth_dev.
218  *
219  * @param dev
220  *   - Pointer to the structure rte_eth_dev to write to.
221  *   - Pointer to the buffer to be saved with the link status.
222  *
223  * @return
224  *   - On success, zero.
225  *   - On failure, negative value.
226  */
227 static int
228 vmxnet3_dev_atomic_write_link_status(struct rte_eth_dev *dev,
229                                      struct rte_eth_link *link)
230 {
231         struct rte_eth_link *dst = &(dev->data->dev_link);
232         struct rte_eth_link *src = link;
233
234         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
235                                 *(uint64_t *)src) == 0)
236                 return -1;
237
238         return 0;
239 }
240
241 /*
242  * This function is based on vmxnet3_disable_intr()
243  */
244 static void
245 vmxnet3_disable_intr(struct vmxnet3_hw *hw)
246 {
247         int i;
248
249         PMD_INIT_FUNC_TRACE();
250
251         hw->shared->devRead.intrConf.intrCtrl |= VMXNET3_IC_DISABLE_ALL;
252         for (i = 0; i < hw->num_intrs; i++)
253                 VMXNET3_WRITE_BAR0_REG(hw, VMXNET3_REG_IMR + i * 8, 1);
254 }
255
256 static void
257 vmxnet3_enable_intr(struct vmxnet3_hw *hw)
258 {
259         int i;
260
261         PMD_INIT_FUNC_TRACE();
262
263         hw->shared->devRead.intrConf.intrCtrl &= ~VMXNET3_IC_DISABLE_ALL;
264         for (i = 0; i < hw->num_intrs; i++)
265                 VMXNET3_WRITE_BAR0_REG(hw, VMXNET3_REG_IMR + i * 8, 0);
266 }
267
268 /*
269  * Gets tx data ring descriptor size.
270  */
271 static uint16_t
272 eth_vmxnet3_txdata_get(struct vmxnet3_hw *hw)
273 {
274         uint16 txdata_desc_size;
275
276         VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD,
277                                VMXNET3_CMD_GET_TXDATA_DESC_SIZE);
278         txdata_desc_size = VMXNET3_READ_BAR1_REG(hw, VMXNET3_REG_CMD);
279
280         return (txdata_desc_size < VMXNET3_TXDATA_DESC_MIN_SIZE ||
281                 txdata_desc_size > VMXNET3_TXDATA_DESC_MAX_SIZE ||
282                 txdata_desc_size & VMXNET3_TXDATA_DESC_SIZE_MASK) ?
283                 sizeof(struct Vmxnet3_TxDataDesc) : txdata_desc_size;
284 }
285
286 /*
287  * It returns 0 on success.
288  */
289 static int
290 eth_vmxnet3_dev_init(struct rte_eth_dev *eth_dev)
291 {
292         struct rte_pci_device *pci_dev;
293         struct vmxnet3_hw *hw = eth_dev->data->dev_private;
294         uint32_t mac_hi, mac_lo, ver;
295
296         PMD_INIT_FUNC_TRACE();
297
298         eth_dev->dev_ops = &vmxnet3_eth_dev_ops;
299         eth_dev->rx_pkt_burst = &vmxnet3_recv_pkts;
300         eth_dev->tx_pkt_burst = &vmxnet3_xmit_pkts;
301         eth_dev->tx_pkt_prepare = vmxnet3_prep_pkts;
302         pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
303
304         /*
305          * for secondary processes, we don't initialize any further as primary
306          * has already done this work.
307          */
308         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
309                 return 0;
310
311         rte_eth_copy_pci_info(eth_dev, pci_dev);
312         eth_dev->data->dev_flags |= RTE_ETH_DEV_DETACHABLE;
313
314         /* Vendor and Device ID need to be set before init of shared code */
315         hw->device_id = pci_dev->id.device_id;
316         hw->vendor_id = pci_dev->id.vendor_id;
317         hw->hw_addr0 = (void *)pci_dev->mem_resource[0].addr;
318         hw->hw_addr1 = (void *)pci_dev->mem_resource[1].addr;
319
320         hw->num_rx_queues = 1;
321         hw->num_tx_queues = 1;
322         hw->bufs_per_pkt = 1;
323
324         /* Check h/w version compatibility with driver. */
325         ver = VMXNET3_READ_BAR1_REG(hw, VMXNET3_REG_VRRS);
326         PMD_INIT_LOG(DEBUG, "Hardware version : %d", ver);
327
328         if (ver & (1 << VMXNET3_REV_3)) {
329                 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_VRRS,
330                                        1 << VMXNET3_REV_3);
331                 hw->version = VMXNET3_REV_3 + 1;
332         } else if (ver & (1 << VMXNET3_REV_2)) {
333                 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_VRRS,
334                                        1 << VMXNET3_REV_2);
335                 hw->version = VMXNET3_REV_2 + 1;
336         } else if (ver & (1 << VMXNET3_REV_1)) {
337                 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_VRRS,
338                                        1 << VMXNET3_REV_1);
339                 hw->version = VMXNET3_REV_1 + 1;
340         } else {
341                 PMD_INIT_LOG(ERR, "Incompatible hardware version: %d", ver);
342                 return -EIO;
343         }
344
345         PMD_INIT_LOG(DEBUG, "Using device version %d\n", hw->version);
346
347         /* Check UPT version compatibility with driver. */
348         ver = VMXNET3_READ_BAR1_REG(hw, VMXNET3_REG_UVRS);
349         PMD_INIT_LOG(DEBUG, "UPT hardware version : %d", ver);
350         if (ver & 0x1)
351                 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_UVRS, 1);
352         else {
353                 PMD_INIT_LOG(ERR, "Incompatible UPT version.");
354                 return -EIO;
355         }
356
357         /* Getting MAC Address */
358         mac_lo = VMXNET3_READ_BAR1_REG(hw, VMXNET3_REG_MACL);
359         mac_hi = VMXNET3_READ_BAR1_REG(hw, VMXNET3_REG_MACH);
360         memcpy(hw->perm_addr, &mac_lo, 4);
361         memcpy(hw->perm_addr + 4, &mac_hi, 2);
362
363         /* Allocate memory for storing MAC addresses */
364         eth_dev->data->mac_addrs = rte_zmalloc("vmxnet3", ETHER_ADDR_LEN *
365                                                VMXNET3_MAX_MAC_ADDRS, 0);
366         if (eth_dev->data->mac_addrs == NULL) {
367                 PMD_INIT_LOG(ERR,
368                              "Failed to allocate %d bytes needed to store MAC addresses",
369                              ETHER_ADDR_LEN * VMXNET3_MAX_MAC_ADDRS);
370                 return -ENOMEM;
371         }
372         /* Copy the permanent MAC address */
373         ether_addr_copy((struct ether_addr *) hw->perm_addr,
374                         &eth_dev->data->mac_addrs[0]);
375
376         PMD_INIT_LOG(DEBUG, "MAC Address : %02x:%02x:%02x:%02x:%02x:%02x",
377                      hw->perm_addr[0], hw->perm_addr[1], hw->perm_addr[2],
378                      hw->perm_addr[3], hw->perm_addr[4], hw->perm_addr[5]);
379
380         /* Put device in Quiesce Mode */
381         VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, VMXNET3_CMD_QUIESCE_DEV);
382
383         /* allow untagged pkts */
384         VMXNET3_SET_VFTABLE_ENTRY(hw->shadow_vfta, 0);
385
386         hw->txdata_desc_size = VMXNET3_VERSION_GE_3(hw) ?
387                 eth_vmxnet3_txdata_get(hw) : sizeof(struct Vmxnet3_TxDataDesc);
388
389         hw->rxdata_desc_size = VMXNET3_VERSION_GE_3(hw) ?
390                 VMXNET3_DEF_RXDATA_DESC_SIZE : 0;
391         RTE_ASSERT((hw->rxdata_desc_size & ~VMXNET3_RXDATA_DESC_SIZE_MASK) ==
392                    hw->rxdata_desc_size);
393
394         /* clear shadow stats */
395         memset(hw->saved_tx_stats, 0, sizeof(hw->saved_tx_stats));
396         memset(hw->saved_rx_stats, 0, sizeof(hw->saved_rx_stats));
397
398         return 0;
399 }
400
401 static int
402 eth_vmxnet3_dev_uninit(struct rte_eth_dev *eth_dev)
403 {
404         struct vmxnet3_hw *hw = eth_dev->data->dev_private;
405
406         PMD_INIT_FUNC_TRACE();
407
408         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
409                 return 0;
410
411         if (hw->adapter_stopped == 0)
412                 vmxnet3_dev_close(eth_dev);
413
414         eth_dev->dev_ops = NULL;
415         eth_dev->rx_pkt_burst = NULL;
416         eth_dev->tx_pkt_burst = NULL;
417         eth_dev->tx_pkt_prepare = NULL;
418
419         rte_free(eth_dev->data->mac_addrs);
420         eth_dev->data->mac_addrs = NULL;
421
422         return 0;
423 }
424
425 static int eth_vmxnet3_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
426         struct rte_pci_device *pci_dev)
427 {
428         return rte_eth_dev_pci_generic_probe(pci_dev,
429                 sizeof(struct vmxnet3_hw), eth_vmxnet3_dev_init);
430 }
431
432 static int eth_vmxnet3_pci_remove(struct rte_pci_device *pci_dev)
433 {
434         return rte_eth_dev_pci_generic_remove(pci_dev, eth_vmxnet3_dev_uninit);
435 }
436
437 static struct rte_pci_driver rte_vmxnet3_pmd = {
438         .id_table = pci_id_vmxnet3_map,
439         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
440         .probe = eth_vmxnet3_pci_probe,
441         .remove = eth_vmxnet3_pci_remove,
442 };
443
444 static int
445 vmxnet3_dev_configure(struct rte_eth_dev *dev)
446 {
447         const struct rte_memzone *mz;
448         struct vmxnet3_hw *hw = dev->data->dev_private;
449         size_t size;
450
451         PMD_INIT_FUNC_TRACE();
452
453         if (dev->data->nb_tx_queues > VMXNET3_MAX_TX_QUEUES ||
454             dev->data->nb_rx_queues > VMXNET3_MAX_RX_QUEUES) {
455                 PMD_INIT_LOG(ERR, "ERROR: Number of queues not supported");
456                 return -EINVAL;
457         }
458
459         if (!rte_is_power_of_2(dev->data->nb_rx_queues)) {
460                 PMD_INIT_LOG(ERR, "ERROR: Number of rx queues not power of 2");
461                 return -EINVAL;
462         }
463
464         size = dev->data->nb_rx_queues * sizeof(struct Vmxnet3_TxQueueDesc) +
465                 dev->data->nb_tx_queues * sizeof(struct Vmxnet3_RxQueueDesc);
466
467         if (size > UINT16_MAX)
468                 return -EINVAL;
469
470         hw->num_rx_queues = (uint8_t)dev->data->nb_rx_queues;
471         hw->num_tx_queues = (uint8_t)dev->data->nb_tx_queues;
472
473         /*
474          * Allocate a memzone for Vmxnet3_DriverShared - Vmxnet3_DSDevRead
475          * on current socket
476          */
477         mz = gpa_zone_reserve(dev, sizeof(struct Vmxnet3_DriverShared),
478                               "shared", rte_socket_id(), 8, 1);
479
480         if (mz == NULL) {
481                 PMD_INIT_LOG(ERR, "ERROR: Creating shared zone");
482                 return -ENOMEM;
483         }
484         memset(mz->addr, 0, mz->len);
485
486         hw->shared = mz->addr;
487         hw->sharedPA = mz->phys_addr;
488
489         /*
490          * Allocate a memzone for Vmxnet3_RxQueueDesc - Vmxnet3_TxQueueDesc
491          * on current socket.
492          *
493          * We cannot reuse this memzone from previous allocation as its size
494          * depends on the number of tx and rx queues, which could be different
495          * from one config to another.
496          */
497         mz = gpa_zone_reserve(dev, size, "queuedesc", rte_socket_id(),
498                               VMXNET3_QUEUE_DESC_ALIGN, 0);
499         if (mz == NULL) {
500                 PMD_INIT_LOG(ERR, "ERROR: Creating queue descriptors zone");
501                 return -ENOMEM;
502         }
503         memset(mz->addr, 0, mz->len);
504
505         hw->tqd_start = (Vmxnet3_TxQueueDesc *)mz->addr;
506         hw->rqd_start = (Vmxnet3_RxQueueDesc *)(hw->tqd_start + hw->num_tx_queues);
507
508         hw->queueDescPA = mz->phys_addr;
509         hw->queue_desc_len = (uint16_t)size;
510
511         if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_RSS) {
512                 /* Allocate memory structure for UPT1_RSSConf and configure */
513                 mz = gpa_zone_reserve(dev, sizeof(struct VMXNET3_RSSConf),
514                                       "rss_conf", rte_socket_id(),
515                                       RTE_CACHE_LINE_SIZE, 1);
516                 if (mz == NULL) {
517                         PMD_INIT_LOG(ERR,
518                                      "ERROR: Creating rss_conf structure zone");
519                         return -ENOMEM;
520                 }
521                 memset(mz->addr, 0, mz->len);
522
523                 hw->rss_conf = mz->addr;
524                 hw->rss_confPA = mz->phys_addr;
525         }
526
527         return 0;
528 }
529
530 static void
531 vmxnet3_write_mac(struct vmxnet3_hw *hw, const uint8_t *addr)
532 {
533         uint32_t val;
534
535         PMD_INIT_LOG(DEBUG,
536                      "Writing MAC Address : %02x:%02x:%02x:%02x:%02x:%02x",
537                      addr[0], addr[1], addr[2],
538                      addr[3], addr[4], addr[5]);
539
540         memcpy(&val, addr, 4);
541         VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_MACL, val);
542
543         memcpy(&val, addr + 4, 2);
544         VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_MACH, val);
545 }
546
547 static int
548 vmxnet3_dev_setup_memreg(struct rte_eth_dev *dev)
549 {
550         struct vmxnet3_hw *hw = dev->data->dev_private;
551         Vmxnet3_DriverShared *shared = hw->shared;
552         Vmxnet3_CmdInfo *cmdInfo;
553         struct rte_mempool *mp[VMXNET3_MAX_RX_QUEUES];
554         uint8_t index[VMXNET3_MAX_RX_QUEUES + VMXNET3_MAX_TX_QUEUES];
555         uint32_t num, i, j, size;
556
557         if (hw->memRegsPA == 0) {
558                 const struct rte_memzone *mz;
559
560                 size = sizeof(Vmxnet3_MemRegs) +
561                         (VMXNET3_MAX_RX_QUEUES + VMXNET3_MAX_TX_QUEUES) *
562                         sizeof(Vmxnet3_MemoryRegion);
563
564                 mz = gpa_zone_reserve(dev, size, "memRegs", rte_socket_id(), 8,
565                                       1);
566                 if (mz == NULL) {
567                         PMD_INIT_LOG(ERR, "ERROR: Creating memRegs zone");
568                         return -ENOMEM;
569                 }
570                 memset(mz->addr, 0, mz->len);
571                 hw->memRegs = mz->addr;
572                 hw->memRegsPA = mz->phys_addr;
573         }
574
575         num = hw->num_rx_queues;
576
577         for (i = 0; i < num; i++) {
578                 vmxnet3_rx_queue_t *rxq = dev->data->rx_queues[i];
579
580                 mp[i] = rxq->mp;
581                 index[i] = 1 << i;
582         }
583
584         /*
585          * The same mempool could be used by multiple queues. In such a case,
586          * remove duplicate mempool entries. Only one entry is kept with
587          * bitmask indicating queues that are using this mempool.
588          */
589         for (i = 1; i < num; i++) {
590                 for (j = 0; j < i; j++) {
591                         if (mp[i] == mp[j]) {
592                                 mp[i] = NULL;
593                                 index[j] |= 1 << i;
594                                 break;
595                         }
596                 }
597         }
598
599         j = 0;
600         for (i = 0; i < num; i++) {
601                 if (mp[i] == NULL)
602                         continue;
603
604                 Vmxnet3_MemoryRegion *mr = &hw->memRegs->memRegs[j];
605
606                 mr->startPA =
607                         (uintptr_t)STAILQ_FIRST(&mp[i]->mem_list)->phys_addr;
608                 mr->length = STAILQ_FIRST(&mp[i]->mem_list)->len <= INT32_MAX ?
609                         STAILQ_FIRST(&mp[i]->mem_list)->len : INT32_MAX;
610                 mr->txQueueBits = index[i];
611                 mr->rxQueueBits = index[i];
612
613                 PMD_INIT_LOG(INFO,
614                              "index: %u startPA: %" PRIu64 " length: %u, "
615                              "rxBits: %x",
616                              j, mr->startPA, mr->length, mr->rxQueueBits);
617                 j++;
618         }
619         hw->memRegs->numRegs = j;
620         PMD_INIT_LOG(INFO, "numRegs: %u", j);
621
622         size = sizeof(Vmxnet3_MemRegs) +
623                 (j - 1) * sizeof(Vmxnet3_MemoryRegion);
624
625         cmdInfo = &shared->cu.cmdInfo;
626         cmdInfo->varConf.confVer = 1;
627         cmdInfo->varConf.confLen = size;
628         cmdInfo->varConf.confPA = hw->memRegsPA;
629
630         return 0;
631 }
632
633 static int
634 vmxnet3_setup_driver_shared(struct rte_eth_dev *dev)
635 {
636         struct rte_eth_conf port_conf = dev->data->dev_conf;
637         struct vmxnet3_hw *hw = dev->data->dev_private;
638         uint32_t mtu = dev->data->mtu;
639         Vmxnet3_DriverShared *shared = hw->shared;
640         Vmxnet3_DSDevRead *devRead = &shared->devRead;
641         uint32_t i;
642         int ret;
643
644         shared->magic = VMXNET3_REV1_MAGIC;
645         devRead->misc.driverInfo.version = VMXNET3_DRIVER_VERSION_NUM;
646
647         /* Setting up Guest OS information */
648         devRead->misc.driverInfo.gos.gosBits   = sizeof(void *) == 4 ?
649                 VMXNET3_GOS_BITS_32 : VMXNET3_GOS_BITS_64;
650         devRead->misc.driverInfo.gos.gosType   = VMXNET3_GOS_TYPE_LINUX;
651         devRead->misc.driverInfo.vmxnet3RevSpt = 1;
652         devRead->misc.driverInfo.uptVerSpt     = 1;
653
654         devRead->misc.mtu = rte_le_to_cpu_32(mtu);
655         devRead->misc.queueDescPA  = hw->queueDescPA;
656         devRead->misc.queueDescLen = hw->queue_desc_len;
657         devRead->misc.numTxQueues  = hw->num_tx_queues;
658         devRead->misc.numRxQueues  = hw->num_rx_queues;
659
660         /*
661          * Set number of interrupts to 1
662          * PMD by default disables all the interrupts but this is MUST
663          * to activate device. It needs at least one interrupt for
664          * link events to handle
665          */
666         hw->num_intrs = devRead->intrConf.numIntrs = 1;
667         devRead->intrConf.intrCtrl |= VMXNET3_IC_DISABLE_ALL;
668
669         for (i = 0; i < hw->num_tx_queues; i++) {
670                 Vmxnet3_TxQueueDesc *tqd = &hw->tqd_start[i];
671                 vmxnet3_tx_queue_t *txq  = dev->data->tx_queues[i];
672
673                 tqd->ctrl.txNumDeferred  = 0;
674                 tqd->ctrl.txThreshold    = 1;
675                 tqd->conf.txRingBasePA   = txq->cmd_ring.basePA;
676                 tqd->conf.compRingBasePA = txq->comp_ring.basePA;
677                 tqd->conf.dataRingBasePA = txq->data_ring.basePA;
678
679                 tqd->conf.txRingSize   = txq->cmd_ring.size;
680                 tqd->conf.compRingSize = txq->comp_ring.size;
681                 tqd->conf.dataRingSize = txq->data_ring.size;
682                 tqd->conf.txDataRingDescSize = txq->txdata_desc_size;
683                 tqd->conf.intrIdx      = txq->comp_ring.intr_idx;
684                 tqd->status.stopped    = TRUE;
685                 tqd->status.error      = 0;
686                 memset(&tqd->stats, 0, sizeof(tqd->stats));
687         }
688
689         for (i = 0; i < hw->num_rx_queues; i++) {
690                 Vmxnet3_RxQueueDesc *rqd  = &hw->rqd_start[i];
691                 vmxnet3_rx_queue_t *rxq   = dev->data->rx_queues[i];
692
693                 rqd->conf.rxRingBasePA[0] = rxq->cmd_ring[0].basePA;
694                 rqd->conf.rxRingBasePA[1] = rxq->cmd_ring[1].basePA;
695                 rqd->conf.compRingBasePA  = rxq->comp_ring.basePA;
696
697                 rqd->conf.rxRingSize[0]   = rxq->cmd_ring[0].size;
698                 rqd->conf.rxRingSize[1]   = rxq->cmd_ring[1].size;
699                 rqd->conf.compRingSize    = rxq->comp_ring.size;
700                 rqd->conf.intrIdx         = rxq->comp_ring.intr_idx;
701                 if (VMXNET3_VERSION_GE_3(hw)) {
702                         rqd->conf.rxDataRingBasePA = rxq->data_ring.basePA;
703                         rqd->conf.rxDataRingDescSize = rxq->data_desc_size;
704                 }
705                 rqd->status.stopped       = TRUE;
706                 rqd->status.error         = 0;
707                 memset(&rqd->stats, 0, sizeof(rqd->stats));
708         }
709
710         /* RxMode set to 0 of VMXNET3_RXM_xxx */
711         devRead->rxFilterConf.rxMode = 0;
712
713         /* Setting up feature flags */
714         if (dev->data->dev_conf.rxmode.hw_ip_checksum)
715                 devRead->misc.uptFeatures |= VMXNET3_F_RXCSUM;
716
717         if (dev->data->dev_conf.rxmode.enable_lro) {
718                 devRead->misc.uptFeatures |= VMXNET3_F_LRO;
719                 devRead->misc.maxNumRxSG = 0;
720         }
721
722         if (port_conf.rxmode.mq_mode == ETH_MQ_RX_RSS) {
723                 ret = vmxnet3_rss_configure(dev);
724                 if (ret != VMXNET3_SUCCESS)
725                         return ret;
726
727                 devRead->misc.uptFeatures |= VMXNET3_F_RSS;
728                 devRead->rssConfDesc.confVer = 1;
729                 devRead->rssConfDesc.confLen = sizeof(struct VMXNET3_RSSConf);
730                 devRead->rssConfDesc.confPA  = hw->rss_confPA;
731         }
732
733         vmxnet3_dev_vlan_offload_set(dev,
734                                      ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK);
735
736         vmxnet3_write_mac(hw, dev->data->mac_addrs->addr_bytes);
737
738         return VMXNET3_SUCCESS;
739 }
740
741 /*
742  * Configure device link speed and setup link.
743  * Must be called after eth_vmxnet3_dev_init. Other wise it might fail
744  * It returns 0 on success.
745  */
746 static int
747 vmxnet3_dev_start(struct rte_eth_dev *dev)
748 {
749         int ret;
750         struct vmxnet3_hw *hw = dev->data->dev_private;
751
752         PMD_INIT_FUNC_TRACE();
753
754         /* Save stats before it is reset by CMD_ACTIVATE */
755         vmxnet3_hw_stats_save(hw);
756
757         ret = vmxnet3_setup_driver_shared(dev);
758         if (ret != VMXNET3_SUCCESS)
759                 return ret;
760
761         /* check if lsc interrupt feature is enabled */
762         if (dev->data->dev_conf.intr_conf.lsc) {
763                 struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev->device);
764
765                 /* Setup interrupt callback  */
766                 rte_intr_callback_register(&pci_dev->intr_handle,
767                                            vmxnet3_interrupt_handler, dev);
768
769                 if (rte_intr_enable(&pci_dev->intr_handle) < 0) {
770                         PMD_INIT_LOG(ERR, "interrupt enable failed");
771                         return -EIO;
772                 }
773         }
774
775         /* Exchange shared data with device */
776         VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_DSAL,
777                                VMXNET3_GET_ADDR_LO(hw->sharedPA));
778         VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_DSAH,
779                                VMXNET3_GET_ADDR_HI(hw->sharedPA));
780
781         /* Activate device by register write */
782         VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, VMXNET3_CMD_ACTIVATE_DEV);
783         ret = VMXNET3_READ_BAR1_REG(hw, VMXNET3_REG_CMD);
784
785         if (ret != 0) {
786                 PMD_INIT_LOG(ERR, "Device activation: UNSUCCESSFUL");
787                 return -EINVAL;
788         }
789
790         /* Setup memory region for rx buffers */
791         ret = vmxnet3_dev_setup_memreg(dev);
792         if (ret == 0) {
793                 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD,
794                                        VMXNET3_CMD_REGISTER_MEMREGS);
795                 ret = VMXNET3_READ_BAR1_REG(hw, VMXNET3_REG_CMD);
796                 if (ret != 0)
797                         PMD_INIT_LOG(DEBUG,
798                                      "Failed in setup memory region cmd\n");
799                 ret = 0;
800         } else {
801                 PMD_INIT_LOG(DEBUG, "Failed to setup memory region\n");
802         }
803
804         /* Disable interrupts */
805         vmxnet3_disable_intr(hw);
806
807         /*
808          * Load RX queues with blank mbufs and update next2fill index for device
809          * Update RxMode of the device
810          */
811         ret = vmxnet3_dev_rxtx_init(dev);
812         if (ret != VMXNET3_SUCCESS) {
813                 PMD_INIT_LOG(ERR, "Device queue init: UNSUCCESSFUL");
814                 return ret;
815         }
816
817         hw->adapter_stopped = FALSE;
818
819         /* Setting proper Rx Mode and issue Rx Mode Update command */
820         vmxnet3_dev_set_rxmode(hw, VMXNET3_RXM_UCAST | VMXNET3_RXM_BCAST, 1);
821
822         if (dev->data->dev_conf.intr_conf.lsc) {
823                 vmxnet3_enable_intr(hw);
824
825                 /*
826                  * Update link state from device since this won't be
827                  * done upon starting with lsc in use. This is done
828                  * only after enabling interrupts to avoid any race
829                  * where the link state could change without an
830                  * interrupt being fired.
831                  */
832                 __vmxnet3_dev_link_update(dev, 0);
833         }
834
835         return VMXNET3_SUCCESS;
836 }
837
838 /*
839  * Stop device: disable rx and tx functions to allow for reconfiguring.
840  */
841 static void
842 vmxnet3_dev_stop(struct rte_eth_dev *dev)
843 {
844         struct rte_eth_link link;
845         struct vmxnet3_hw *hw = dev->data->dev_private;
846
847         PMD_INIT_FUNC_TRACE();
848
849         if (hw->adapter_stopped == 1) {
850                 PMD_INIT_LOG(DEBUG, "Device already closed.");
851                 return;
852         }
853
854         /* disable interrupts */
855         vmxnet3_disable_intr(hw);
856
857         if (dev->data->dev_conf.intr_conf.lsc) {
858                 struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev->device);
859
860                 rte_intr_disable(&pci_dev->intr_handle);
861
862                 rte_intr_callback_unregister(&pci_dev->intr_handle,
863                                              vmxnet3_interrupt_handler, dev);
864         }
865
866         /* quiesce the device first */
867         VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, VMXNET3_CMD_QUIESCE_DEV);
868         VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_DSAL, 0);
869         VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_DSAH, 0);
870
871         /* reset the device */
872         VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, VMXNET3_CMD_RESET_DEV);
873         PMD_INIT_LOG(DEBUG, "Device reset.");
874         hw->adapter_stopped = 0;
875
876         vmxnet3_dev_clear_queues(dev);
877
878         /* Clear recorded link status */
879         memset(&link, 0, sizeof(link));
880         vmxnet3_dev_atomic_write_link_status(dev, &link);
881 }
882
883 /*
884  * Reset and stop device.
885  */
886 static void
887 vmxnet3_dev_close(struct rte_eth_dev *dev)
888 {
889         struct vmxnet3_hw *hw = dev->data->dev_private;
890
891         PMD_INIT_FUNC_TRACE();
892
893         vmxnet3_dev_stop(dev);
894         hw->adapter_stopped = 1;
895 }
896
897 static void
898 vmxnet3_hw_tx_stats_get(struct vmxnet3_hw *hw, unsigned int q,
899                         struct UPT1_TxStats *res)
900 {
901 #define VMXNET3_UPDATE_TX_STAT(h, i, f, r)              \
902                 ((r)->f = (h)->tqd_start[(i)].stats.f + \
903                         (h)->saved_tx_stats[(i)].f)
904
905         VMXNET3_UPDATE_TX_STAT(hw, q, ucastPktsTxOK, res);
906         VMXNET3_UPDATE_TX_STAT(hw, q, mcastPktsTxOK, res);
907         VMXNET3_UPDATE_TX_STAT(hw, q, bcastPktsTxOK, res);
908         VMXNET3_UPDATE_TX_STAT(hw, q, ucastBytesTxOK, res);
909         VMXNET3_UPDATE_TX_STAT(hw, q, mcastBytesTxOK, res);
910         VMXNET3_UPDATE_TX_STAT(hw, q, bcastBytesTxOK, res);
911         VMXNET3_UPDATE_TX_STAT(hw, q, pktsTxError, res);
912         VMXNET3_UPDATE_TX_STAT(hw, q, pktsTxDiscard, res);
913
914 #undef VMXNET3_UPDATE_TX_STAT
915 }
916
917 static void
918 vmxnet3_hw_rx_stats_get(struct vmxnet3_hw *hw, unsigned int q,
919                         struct UPT1_RxStats *res)
920 {
921 #define VMXNET3_UPDATE_RX_STAT(h, i, f, r)              \
922                 ((r)->f = (h)->rqd_start[(i)].stats.f + \
923                         (h)->saved_rx_stats[(i)].f)
924
925         VMXNET3_UPDATE_RX_STAT(hw, q, ucastPktsRxOK, res);
926         VMXNET3_UPDATE_RX_STAT(hw, q, mcastPktsRxOK, res);
927         VMXNET3_UPDATE_RX_STAT(hw, q, bcastPktsRxOK, res);
928         VMXNET3_UPDATE_RX_STAT(hw, q, ucastBytesRxOK, res);
929         VMXNET3_UPDATE_RX_STAT(hw, q, mcastBytesRxOK, res);
930         VMXNET3_UPDATE_RX_STAT(hw, q, bcastBytesRxOK, res);
931         VMXNET3_UPDATE_RX_STAT(hw, q, pktsRxError, res);
932         VMXNET3_UPDATE_RX_STAT(hw, q, pktsRxOutOfBuf, res);
933
934 #undef VMXNET3_UPDATE_RX_STATS
935 }
936
937 static void
938 vmxnet3_hw_stats_save(struct vmxnet3_hw *hw)
939 {
940         unsigned int i;
941
942         VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, VMXNET3_CMD_GET_STATS);
943
944         RTE_BUILD_BUG_ON(RTE_ETHDEV_QUEUE_STAT_CNTRS < VMXNET3_MAX_TX_QUEUES);
945
946         for (i = 0; i < hw->num_tx_queues; i++)
947                 vmxnet3_hw_tx_stats_get(hw, i, &hw->saved_tx_stats[i]);
948         for (i = 0; i < hw->num_rx_queues; i++)
949                 vmxnet3_hw_rx_stats_get(hw, i, &hw->saved_rx_stats[i]);
950 }
951
952 static int
953 vmxnet3_dev_xstats_get_names(struct rte_eth_dev *dev,
954                              struct rte_eth_xstat_name *xstats_names,
955                              unsigned int n)
956 {
957         unsigned int i, t, count = 0;
958         unsigned int nstats =
959                 dev->data->nb_tx_queues * RTE_DIM(vmxnet3_txq_stat_strings) +
960                 dev->data->nb_rx_queues * RTE_DIM(vmxnet3_rxq_stat_strings);
961
962         if (!xstats_names || n < nstats)
963                 return nstats;
964
965         for (i = 0; i < dev->data->nb_rx_queues; i++) {
966                 if (!dev->data->rx_queues[i])
967                         continue;
968
969                 for (t = 0; t < RTE_DIM(vmxnet3_rxq_stat_strings); t++) {
970                         snprintf(xstats_names[count].name,
971                                  sizeof(xstats_names[count].name),
972                                  "rx_q%u_%s", i,
973                                  vmxnet3_rxq_stat_strings[t].name);
974                         count++;
975                 }
976         }
977
978         for (i = 0; i < dev->data->nb_tx_queues; i++) {
979                 if (!dev->data->tx_queues[i])
980                         continue;
981
982                 for (t = 0; t < RTE_DIM(vmxnet3_txq_stat_strings); t++) {
983                         snprintf(xstats_names[count].name,
984                                  sizeof(xstats_names[count].name),
985                                  "tx_q%u_%s", i,
986                                  vmxnet3_txq_stat_strings[t].name);
987                         count++;
988                 }
989         }
990
991         return count;
992 }
993
994 static int
995 vmxnet3_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
996                        unsigned int n)
997 {
998         unsigned int i, t, count = 0;
999         unsigned int nstats =
1000                 dev->data->nb_tx_queues * RTE_DIM(vmxnet3_txq_stat_strings) +
1001                 dev->data->nb_rx_queues * RTE_DIM(vmxnet3_rxq_stat_strings);
1002
1003         if (n < nstats)
1004                 return nstats;
1005
1006         for (i = 0; i < dev->data->nb_rx_queues; i++) {
1007                 struct vmxnet3_rx_queue *rxq = dev->data->rx_queues[i];
1008
1009                 if (rxq == NULL)
1010                         continue;
1011
1012                 for (t = 0; t < RTE_DIM(vmxnet3_rxq_stat_strings); t++) {
1013                         xstats[count].value = *(uint64_t *)(((char *)&rxq->stats) +
1014                                 vmxnet3_rxq_stat_strings[t].offset);
1015                         xstats[count].id = count;
1016                         count++;
1017                 }
1018         }
1019
1020         for (i = 0; i < dev->data->nb_tx_queues; i++) {
1021                 struct vmxnet3_tx_queue *txq = dev->data->tx_queues[i];
1022
1023                 if (txq == NULL)
1024                         continue;
1025
1026                 for (t = 0; t < RTE_DIM(vmxnet3_txq_stat_strings); t++) {
1027                         xstats[count].value = *(uint64_t *)(((char *)&txq->stats) +
1028                                 vmxnet3_txq_stat_strings[t].offset);
1029                         xstats[count].id = count;
1030                         count++;
1031                 }
1032         }
1033
1034         return count;
1035 }
1036
1037 static void
1038 vmxnet3_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
1039 {
1040         unsigned int i;
1041         struct vmxnet3_hw *hw = dev->data->dev_private;
1042         struct UPT1_TxStats txStats;
1043         struct UPT1_RxStats rxStats;
1044
1045         VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, VMXNET3_CMD_GET_STATS);
1046
1047         RTE_BUILD_BUG_ON(RTE_ETHDEV_QUEUE_STAT_CNTRS < VMXNET3_MAX_TX_QUEUES);
1048         for (i = 0; i < hw->num_tx_queues; i++) {
1049                 vmxnet3_hw_tx_stats_get(hw, i, &txStats);
1050
1051                 stats->q_opackets[i] = txStats.ucastPktsTxOK +
1052                         txStats.mcastPktsTxOK +
1053                         txStats.bcastPktsTxOK;
1054
1055                 stats->q_obytes[i] = txStats.ucastBytesTxOK +
1056                         txStats.mcastBytesTxOK +
1057                         txStats.bcastBytesTxOK;
1058
1059                 stats->opackets += stats->q_opackets[i];
1060                 stats->obytes += stats->q_obytes[i];
1061                 stats->oerrors += txStats.pktsTxError + txStats.pktsTxDiscard;
1062         }
1063
1064         RTE_BUILD_BUG_ON(RTE_ETHDEV_QUEUE_STAT_CNTRS < VMXNET3_MAX_RX_QUEUES);
1065         for (i = 0; i < hw->num_rx_queues; i++) {
1066                 vmxnet3_hw_rx_stats_get(hw, i, &rxStats);
1067
1068                 stats->q_ipackets[i] = rxStats.ucastPktsRxOK +
1069                         rxStats.mcastPktsRxOK +
1070                         rxStats.bcastPktsRxOK;
1071
1072                 stats->q_ibytes[i] = rxStats.ucastBytesRxOK +
1073                         rxStats.mcastBytesRxOK +
1074                         rxStats.bcastBytesRxOK;
1075
1076                 stats->ipackets += stats->q_ipackets[i];
1077                 stats->ibytes += stats->q_ibytes[i];
1078
1079                 stats->q_errors[i] = rxStats.pktsRxError;
1080                 stats->ierrors += rxStats.pktsRxError;
1081                 stats->rx_nombuf += rxStats.pktsRxOutOfBuf;
1082         }
1083 }
1084
1085 static void
1086 vmxnet3_dev_info_get(struct rte_eth_dev *dev,
1087                      struct rte_eth_dev_info *dev_info)
1088 {
1089         dev_info->pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1090
1091         dev_info->max_rx_queues = VMXNET3_MAX_RX_QUEUES;
1092         dev_info->max_tx_queues = VMXNET3_MAX_TX_QUEUES;
1093         dev_info->min_rx_bufsize = 1518 + RTE_PKTMBUF_HEADROOM;
1094         dev_info->max_rx_pktlen = 16384; /* includes CRC, cf MAXFRS register */
1095         dev_info->speed_capa = ETH_LINK_SPEED_10G;
1096         dev_info->max_mac_addrs = VMXNET3_MAX_MAC_ADDRS;
1097
1098         dev_info->default_txconf.txq_flags = ETH_TXQ_FLAGS_NOXSUMSCTP;
1099         dev_info->flow_type_rss_offloads = VMXNET3_RSS_OFFLOAD_ALL;
1100
1101         dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
1102                 .nb_max = VMXNET3_RX_RING_MAX_SIZE,
1103                 .nb_min = VMXNET3_DEF_RX_RING_SIZE,
1104                 .nb_align = 1,
1105         };
1106
1107         dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
1108                 .nb_max = VMXNET3_TX_RING_MAX_SIZE,
1109                 .nb_min = VMXNET3_DEF_TX_RING_SIZE,
1110                 .nb_align = 1,
1111                 .nb_seg_max = VMXNET3_TX_MAX_SEG,
1112                 .nb_mtu_seg_max = VMXNET3_MAX_TXD_PER_PKT,
1113         };
1114
1115         dev_info->rx_offload_capa =
1116                 DEV_RX_OFFLOAD_VLAN_STRIP |
1117                 DEV_RX_OFFLOAD_UDP_CKSUM |
1118                 DEV_RX_OFFLOAD_TCP_CKSUM |
1119                 DEV_RX_OFFLOAD_TCP_LRO;
1120
1121         dev_info->tx_offload_capa =
1122                 DEV_TX_OFFLOAD_VLAN_INSERT |
1123                 DEV_TX_OFFLOAD_TCP_CKSUM |
1124                 DEV_TX_OFFLOAD_UDP_CKSUM |
1125                 DEV_TX_OFFLOAD_TCP_TSO;
1126 }
1127
1128 static const uint32_t *
1129 vmxnet3_dev_supported_ptypes_get(struct rte_eth_dev *dev)
1130 {
1131         static const uint32_t ptypes[] = {
1132                 RTE_PTYPE_L3_IPV4_EXT,
1133                 RTE_PTYPE_L3_IPV4,
1134                 RTE_PTYPE_UNKNOWN
1135         };
1136
1137         if (dev->rx_pkt_burst == vmxnet3_recv_pkts)
1138                 return ptypes;
1139         return NULL;
1140 }
1141
1142 static void
1143 vmxnet3_mac_addr_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr)
1144 {
1145         struct vmxnet3_hw *hw = dev->data->dev_private;
1146
1147         ether_addr_copy(mac_addr, (struct ether_addr *)(hw->perm_addr));
1148         ether_addr_copy(mac_addr, &dev->data->mac_addrs[0]);
1149         vmxnet3_write_mac(hw, mac_addr->addr_bytes);
1150 }
1151
1152 /* return 0 means link status changed, -1 means not changed */
1153 static int
1154 __vmxnet3_dev_link_update(struct rte_eth_dev *dev,
1155                           __rte_unused int wait_to_complete)
1156 {
1157         struct vmxnet3_hw *hw = dev->data->dev_private;
1158         struct rte_eth_link old = { 0 }, link;
1159         uint32_t ret;
1160
1161         memset(&link, 0, sizeof(link));
1162         vmxnet3_dev_atomic_read_link_status(dev, &old);
1163
1164         VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, VMXNET3_CMD_GET_LINK);
1165         ret = VMXNET3_READ_BAR1_REG(hw, VMXNET3_REG_CMD);
1166
1167         if (ret & 0x1) {
1168                 link.link_status = ETH_LINK_UP;
1169                 link.link_duplex = ETH_LINK_FULL_DUPLEX;
1170                 link.link_speed = ETH_SPEED_NUM_10G;
1171                 link.link_autoneg = ETH_LINK_SPEED_FIXED;
1172         }
1173
1174         vmxnet3_dev_atomic_write_link_status(dev, &link);
1175
1176         return (old.link_status == link.link_status) ? -1 : 0;
1177 }
1178
1179 static int
1180 vmxnet3_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
1181 {
1182         /* Link status doesn't change for stopped dev */
1183         if (dev->data->dev_started == 0)
1184                 return -1;
1185
1186         return __vmxnet3_dev_link_update(dev, wait_to_complete);
1187 }
1188
1189 /* Updating rxmode through Vmxnet3_DriverShared structure in adapter */
1190 static void
1191 vmxnet3_dev_set_rxmode(struct vmxnet3_hw *hw, uint32_t feature, int set)
1192 {
1193         struct Vmxnet3_RxFilterConf *rxConf = &hw->shared->devRead.rxFilterConf;
1194
1195         if (set)
1196                 rxConf->rxMode = rxConf->rxMode | feature;
1197         else
1198                 rxConf->rxMode = rxConf->rxMode & (~feature);
1199
1200         VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, VMXNET3_CMD_UPDATE_RX_MODE);
1201 }
1202
1203 /* Promiscuous supported only if Vmxnet3_DriverShared is initialized in adapter */
1204 static void
1205 vmxnet3_dev_promiscuous_enable(struct rte_eth_dev *dev)
1206 {
1207         struct vmxnet3_hw *hw = dev->data->dev_private;
1208         uint32_t *vf_table = hw->shared->devRead.rxFilterConf.vfTable;
1209
1210         memset(vf_table, 0, VMXNET3_VFT_TABLE_SIZE);
1211         vmxnet3_dev_set_rxmode(hw, VMXNET3_RXM_PROMISC, 1);
1212
1213         VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD,
1214                                VMXNET3_CMD_UPDATE_VLAN_FILTERS);
1215 }
1216
1217 /* Promiscuous supported only if Vmxnet3_DriverShared is initialized in adapter */
1218 static void
1219 vmxnet3_dev_promiscuous_disable(struct rte_eth_dev *dev)
1220 {
1221         struct vmxnet3_hw *hw = dev->data->dev_private;
1222         uint32_t *vf_table = hw->shared->devRead.rxFilterConf.vfTable;
1223
1224         if (dev->data->dev_conf.rxmode.hw_vlan_filter)
1225                 memcpy(vf_table, hw->shadow_vfta, VMXNET3_VFT_TABLE_SIZE);
1226         else
1227                 memset(vf_table, 0xff, VMXNET3_VFT_TABLE_SIZE);
1228         vmxnet3_dev_set_rxmode(hw, VMXNET3_RXM_PROMISC, 0);
1229         VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD,
1230                                VMXNET3_CMD_UPDATE_VLAN_FILTERS);
1231 }
1232
1233 /* Allmulticast supported only if Vmxnet3_DriverShared is initialized in adapter */
1234 static void
1235 vmxnet3_dev_allmulticast_enable(struct rte_eth_dev *dev)
1236 {
1237         struct vmxnet3_hw *hw = dev->data->dev_private;
1238
1239         vmxnet3_dev_set_rxmode(hw, VMXNET3_RXM_ALL_MULTI, 1);
1240 }
1241
1242 /* Allmulticast supported only if Vmxnet3_DriverShared is initialized in adapter */
1243 static void
1244 vmxnet3_dev_allmulticast_disable(struct rte_eth_dev *dev)
1245 {
1246         struct vmxnet3_hw *hw = dev->data->dev_private;
1247
1248         vmxnet3_dev_set_rxmode(hw, VMXNET3_RXM_ALL_MULTI, 0);
1249 }
1250
1251 /* Enable/disable filter on vlan */
1252 static int
1253 vmxnet3_dev_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vid, int on)
1254 {
1255         struct vmxnet3_hw *hw = dev->data->dev_private;
1256         struct Vmxnet3_RxFilterConf *rxConf = &hw->shared->devRead.rxFilterConf;
1257         uint32_t *vf_table = rxConf->vfTable;
1258
1259         /* save state for restore */
1260         if (on)
1261                 VMXNET3_SET_VFTABLE_ENTRY(hw->shadow_vfta, vid);
1262         else
1263                 VMXNET3_CLEAR_VFTABLE_ENTRY(hw->shadow_vfta, vid);
1264
1265         /* don't change active filter if in promiscuous mode */
1266         if (rxConf->rxMode & VMXNET3_RXM_PROMISC)
1267                 return 0;
1268
1269         /* set in hardware */
1270         if (on)
1271                 VMXNET3_SET_VFTABLE_ENTRY(vf_table, vid);
1272         else
1273                 VMXNET3_CLEAR_VFTABLE_ENTRY(vf_table, vid);
1274
1275         VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD,
1276                                VMXNET3_CMD_UPDATE_VLAN_FILTERS);
1277         return 0;
1278 }
1279
1280 static void
1281 vmxnet3_dev_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1282 {
1283         struct vmxnet3_hw *hw = dev->data->dev_private;
1284         Vmxnet3_DSDevRead *devRead = &hw->shared->devRead;
1285         uint32_t *vf_table = devRead->rxFilterConf.vfTable;
1286
1287         if (mask & ETH_VLAN_STRIP_MASK) {
1288                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
1289                         devRead->misc.uptFeatures |= UPT1_F_RXVLAN;
1290                 else
1291                         devRead->misc.uptFeatures &= ~UPT1_F_RXVLAN;
1292
1293                 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD,
1294                                        VMXNET3_CMD_UPDATE_FEATURE);
1295         }
1296
1297         if (mask & ETH_VLAN_FILTER_MASK) {
1298                 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
1299                         memcpy(vf_table, hw->shadow_vfta, VMXNET3_VFT_TABLE_SIZE);
1300                 else
1301                         memset(vf_table, 0xff, VMXNET3_VFT_TABLE_SIZE);
1302
1303                 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD,
1304                                        VMXNET3_CMD_UPDATE_VLAN_FILTERS);
1305         }
1306 }
1307
1308 static void
1309 vmxnet3_process_events(struct rte_eth_dev *dev)
1310 {
1311         struct vmxnet3_hw *hw = dev->data->dev_private;
1312         uint32_t events = hw->shared->ecr;
1313
1314         if (!events)
1315                 return;
1316
1317         /*
1318          * ECR bits when written with 1b are cleared. Hence write
1319          * events back to ECR so that the bits which were set will be reset.
1320          */
1321         VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_ECR, events);
1322
1323         /* Check if link state has changed */
1324         if (events & VMXNET3_ECR_LINK) {
1325                 PMD_DRV_LOG(DEBUG, "Process events: VMXNET3_ECR_LINK event");
1326                 if (vmxnet3_dev_link_update(dev, 0) == 0)
1327                         _rte_eth_dev_callback_process(dev,
1328                                                       RTE_ETH_EVENT_INTR_LSC,
1329                                                       NULL, NULL);
1330         }
1331
1332         /* Check if there is an error on xmit/recv queues */
1333         if (events & (VMXNET3_ECR_TQERR | VMXNET3_ECR_RQERR)) {
1334                 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD,
1335                                        VMXNET3_CMD_GET_QUEUE_STATUS);
1336
1337                 if (hw->tqd_start->status.stopped)
1338                         PMD_DRV_LOG(ERR, "tq error 0x%x",
1339                                     hw->tqd_start->status.error);
1340
1341                 if (hw->rqd_start->status.stopped)
1342                         PMD_DRV_LOG(ERR, "rq error 0x%x",
1343                                      hw->rqd_start->status.error);
1344
1345                 /* Reset the device */
1346                 /* Have to reset the device */
1347         }
1348
1349         if (events & VMXNET3_ECR_DIC)
1350                 PMD_DRV_LOG(DEBUG, "Device implementation change event.");
1351
1352         if (events & VMXNET3_ECR_DEBUG)
1353                 PMD_DRV_LOG(DEBUG, "Debug event generated by device.");
1354 }
1355
1356 static void
1357 vmxnet3_interrupt_handler(void *param)
1358 {
1359         struct rte_eth_dev *dev = param;
1360         struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev->device);
1361
1362         vmxnet3_process_events(dev);
1363
1364         if (rte_intr_enable(&pci_dev->intr_handle) < 0)
1365                 PMD_DRV_LOG(ERR, "interrupt enable failed");
1366 }
1367
1368 RTE_PMD_REGISTER_PCI(net_vmxnet3, rte_vmxnet3_pmd);
1369 RTE_PMD_REGISTER_PCI_TABLE(net_vmxnet3, pci_id_vmxnet3_map);
1370 RTE_PMD_REGISTER_KMOD_DEP(net_vmxnet3, "* igb_uio | uio_pci_generic | vfio-pci");