drivers/net/vmxnet3/vmxnet3_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2010-2015 Intel Corporation
   3  */
   4
   5 #include <sys/queue.h>
   6 #include <stdio.h>
   7 #include <errno.h>
   8 #include <stdint.h>
   9 #include <string.h>
  10 #include <unistd.h>
  11 #include <stdarg.h>
  12 #include <fcntl.h>
  13 #include <inttypes.h>
  14 #include <rte_byteorder.h>
  15 #include <rte_common.h>
  16 #include <rte_cycles.h>
  17
  18 #include <rte_interrupts.h>
  19 #include <rte_log.h>
  20 #include <rte_debug.h>
  21 #include <rte_pci.h>
  22 #include <rte_bus_pci.h>
  23 #include <rte_branch_prediction.h>
  24 #include <rte_memory.h>
  25 #include <rte_memzone.h>
  26 #include <rte_eal.h>
  27 #include <rte_alarm.h>
  28 #include <rte_ether.h>
  29 #include <rte_ethdev_driver.h>
  30 #include <rte_ethdev_pci.h>
  31 #include <rte_string_fns.h>
  32 #include <rte_malloc.h>
  33 #include <rte_dev.h>
  34
  35 #include "base/vmxnet3_defs.h"
  36
  37 #include "vmxnet3_ring.h"
  38 #include "vmxnet3_logs.h"
  39 #include "vmxnet3_ethdev.h"
  40
  41 #define PROCESS_SYS_EVENTS 0
  42
  43 #define VMXNET3_TX_MAX_SEG      UINT8_MAX
  44
  45 #define VMXNET3_TX_OFFLOAD_CAP          \
  46         (DEV_TX_OFFLOAD_VLAN_INSERT |   \
  47          DEV_TX_OFFLOAD_TCP_CKSUM |     \
  48          DEV_TX_OFFLOAD_UDP_CKSUM |     \
  49          DEV_TX_OFFLOAD_TCP_TSO |       \
  50          DEV_TX_OFFLOAD_MULTI_SEGS)
  51
  52 #define VMXNET3_RX_OFFLOAD_CAP          \
  53         (DEV_RX_OFFLOAD_VLAN_STRIP |    \
  54          DEV_RX_OFFLOAD_VLAN_FILTER |   \
  55          DEV_RX_OFFLOAD_SCATTER |       \
  56          DEV_RX_OFFLOAD_UDP_CKSUM |     \
  57          DEV_RX_OFFLOAD_TCP_CKSUM |     \
  58          DEV_RX_OFFLOAD_TCP_LRO |       \
  59          DEV_RX_OFFLOAD_JUMBO_FRAME |   \
  60          DEV_RX_OFFLOAD_RSS_HASH)
  61
  62 static int eth_vmxnet3_dev_init(struct rte_eth_dev *eth_dev);
  63 static int eth_vmxnet3_dev_uninit(struct rte_eth_dev *eth_dev);
  64 static int vmxnet3_dev_configure(struct rte_eth_dev *dev);
  65 static int vmxnet3_dev_start(struct rte_eth_dev *dev);
  66 static void vmxnet3_dev_stop(struct rte_eth_dev *dev);
  67 static int vmxnet3_dev_close(struct rte_eth_dev *dev);
  68 static void vmxnet3_dev_set_rxmode(struct vmxnet3_hw *hw, uint32_t feature, int set);
  69 static int vmxnet3_dev_promiscuous_enable(struct rte_eth_dev *dev);
  70 static int vmxnet3_dev_promiscuous_disable(struct rte_eth_dev *dev);
  71 static int vmxnet3_dev_allmulticast_enable(struct rte_eth_dev *dev);
  72 static int vmxnet3_dev_allmulticast_disable(struct rte_eth_dev *dev);
  73 static int __vmxnet3_dev_link_update(struct rte_eth_dev *dev,
  74                                      int wait_to_complete);
  75 static int vmxnet3_dev_link_update(struct rte_eth_dev *dev,
  76                                    int wait_to_complete);
  77 static void vmxnet3_hw_stats_save(struct vmxnet3_hw *hw);
  78 static int vmxnet3_dev_stats_get(struct rte_eth_dev *dev,
  79                                   struct rte_eth_stats *stats);
  80 static int vmxnet3_dev_stats_reset(struct rte_eth_dev *dev);
  81 static int vmxnet3_dev_xstats_get_names(struct rte_eth_dev *dev,
  82                                         struct rte_eth_xstat_name *xstats,
  83                                         unsigned int n);
  84 static int vmxnet3_dev_xstats_get(struct rte_eth_dev *dev,
  85                                   struct rte_eth_xstat *xstats, unsigned int n);
  86 static int vmxnet3_dev_info_get(struct rte_eth_dev *dev,
  87                                 struct rte_eth_dev_info *dev_info);
  88 static const uint32_t *
  89 vmxnet3_dev_supported_ptypes_get(struct rte_eth_dev *dev);
  90 static int vmxnet3_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
  91 static int vmxnet3_dev_vlan_filter_set(struct rte_eth_dev *dev,
  92                                        uint16_t vid, int on);
  93 static int vmxnet3_dev_vlan_offload_set(struct rte_eth_dev *dev, int mask);
  94 static int vmxnet3_mac_addr_set(struct rte_eth_dev *dev,
  95                                  struct rte_ether_addr *mac_addr);
  96 static void vmxnet3_interrupt_handler(void *param);
  97
  98 /*
  99  * The set of PCI devices this driver supports
 100  */
 101 #define VMWARE_PCI_VENDOR_ID 0x15AD
 102 #define VMWARE_DEV_ID_VMXNET3 0x07B0
 103 static const struct rte_pci_id pci_id_vmxnet3_map[] = {
 104         { RTE_PCI_DEVICE(VMWARE_PCI_VENDOR_ID, VMWARE_DEV_ID_VMXNET3) },
 105         { .vendor_id = 0, /* sentinel */ },
 106 };
 107
 108 static const struct eth_dev_ops vmxnet3_eth_dev_ops = {
 109         .dev_configure        = vmxnet3_dev_configure,
 110         .dev_start            = vmxnet3_dev_start,
 111         .dev_stop             = vmxnet3_dev_stop,
 112         .dev_close            = vmxnet3_dev_close,
 113         .promiscuous_enable   = vmxnet3_dev_promiscuous_enable,
 114         .promiscuous_disable  = vmxnet3_dev_promiscuous_disable,
 115         .allmulticast_enable  = vmxnet3_dev_allmulticast_enable,
 116         .allmulticast_disable = vmxnet3_dev_allmulticast_disable,
 117         .link_update          = vmxnet3_dev_link_update,
 118         .stats_get            = vmxnet3_dev_stats_get,
 119         .xstats_get_names     = vmxnet3_dev_xstats_get_names,
 120         .xstats_get           = vmxnet3_dev_xstats_get,
 121         .stats_reset          = vmxnet3_dev_stats_reset,
 122         .mac_addr_set         = vmxnet3_mac_addr_set,
 123         .dev_infos_get        = vmxnet3_dev_info_get,
 124         .dev_supported_ptypes_get = vmxnet3_dev_supported_ptypes_get,
 125         .mtu_set              = vmxnet3_dev_mtu_set,
 126         .vlan_filter_set      = vmxnet3_dev_vlan_filter_set,
 127         .vlan_offload_set     = vmxnet3_dev_vlan_offload_set,
 128         .rx_queue_setup       = vmxnet3_dev_rx_queue_setup,
 129         .rx_queue_release     = vmxnet3_dev_rx_queue_release,
 130         .tx_queue_setup       = vmxnet3_dev_tx_queue_setup,
 131         .tx_queue_release     = vmxnet3_dev_tx_queue_release,
 132 };
 133
 134 struct vmxnet3_xstats_name_off {
 135         char name[RTE_ETH_XSTATS_NAME_SIZE];
 136         unsigned int offset;
 137 };
 138
 139 /* tx_qX_ is prepended to the name string here */
 140 static const struct vmxnet3_xstats_name_off vmxnet3_txq_stat_strings[] = {
 141         {"drop_total",         offsetof(struct vmxnet3_txq_stats, drop_total)},
 142         {"drop_too_many_segs", offsetof(struct vmxnet3_txq_stats, drop_too_many_segs)},
 143         {"drop_tso",           offsetof(struct vmxnet3_txq_stats, drop_tso)},
 144         {"tx_ring_full",       offsetof(struct vmxnet3_txq_stats, tx_ring_full)},
 145 };
 146
 147 /* rx_qX_ is prepended to the name string here */
 148 static const struct vmxnet3_xstats_name_off vmxnet3_rxq_stat_strings[] = {
 149         {"drop_total",           offsetof(struct vmxnet3_rxq_stats, drop_total)},
 150         {"drop_err",             offsetof(struct vmxnet3_rxq_stats, drop_err)},
 151         {"drop_fcs",             offsetof(struct vmxnet3_rxq_stats, drop_fcs)},
 152         {"rx_buf_alloc_failure", offsetof(struct vmxnet3_rxq_stats, rx_buf_alloc_failure)},
 153 };
 154
 155 static const struct rte_memzone *
 156 gpa_zone_reserve(struct rte_eth_dev *dev, uint32_t size,
 157                  const char *post_string, int socket_id,
 158                  uint16_t align, bool reuse)
 159 {
 160         char z_name[RTE_MEMZONE_NAMESIZE];
 161         const struct rte_memzone *mz;
 162
 163         snprintf(z_name, sizeof(z_name), "eth_p%d_%s",
 164                         dev->data->port_id, post_string);
 165
 166         mz = rte_memzone_lookup(z_name);
 167         if (!reuse) {
 168                 if (mz)
 169                         rte_memzone_free(mz);
 170                 return rte_memzone_reserve_aligned(z_name, size, socket_id,
 171                                 RTE_MEMZONE_IOVA_CONTIG, align);
 172         }
 173
 174         if (mz)
 175                 return mz;
 176
 177         return rte_memzone_reserve_aligned(z_name, size, socket_id,
 178                         RTE_MEMZONE_IOVA_CONTIG, align);
 179 }
 180
 181 /*
 182  * This function is based on vmxnet3_disable_intr()
 183  */
 184 static void
 185 vmxnet3_disable_intr(struct vmxnet3_hw *hw)
 186 {
 187         int i;
 188
 189         PMD_INIT_FUNC_TRACE();
 190
 191         hw->shared->devRead.intrConf.intrCtrl |= VMXNET3_IC_DISABLE_ALL;
 192         for (i = 0; i < hw->num_intrs; i++)
 193                 VMXNET3_WRITE_BAR0_REG(hw, VMXNET3_REG_IMR + i * 8, 1);
 194 }
 195
 196 static void
 197 vmxnet3_enable_intr(struct vmxnet3_hw *hw)
 198 {
 199         int i;
 200
 201         PMD_INIT_FUNC_TRACE();
 202
 203         hw->shared->devRead.intrConf.intrCtrl &= ~VMXNET3_IC_DISABLE_ALL;
 204         for (i = 0; i < hw->num_intrs; i++)
 205                 VMXNET3_WRITE_BAR0_REG(hw, VMXNET3_REG_IMR + i * 8, 0);
 206 }
 207
 208 /*
 209  * Gets tx data ring descriptor size.
 210  */
 211 static uint16_t
 212 eth_vmxnet3_txdata_get(struct vmxnet3_hw *hw)
 213 {
 214         uint16 txdata_desc_size;
 215
 216         VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD,
 217                                VMXNET3_CMD_GET_TXDATA_DESC_SIZE);
 218         txdata_desc_size = VMXNET3_READ_BAR1_REG(hw, VMXNET3_REG_CMD);
 219
 220         return (txdata_desc_size < VMXNET3_TXDATA_DESC_MIN_SIZE ||
 221                 txdata_desc_size > VMXNET3_TXDATA_DESC_MAX_SIZE ||
 222                 txdata_desc_size & VMXNET3_TXDATA_DESC_SIZE_MASK) ?
 223                 sizeof(struct Vmxnet3_TxDataDesc) : txdata_desc_size;
 224 }
 225
 226 /*
 227  * It returns 0 on success.
 228  */
 229 static int
 230 eth_vmxnet3_dev_init(struct rte_eth_dev *eth_dev)
 231 {
 232         struct rte_pci_device *pci_dev;
 233         struct vmxnet3_hw *hw = eth_dev->data->dev_private;
 234         uint32_t mac_hi, mac_lo, ver;
 235         struct rte_eth_link link;
 236
 237         PMD_INIT_FUNC_TRACE();
 238
 239         eth_dev->dev_ops = &vmxnet3_eth_dev_ops;
 240         eth_dev->rx_pkt_burst = &vmxnet3_recv_pkts;
 241         eth_dev->tx_pkt_burst = &vmxnet3_xmit_pkts;
 242         eth_dev->tx_pkt_prepare = vmxnet3_prep_pkts;
 243         pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
 244
 245         /*
 246          * for secondary processes, we don't initialize any further as primary
 247          * has already done this work.
 248          */
 249         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
 250                 return 0;
 251
 252         rte_eth_copy_pci_info(eth_dev, pci_dev);
 253
 254         /* Vendor and Device ID need to be set before init of shared code */
 255         hw->device_id = pci_dev->id.device_id;
 256         hw->vendor_id = pci_dev->id.vendor_id;
 257         hw->hw_addr0 = (void *)pci_dev->mem_resource[0].addr;
 258         hw->hw_addr1 = (void *)pci_dev->mem_resource[1].addr;
 259
 260         hw->num_rx_queues = 1;
 261         hw->num_tx_queues = 1;
 262         hw->bufs_per_pkt = 1;
 263
 264         /* Check h/w version compatibility with driver. */
 265         ver = VMXNET3_READ_BAR1_REG(hw, VMXNET3_REG_VRRS);
 266         PMD_INIT_LOG(DEBUG, "Hardware version : %d", ver);
 267
 268         if (ver & (1 << VMXNET3_REV_4)) {
 269                 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_VRRS,
 270                                        1 << VMXNET3_REV_4);
 271                 hw->version = VMXNET3_REV_4 + 1;
 272         } else if (ver & (1 << VMXNET3_REV_3)) {
 273                 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_VRRS,
 274                                        1 << VMXNET3_REV_3);
 275                 hw->version = VMXNET3_REV_3 + 1;
 276         } else if (ver & (1 << VMXNET3_REV_2)) {
 277                 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_VRRS,
 278                                        1 << VMXNET3_REV_2);
 279                 hw->version = VMXNET3_REV_2 + 1;
 280         } else if (ver & (1 << VMXNET3_REV_1)) {
 281                 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_VRRS,
 282                                        1 << VMXNET3_REV_1);
 283                 hw->version = VMXNET3_REV_1 + 1;
 284         } else {
 285                 PMD_INIT_LOG(ERR, "Incompatible hardware version: %d", ver);
 286                 return -EIO;
 287         }
 288
 289         PMD_INIT_LOG(DEBUG, "Using device version %d\n", hw->version);
 290
 291         /* Check UPT version compatibility with driver. */
 292         ver = VMXNET3_READ_BAR1_REG(hw, VMXNET3_REG_UVRS);
 293         PMD_INIT_LOG(DEBUG, "UPT hardware version : %d", ver);
 294         if (ver & 0x1)
 295                 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_UVRS, 1);
 296         else {
 297                 PMD_INIT_LOG(ERR, "Incompatible UPT version.");
 298                 return -EIO;
 299         }
 300
 301         /* Getting MAC Address */
 302         mac_lo = VMXNET3_READ_BAR1_REG(hw, VMXNET3_REG_MACL);
 303         mac_hi = VMXNET3_READ_BAR1_REG(hw, VMXNET3_REG_MACH);
 304         memcpy(hw->perm_addr, &mac_lo, 4);
 305         memcpy(hw->perm_addr + 4, &mac_hi, 2);
 306
 307         /* Allocate memory for storing MAC addresses */
 308         eth_dev->data->mac_addrs = rte_zmalloc("vmxnet3", RTE_ETHER_ADDR_LEN *
 309                                                VMXNET3_MAX_MAC_ADDRS, 0);
 310         if (eth_dev->data->mac_addrs == NULL) {
 311                 PMD_INIT_LOG(ERR,
 312                              "Failed to allocate %d bytes needed to store MAC addresses",
 313                              RTE_ETHER_ADDR_LEN * VMXNET3_MAX_MAC_ADDRS);
 314                 return -ENOMEM;
 315         }
 316         /* Copy the permanent MAC address */
 317         rte_ether_addr_copy((struct rte_ether_addr *)hw->perm_addr,
 318                         &eth_dev->data->mac_addrs[0]);
 319
 320         PMD_INIT_LOG(DEBUG, "MAC Address : %02x:%02x:%02x:%02x:%02x:%02x",
 321                      hw->perm_addr[0], hw->perm_addr[1], hw->perm_addr[2],
 322                      hw->perm_addr[3], hw->perm_addr[4], hw->perm_addr[5]);
 323
 324         /* Put device in Quiesce Mode */
 325         VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, VMXNET3_CMD_QUIESCE_DEV);
 326
 327         /* allow untagged pkts */
 328         VMXNET3_SET_VFTABLE_ENTRY(hw->shadow_vfta, 0);
 329
 330         hw->txdata_desc_size = VMXNET3_VERSION_GE_3(hw) ?
 331                 eth_vmxnet3_txdata_get(hw) : sizeof(struct Vmxnet3_TxDataDesc);
 332
 333         hw->rxdata_desc_size = VMXNET3_VERSION_GE_3(hw) ?
 334                 VMXNET3_DEF_RXDATA_DESC_SIZE : 0;
 335         RTE_ASSERT((hw->rxdata_desc_size & ~VMXNET3_RXDATA_DESC_SIZE_MASK) ==
 336                    hw->rxdata_desc_size);
 337
 338         /* clear shadow stats */
 339         memset(hw->saved_tx_stats, 0, sizeof(hw->saved_tx_stats));
 340         memset(hw->saved_rx_stats, 0, sizeof(hw->saved_rx_stats));
 341
 342         /* clear snapshot stats */
 343         memset(hw->snapshot_tx_stats, 0, sizeof(hw->snapshot_tx_stats));
 344         memset(hw->snapshot_rx_stats, 0, sizeof(hw->snapshot_rx_stats));
 345
 346         /* set the initial link status */
 347         memset(&link, 0, sizeof(link));
 348         link.link_duplex = ETH_LINK_FULL_DUPLEX;
 349         link.link_speed = ETH_SPEED_NUM_10G;
 350         link.link_autoneg = ETH_LINK_FIXED;
 351         rte_eth_linkstatus_set(eth_dev, &link);
 352
 353         return 0;
 354 }
 355
 356 static int
 357 eth_vmxnet3_dev_uninit(struct rte_eth_dev *eth_dev)
 358 {
 359         struct vmxnet3_hw *hw = eth_dev->data->dev_private;
 360
 361         PMD_INIT_FUNC_TRACE();
 362
 363         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
 364                 return 0;
 365
 366         if (hw->adapter_stopped == 0) {
 367                 PMD_INIT_LOG(DEBUG, "Device has not been closed.");
 368                 return -EBUSY;
 369         }
 370
 371         return 0;
 372 }
 373
 374 static int eth_vmxnet3_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
 375         struct rte_pci_device *pci_dev)
 376 {
 377         return rte_eth_dev_pci_generic_probe(pci_dev,
 378                 sizeof(struct vmxnet3_hw), eth_vmxnet3_dev_init);
 379 }
 380
 381 static int eth_vmxnet3_pci_remove(struct rte_pci_device *pci_dev)
 382 {
 383         return rte_eth_dev_pci_generic_remove(pci_dev, eth_vmxnet3_dev_uninit);
 384 }
 385
 386 static struct rte_pci_driver rte_vmxnet3_pmd = {
 387         .id_table = pci_id_vmxnet3_map,
 388         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
 389         .probe = eth_vmxnet3_pci_probe,
 390         .remove = eth_vmxnet3_pci_remove,
 391 };
 392
 393 static int
 394 vmxnet3_dev_configure(struct rte_eth_dev *dev)
 395 {
 396         const struct rte_memzone *mz;
 397         struct vmxnet3_hw *hw = dev->data->dev_private;
 398         size_t size;
 399
 400         PMD_INIT_FUNC_TRACE();
 401
 402         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG)
 403                 dev->data->dev_conf.rxmode.offloads |= DEV_RX_OFFLOAD_RSS_HASH;
 404
 405         if (dev->data->nb_tx_queues > VMXNET3_MAX_TX_QUEUES ||
 406             dev->data->nb_rx_queues > VMXNET3_MAX_RX_QUEUES) {
 407                 PMD_INIT_LOG(ERR, "ERROR: Number of queues not supported");
 408                 return -EINVAL;
 409         }
 410
 411         if (!rte_is_power_of_2(dev->data->nb_rx_queues)) {
 412                 PMD_INIT_LOG(ERR, "ERROR: Number of rx queues not power of 2");
 413                 return -EINVAL;
 414         }
 415
 416         size = dev->data->nb_rx_queues * sizeof(struct Vmxnet3_TxQueueDesc) +
 417                 dev->data->nb_tx_queues * sizeof(struct Vmxnet3_RxQueueDesc);
 418
 419         if (size > UINT16_MAX)
 420                 return -EINVAL;
 421
 422         hw->num_rx_queues = (uint8_t)dev->data->nb_rx_queues;
 423         hw->num_tx_queues = (uint8_t)dev->data->nb_tx_queues;
 424
 425         /*
 426          * Allocate a memzone for Vmxnet3_DriverShared - Vmxnet3_DSDevRead
 427          * on current socket
 428          */
 429         mz = gpa_zone_reserve(dev, sizeof(struct Vmxnet3_DriverShared),
 430                               "shared", rte_socket_id(), 8, 1);
 431
 432         if (mz == NULL) {
 433                 PMD_INIT_LOG(ERR, "ERROR: Creating shared zone");
 434                 return -ENOMEM;
 435         }
 436         memset(mz->addr, 0, mz->len);
 437
 438         hw->shared = mz->addr;
 439         hw->sharedPA = mz->iova;
 440
 441         /*
 442          * Allocate a memzone for Vmxnet3_RxQueueDesc - Vmxnet3_TxQueueDesc
 443          * on current socket.
 444          *
 445          * We cannot reuse this memzone from previous allocation as its size
 446          * depends on the number of tx and rx queues, which could be different
 447          * from one config to another.
 448          */
 449         mz = gpa_zone_reserve(dev, size, "queuedesc", rte_socket_id(),
 450                               VMXNET3_QUEUE_DESC_ALIGN, 0);
 451         if (mz == NULL) {
 452                 PMD_INIT_LOG(ERR, "ERROR: Creating queue descriptors zone");
 453                 return -ENOMEM;
 454         }
 455         memset(mz->addr, 0, mz->len);
 456
 457         hw->tqd_start = (Vmxnet3_TxQueueDesc *)mz->addr;
 458         hw->rqd_start = (Vmxnet3_RxQueueDesc *)(hw->tqd_start + hw->num_tx_queues);
 459
 460         hw->queueDescPA = mz->iova;
 461         hw->queue_desc_len = (uint16_t)size;
 462
 463         if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_RSS) {
 464                 /* Allocate memory structure for UPT1_RSSConf and configure */
 465                 mz = gpa_zone_reserve(dev, sizeof(struct VMXNET3_RSSConf),
 466                                       "rss_conf", rte_socket_id(),
 467                                       RTE_CACHE_LINE_SIZE, 1);
 468                 if (mz == NULL) {
 469                         PMD_INIT_LOG(ERR,
 470                                      "ERROR: Creating rss_conf structure zone");
 471                         return -ENOMEM;
 472                 }
 473                 memset(mz->addr, 0, mz->len);
 474
 475                 hw->rss_conf = mz->addr;
 476                 hw->rss_confPA = mz->iova;
 477         }
 478
 479         return 0;
 480 }
 481
 482 static void
 483 vmxnet3_write_mac(struct vmxnet3_hw *hw, const uint8_t *addr)
 484 {
 485         uint32_t val;
 486
 487         PMD_INIT_LOG(DEBUG,
 488                      "Writing MAC Address : %02x:%02x:%02x:%02x:%02x:%02x",
 489                      addr[0], addr[1], addr[2],
 490                      addr[3], addr[4], addr[5]);
 491
 492         memcpy(&val, addr, 4);
 493         VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_MACL, val);
 494
 495         memcpy(&val, addr + 4, 2);
 496         VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_MACH, val);
 497 }
 498
 499 static int
 500 vmxnet3_dev_setup_memreg(struct rte_eth_dev *dev)
 501 {
 502         struct vmxnet3_hw *hw = dev->data->dev_private;
 503         Vmxnet3_DriverShared *shared = hw->shared;
 504         Vmxnet3_CmdInfo *cmdInfo;
 505         struct rte_mempool *mp[VMXNET3_MAX_RX_QUEUES];
 506         uint8_t index[VMXNET3_MAX_RX_QUEUES + VMXNET3_MAX_TX_QUEUES];
 507         uint32_t num, i, j, size;
 508
 509         if (hw->memRegsPA == 0) {
 510                 const struct rte_memzone *mz;
 511
 512                 size = sizeof(Vmxnet3_MemRegs) +
 513                         (VMXNET3_MAX_RX_QUEUES + VMXNET3_MAX_TX_QUEUES) *
 514                         sizeof(Vmxnet3_MemoryRegion);
 515
 516                 mz = gpa_zone_reserve(dev, size, "memRegs", rte_socket_id(), 8,
 517                                       1);
 518                 if (mz == NULL) {
 519                         PMD_INIT_LOG(ERR, "ERROR: Creating memRegs zone");
 520                         return -ENOMEM;
 521                 }
 522                 memset(mz->addr, 0, mz->len);
 523                 hw->memRegs = mz->addr;
 524                 hw->memRegsPA = mz->iova;
 525         }
 526
 527         num = hw->num_rx_queues;
 528
 529         for (i = 0; i < num; i++) {
 530                 vmxnet3_rx_queue_t *rxq = dev->data->rx_queues[i];
 531
 532                 mp[i] = rxq->mp;
 533                 index[i] = 1 << i;
 534         }
 535
 536         /*
 537          * The same mempool could be used by multiple queues. In such a case,
 538          * remove duplicate mempool entries. Only one entry is kept with
 539          * bitmask indicating queues that are using this mempool.
 540          */
 541         for (i = 1; i < num; i++) {
 542                 for (j = 0; j < i; j++) {
 543                         if (mp[i] == mp[j]) {
 544                                 mp[i] = NULL;
 545                                 index[j] |= 1 << i;
 546                                 break;
 547                         }
 548                 }
 549         }
 550
 551         j = 0;
 552         for (i = 0; i < num; i++) {
 553                 if (mp[i] == NULL)
 554                         continue;
 555
 556                 Vmxnet3_MemoryRegion *mr = &hw->memRegs->memRegs[j];
 557
 558                 mr->startPA =
 559                         (uintptr_t)STAILQ_FIRST(&mp[i]->mem_list)->iova;
 560                 mr->length = STAILQ_FIRST(&mp[i]->mem_list)->len <= INT32_MAX ?
 561                         STAILQ_FIRST(&mp[i]->mem_list)->len : INT32_MAX;
 562                 mr->txQueueBits = index[i];
 563                 mr->rxQueueBits = index[i];
 564
 565                 PMD_INIT_LOG(INFO,
 566                              "index: %u startPA: %" PRIu64 " length: %u, "
 567                              "rxBits: %x",
 568                              j, mr->startPA, mr->length, mr->rxQueueBits);
 569                 j++;
 570         }
 571         hw->memRegs->numRegs = j;
 572         PMD_INIT_LOG(INFO, "numRegs: %u", j);
 573
 574         size = sizeof(Vmxnet3_MemRegs) +
 575                 (j - 1) * sizeof(Vmxnet3_MemoryRegion);
 576
 577         cmdInfo = &shared->cu.cmdInfo;
 578         cmdInfo->varConf.confVer = 1;
 579         cmdInfo->varConf.confLen = size;
 580         cmdInfo->varConf.confPA = hw->memRegsPA;
 581
 582         return 0;
 583 }
 584
 585 static int
 586 vmxnet3_setup_driver_shared(struct rte_eth_dev *dev)
 587 {
 588         struct rte_eth_conf port_conf = dev->data->dev_conf;
 589         struct vmxnet3_hw *hw = dev->data->dev_private;
 590         uint32_t mtu = dev->data->mtu;
 591         Vmxnet3_DriverShared *shared = hw->shared;
 592         Vmxnet3_DSDevRead *devRead = &shared->devRead;
 593         uint64_t rx_offloads = dev->data->dev_conf.rxmode.offloads;
 594         uint32_t i;
 595         int ret;
 596
 597         hw->mtu = mtu;
 598
 599         shared->magic = VMXNET3_REV1_MAGIC;
 600         devRead->misc.driverInfo.version = VMXNET3_DRIVER_VERSION_NUM;
 601
 602         /* Setting up Guest OS information */
 603         devRead->misc.driverInfo.gos.gosBits   = sizeof(void *) == 4 ?
 604                 VMXNET3_GOS_BITS_32 : VMXNET3_GOS_BITS_64;
 605         devRead->misc.driverInfo.gos.gosType   = VMXNET3_GOS_TYPE_LINUX;
 606         devRead->misc.driverInfo.vmxnet3RevSpt = 1;
 607         devRead->misc.driverInfo.uptVerSpt     = 1;
 608
 609         devRead->misc.mtu = rte_le_to_cpu_32(mtu);
 610         devRead->misc.queueDescPA  = hw->queueDescPA;
 611         devRead->misc.queueDescLen = hw->queue_desc_len;
 612         devRead->misc.numTxQueues  = hw->num_tx_queues;
 613         devRead->misc.numRxQueues  = hw->num_rx_queues;
 614
 615         /*
 616          * Set number of interrupts to 1
 617          * PMD by default disables all the interrupts but this is MUST
 618          * to activate device. It needs at least one interrupt for
 619          * link events to handle
 620          */
 621         hw->num_intrs = devRead->intrConf.numIntrs = 1;
 622         devRead->intrConf.intrCtrl |= VMXNET3_IC_DISABLE_ALL;
 623
 624         for (i = 0; i < hw->num_tx_queues; i++) {
 625                 Vmxnet3_TxQueueDesc *tqd = &hw->tqd_start[i];
 626                 vmxnet3_tx_queue_t *txq  = dev->data->tx_queues[i];
 627
 628                 txq->shared = &hw->tqd_start[i];
 629
 630                 tqd->ctrl.txNumDeferred  = 0;
 631                 tqd->ctrl.txThreshold    = 1;
 632                 tqd->conf.txRingBasePA   = txq->cmd_ring.basePA;
 633                 tqd->conf.compRingBasePA = txq->comp_ring.basePA;
 634                 tqd->conf.dataRingBasePA = txq->data_ring.basePA;
 635
 636                 tqd->conf.txRingSize   = txq->cmd_ring.size;
 637                 tqd->conf.compRingSize = txq->comp_ring.size;
 638                 tqd->conf.dataRingSize = txq->data_ring.size;
 639                 tqd->conf.txDataRingDescSize = txq->txdata_desc_size;
 640                 tqd->conf.intrIdx      = txq->comp_ring.intr_idx;
 641                 tqd->status.stopped    = TRUE;
 642                 tqd->status.error      = 0;
 643                 memset(&tqd->stats, 0, sizeof(tqd->stats));
 644         }
 645
 646         for (i = 0; i < hw->num_rx_queues; i++) {
 647                 Vmxnet3_RxQueueDesc *rqd  = &hw->rqd_start[i];
 648                 vmxnet3_rx_queue_t *rxq   = dev->data->rx_queues[i];
 649
 650                 rxq->shared = &hw->rqd_start[i];
 651
 652                 rqd->conf.rxRingBasePA[0] = rxq->cmd_ring[0].basePA;
 653                 rqd->conf.rxRingBasePA[1] = rxq->cmd_ring[1].basePA;
 654                 rqd->conf.compRingBasePA  = rxq->comp_ring.basePA;
 655
 656                 rqd->conf.rxRingSize[0]   = rxq->cmd_ring[0].size;
 657                 rqd->conf.rxRingSize[1]   = rxq->cmd_ring[1].size;
 658                 rqd->conf.compRingSize    = rxq->comp_ring.size;
 659                 rqd->conf.intrIdx         = rxq->comp_ring.intr_idx;
 660                 if (VMXNET3_VERSION_GE_3(hw)) {
 661                         rqd->conf.rxDataRingBasePA = rxq->data_ring.basePA;
 662                         rqd->conf.rxDataRingDescSize = rxq->data_desc_size;
 663                 }
 664                 rqd->status.stopped       = TRUE;
 665                 rqd->status.error         = 0;
 666                 memset(&rqd->stats, 0, sizeof(rqd->stats));
 667         }
 668
 669         /* RxMode set to 0 of VMXNET3_RXM_xxx */
 670         devRead->rxFilterConf.rxMode = 0;
 671
 672         /* Setting up feature flags */
 673         if (rx_offloads & DEV_RX_OFFLOAD_CHECKSUM)
 674                 devRead->misc.uptFeatures |= VMXNET3_F_RXCSUM;
 675
 676         if (rx_offloads & DEV_RX_OFFLOAD_TCP_LRO) {
 677                 devRead->misc.uptFeatures |= VMXNET3_F_LRO;
 678                 devRead->misc.maxNumRxSG = 0;
 679         }
 680
 681         if (port_conf.rxmode.mq_mode == ETH_MQ_RX_RSS) {
 682                 ret = vmxnet3_rss_configure(dev);
 683                 if (ret != VMXNET3_SUCCESS)
 684                         return ret;
 685
 686                 devRead->misc.uptFeatures |= VMXNET3_F_RSS;
 687                 devRead->rssConfDesc.confVer = 1;
 688                 devRead->rssConfDesc.confLen = sizeof(struct VMXNET3_RSSConf);
 689                 devRead->rssConfDesc.confPA  = hw->rss_confPA;
 690         }
 691
 692         ret = vmxnet3_dev_vlan_offload_set(dev,
 693                         ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK);
 694         if (ret)
 695                 return ret;
 696
 697         vmxnet3_write_mac(hw, dev->data->mac_addrs->addr_bytes);
 698
 699         return VMXNET3_SUCCESS;
 700 }
 701
 702 /*
 703  * Configure device link speed and setup link.
 704  * Must be called after eth_vmxnet3_dev_init. Other wise it might fail
 705  * It returns 0 on success.
 706  */
 707 static int
 708 vmxnet3_dev_start(struct rte_eth_dev *dev)
 709 {
 710         int ret;
 711         struct vmxnet3_hw *hw = dev->data->dev_private;
 712
 713         PMD_INIT_FUNC_TRACE();
 714
 715         /* Save stats before it is reset by CMD_ACTIVATE */
 716         vmxnet3_hw_stats_save(hw);
 717
 718         ret = vmxnet3_setup_driver_shared(dev);
 719         if (ret != VMXNET3_SUCCESS)
 720                 return ret;
 721
 722         /* check if lsc interrupt feature is enabled */
 723         if (dev->data->dev_conf.intr_conf.lsc) {
 724                 struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev->device);
 725
 726                 /* Setup interrupt callback  */
 727                 rte_intr_callback_register(&pci_dev->intr_handle,
 728                                            vmxnet3_interrupt_handler, dev);
 729
 730                 if (rte_intr_enable(&pci_dev->intr_handle) < 0) {
 731                         PMD_INIT_LOG(ERR, "interrupt enable failed");
 732                         return -EIO;
 733                 }
 734         }
 735
 736         /* Exchange shared data with device */
 737         VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_DSAL,
 738                                VMXNET3_GET_ADDR_LO(hw->sharedPA));
 739         VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_DSAH,
 740                                VMXNET3_GET_ADDR_HI(hw->sharedPA));
 741
 742         /* Activate device by register write */
 743         VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, VMXNET3_CMD_ACTIVATE_DEV);
 744         ret = VMXNET3_READ_BAR1_REG(hw, VMXNET3_REG_CMD);
 745
 746         if (ret != 0) {
 747                 PMD_INIT_LOG(ERR, "Device activation: UNSUCCESSFUL");
 748                 return -EINVAL;
 749         }
 750
 751         /* Setup memory region for rx buffers */
 752         ret = vmxnet3_dev_setup_memreg(dev);
 753         if (ret == 0) {
 754                 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD,
 755                                        VMXNET3_CMD_REGISTER_MEMREGS);
 756                 ret = VMXNET3_READ_BAR1_REG(hw, VMXNET3_REG_CMD);
 757                 if (ret != 0)
 758                         PMD_INIT_LOG(DEBUG,
 759                                      "Failed in setup memory region cmd\n");
 760                 ret = 0;
 761         } else {
 762                 PMD_INIT_LOG(DEBUG, "Failed to setup memory region\n");
 763         }
 764
 765         if (VMXNET3_VERSION_GE_4(hw) &&
 766             dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_RSS) {
 767                 /* Check for additional RSS  */
 768                 ret = vmxnet3_v4_rss_configure(dev);
 769                 if (ret != VMXNET3_SUCCESS) {
 770                         PMD_INIT_LOG(ERR, "Failed to configure v4 RSS");
 771                         return ret;
 772                 }
 773         }
 774
 775         /* Disable interrupts */
 776         vmxnet3_disable_intr(hw);
 777
 778         /*
 779          * Load RX queues with blank mbufs and update next2fill index for device
 780          * Update RxMode of the device
 781          */
 782         ret = vmxnet3_dev_rxtx_init(dev);
 783         if (ret != VMXNET3_SUCCESS) {
 784                 PMD_INIT_LOG(ERR, "Device queue init: UNSUCCESSFUL");
 785                 return ret;
 786         }
 787
 788         hw->adapter_stopped = FALSE;
 789
 790         /* Setting proper Rx Mode and issue Rx Mode Update command */
 791         vmxnet3_dev_set_rxmode(hw, VMXNET3_RXM_UCAST | VMXNET3_RXM_BCAST, 1);
 792
 793         if (dev->data->dev_conf.intr_conf.lsc) {
 794                 vmxnet3_enable_intr(hw);
 795
 796                 /*
 797                  * Update link state from device since this won't be
 798                  * done upon starting with lsc in use. This is done
 799                  * only after enabling interrupts to avoid any race
 800                  * where the link state could change without an
 801                  * interrupt being fired.
 802                  */
 803                 __vmxnet3_dev_link_update(dev, 0);
 804         }
 805
 806         return VMXNET3_SUCCESS;
 807 }
 808
 809 /*
 810  * Stop device: disable rx and tx functions to allow for reconfiguring.
 811  */
 812 static void
 813 vmxnet3_dev_stop(struct rte_eth_dev *dev)
 814 {
 815         struct rte_eth_link link;
 816         struct vmxnet3_hw *hw = dev->data->dev_private;
 817
 818         PMD_INIT_FUNC_TRACE();
 819
 820         if (hw->adapter_stopped == 1) {
 821                 PMD_INIT_LOG(DEBUG, "Device already stopped.");
 822                 return;
 823         }
 824
 825         /* disable interrupts */
 826         vmxnet3_disable_intr(hw);
 827
 828         if (dev->data->dev_conf.intr_conf.lsc) {
 829                 struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev->device);
 830
 831                 rte_intr_disable(&pci_dev->intr_handle);
 832
 833                 rte_intr_callback_unregister(&pci_dev->intr_handle,
 834                                              vmxnet3_interrupt_handler, dev);
 835         }
 836
 837         /* quiesce the device first */
 838         VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, VMXNET3_CMD_QUIESCE_DEV);
 839         VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_DSAL, 0);
 840         VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_DSAH, 0);
 841
 842         /* reset the device */
 843         VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, VMXNET3_CMD_RESET_DEV);
 844         PMD_INIT_LOG(DEBUG, "Device reset.");
 845
 846         vmxnet3_dev_clear_queues(dev);
 847
 848         /* Clear recorded link status */
 849         memset(&link, 0, sizeof(link));
 850         link.link_duplex = ETH_LINK_FULL_DUPLEX;
 851         link.link_speed = ETH_SPEED_NUM_10G;
 852         link.link_autoneg = ETH_LINK_FIXED;
 853         rte_eth_linkstatus_set(dev, &link);
 854
 855         hw->adapter_stopped = 1;
 856         dev->data->dev_started = 0;
 857 }
 858
 859 static void
 860 vmxnet3_free_queues(struct rte_eth_dev *dev)
 861 {
 862         int i;
 863
 864         PMD_INIT_FUNC_TRACE();
 865
 866         for (i = 0; i < dev->data->nb_rx_queues; i++) {
 867                 void *rxq = dev->data->rx_queues[i];
 868
 869                 vmxnet3_dev_rx_queue_release(rxq);
 870         }
 871         dev->data->nb_rx_queues = 0;
 872
 873         for (i = 0; i < dev->data->nb_tx_queues; i++) {
 874                 void *txq = dev->data->tx_queues[i];
 875
 876                 vmxnet3_dev_tx_queue_release(txq);
 877         }
 878         dev->data->nb_tx_queues = 0;
 879 }
 880
 881 /*
 882  * Reset and stop device.
 883  */
 884 static int
 885 vmxnet3_dev_close(struct rte_eth_dev *dev)
 886 {
 887         PMD_INIT_FUNC_TRACE();
 888         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
 889                 return 0;
 890
 891         vmxnet3_dev_stop(dev);
 892         vmxnet3_free_queues(dev);
 893
 894         return 0;
 895 }
 896
 897 static void
 898 vmxnet3_hw_tx_stats_get(struct vmxnet3_hw *hw, unsigned int q,
 899                         struct UPT1_TxStats *res)
 900 {
 901 #define VMXNET3_UPDATE_TX_STAT(h, i, f, r)              \
 902                 ((r)->f = (h)->tqd_start[(i)].stats.f + \
 903                         (h)->saved_tx_stats[(i)].f)
 904
 905         VMXNET3_UPDATE_TX_STAT(hw, q, ucastPktsTxOK, res);
 906         VMXNET3_UPDATE_TX_STAT(hw, q, mcastPktsTxOK, res);
 907         VMXNET3_UPDATE_TX_STAT(hw, q, bcastPktsTxOK, res);
 908         VMXNET3_UPDATE_TX_STAT(hw, q, ucastBytesTxOK, res);
 909         VMXNET3_UPDATE_TX_STAT(hw, q, mcastBytesTxOK, res);
 910         VMXNET3_UPDATE_TX_STAT(hw, q, bcastBytesTxOK, res);
 911         VMXNET3_UPDATE_TX_STAT(hw, q, pktsTxError, res);
 912         VMXNET3_UPDATE_TX_STAT(hw, q, pktsTxDiscard, res);
 913
 914 #undef VMXNET3_UPDATE_TX_STAT
 915 }
 916
 917 static void
 918 vmxnet3_hw_rx_stats_get(struct vmxnet3_hw *hw, unsigned int q,
 919                         struct UPT1_RxStats *res)
 920 {
 921 #define VMXNET3_UPDATE_RX_STAT(h, i, f, r)              \
 922                 ((r)->f = (h)->rqd_start[(i)].stats.f + \
 923                         (h)->saved_rx_stats[(i)].f)
 924
 925         VMXNET3_UPDATE_RX_STAT(hw, q, ucastPktsRxOK, res);
 926         VMXNET3_UPDATE_RX_STAT(hw, q, mcastPktsRxOK, res);
 927         VMXNET3_UPDATE_RX_STAT(hw, q, bcastPktsRxOK, res);
 928         VMXNET3_UPDATE_RX_STAT(hw, q, ucastBytesRxOK, res);
 929         VMXNET3_UPDATE_RX_STAT(hw, q, mcastBytesRxOK, res);
 930         VMXNET3_UPDATE_RX_STAT(hw, q, bcastBytesRxOK, res);
 931         VMXNET3_UPDATE_RX_STAT(hw, q, pktsRxError, res);
 932         VMXNET3_UPDATE_RX_STAT(hw, q, pktsRxOutOfBuf, res);
 933
 934 #undef VMXNET3_UPDATE_RX_STAT
 935 }
 936
 937 static void
 938 vmxnet3_tx_stats_get(struct vmxnet3_hw *hw, unsigned int q,
 939                                         struct UPT1_TxStats *res)
 940 {
 941                 vmxnet3_hw_tx_stats_get(hw, q, res);
 942
 943 #define VMXNET3_REDUCE_SNAPSHOT_TX_STAT(h, i, f, r)     \
 944                 ((r)->f -= (h)->snapshot_tx_stats[(i)].f)
 945
 946         VMXNET3_REDUCE_SNAPSHOT_TX_STAT(hw, q, ucastPktsTxOK, res);
 947         VMXNET3_REDUCE_SNAPSHOT_TX_STAT(hw, q, mcastPktsTxOK, res);
 948         VMXNET3_REDUCE_SNAPSHOT_TX_STAT(hw, q, bcastPktsTxOK, res);
 949         VMXNET3_REDUCE_SNAPSHOT_TX_STAT(hw, q, ucastBytesTxOK, res);
 950         VMXNET3_REDUCE_SNAPSHOT_TX_STAT(hw, q, mcastBytesTxOK, res);
 951         VMXNET3_REDUCE_SNAPSHOT_TX_STAT(hw, q, bcastBytesTxOK, res);
 952         VMXNET3_REDUCE_SNAPSHOT_TX_STAT(hw, q, pktsTxError, res);
 953         VMXNET3_REDUCE_SNAPSHOT_TX_STAT(hw, q, pktsTxDiscard, res);
 954
 955 #undef VMXNET3_REDUCE_SNAPSHOT_TX_STAT
 956 }
 957
 958 static void
 959 vmxnet3_rx_stats_get(struct vmxnet3_hw *hw, unsigned int q,
 960                                         struct UPT1_RxStats *res)
 961 {
 962                 vmxnet3_hw_rx_stats_get(hw, q, res);
 963
 964 #define VMXNET3_REDUCE_SNAPSHOT_RX_STAT(h, i, f, r)     \
 965                 ((r)->f -= (h)->snapshot_rx_stats[(i)].f)
 966
 967         VMXNET3_REDUCE_SNAPSHOT_RX_STAT(hw, q, ucastPktsRxOK, res);
 968         VMXNET3_REDUCE_SNAPSHOT_RX_STAT(hw, q, mcastPktsRxOK, res);
 969         VMXNET3_REDUCE_SNAPSHOT_RX_STAT(hw, q, bcastPktsRxOK, res);
 970         VMXNET3_REDUCE_SNAPSHOT_RX_STAT(hw, q, ucastBytesRxOK, res);
 971         VMXNET3_REDUCE_SNAPSHOT_RX_STAT(hw, q, mcastBytesRxOK, res);
 972         VMXNET3_REDUCE_SNAPSHOT_RX_STAT(hw, q, bcastBytesRxOK, res);
 973         VMXNET3_REDUCE_SNAPSHOT_RX_STAT(hw, q, pktsRxError, res);
 974         VMXNET3_REDUCE_SNAPSHOT_RX_STAT(hw, q, pktsRxOutOfBuf, res);
 975
 976 #undef VMXNET3_REDUCE_SNAPSHOT_RX_STAT
 977 }
 978
 979 static void
 980 vmxnet3_hw_stats_save(struct vmxnet3_hw *hw)
 981 {
 982         unsigned int i;
 983
 984         VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, VMXNET3_CMD_GET_STATS);
 985
 986         RTE_BUILD_BUG_ON(RTE_ETHDEV_QUEUE_STAT_CNTRS < VMXNET3_MAX_TX_QUEUES);
 987
 988         for (i = 0; i < hw->num_tx_queues; i++)
 989                 vmxnet3_hw_tx_stats_get(hw, i, &hw->saved_tx_stats[i]);
 990         for (i = 0; i < hw->num_rx_queues; i++)
 991                 vmxnet3_hw_rx_stats_get(hw, i, &hw->saved_rx_stats[i]);
 992 }
 993
 994 static int
 995 vmxnet3_dev_xstats_get_names(struct rte_eth_dev *dev,
 996                              struct rte_eth_xstat_name *xstats_names,
 997                              unsigned int n)
 998 {
 999         unsigned int i, t, count = 0;
1000         unsigned int nstats =
1001                 dev->data->nb_tx_queues * RTE_DIM(vmxnet3_txq_stat_strings) +
1002                 dev->data->nb_rx_queues * RTE_DIM(vmxnet3_rxq_stat_strings);
1003
1004         if (!xstats_names || n < nstats)
1005                 return nstats;
1006
1007         for (i = 0; i < dev->data->nb_rx_queues; i++) {
1008                 if (!dev->data->rx_queues[i])
1009                         continue;
1010
1011                 for (t = 0; t < RTE_DIM(vmxnet3_rxq_stat_strings); t++) {
1012                         snprintf(xstats_names[count].name,
1013                                  sizeof(xstats_names[count].name),
1014                                  "rx_q%u_%s", i,
1015                                  vmxnet3_rxq_stat_strings[t].name);
1016                         count++;
1017                 }
1018         }
1019
1020         for (i = 0; i < dev->data->nb_tx_queues; i++) {
1021                 if (!dev->data->tx_queues[i])
1022                         continue;
1023
1024                 for (t = 0; t < RTE_DIM(vmxnet3_txq_stat_strings); t++) {
1025                         snprintf(xstats_names[count].name,
1026                                  sizeof(xstats_names[count].name),
1027                                  "tx_q%u_%s", i,
1028                                  vmxnet3_txq_stat_strings[t].name);
1029                         count++;
1030                 }
1031         }
1032
1033         return count;
1034 }
1035
1036 static int
1037 vmxnet3_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
1038                        unsigned int n)
1039 {
1040         unsigned int i, t, count = 0;
1041         unsigned int nstats =
1042                 dev->data->nb_tx_queues * RTE_DIM(vmxnet3_txq_stat_strings) +
1043                 dev->data->nb_rx_queues * RTE_DIM(vmxnet3_rxq_stat_strings);
1044
1045         if (n < nstats)
1046                 return nstats;
1047
1048         for (i = 0; i < dev->data->nb_rx_queues; i++) {
1049                 struct vmxnet3_rx_queue *rxq = dev->data->rx_queues[i];
1050
1051                 if (rxq == NULL)
1052                         continue;
1053
1054                 for (t = 0; t < RTE_DIM(vmxnet3_rxq_stat_strings); t++) {
1055                         xstats[count].value = *(uint64_t *)(((char *)&rxq->stats) +
1056                                 vmxnet3_rxq_stat_strings[t].offset);
1057                         xstats[count].id = count;
1058                         count++;
1059                 }
1060         }
1061
1062         for (i = 0; i < dev->data->nb_tx_queues; i++) {
1063                 struct vmxnet3_tx_queue *txq = dev->data->tx_queues[i];
1064
1065                 if (txq == NULL)
1066                         continue;
1067
1068                 for (t = 0; t < RTE_DIM(vmxnet3_txq_stat_strings); t++) {
1069                         xstats[count].value = *(uint64_t *)(((char *)&txq->stats) +
1070                                 vmxnet3_txq_stat_strings[t].offset);
1071                         xstats[count].id = count;
1072                         count++;
1073                 }
1074         }
1075
1076         return count;
1077 }
1078
1079 static int
1080 vmxnet3_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
1081 {
1082         unsigned int i;
1083         struct vmxnet3_hw *hw = dev->data->dev_private;
1084         struct UPT1_TxStats txStats;
1085         struct UPT1_RxStats rxStats;
1086
1087         VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, VMXNET3_CMD_GET_STATS);
1088
1089         RTE_BUILD_BUG_ON(RTE_ETHDEV_QUEUE_STAT_CNTRS < VMXNET3_MAX_TX_QUEUES);
1090         for (i = 0; i < hw->num_tx_queues; i++) {
1091                 vmxnet3_tx_stats_get(hw, i, &txStats);
1092
1093                 stats->q_opackets[i] = txStats.ucastPktsTxOK +
1094                         txStats.mcastPktsTxOK +
1095                         txStats.bcastPktsTxOK;
1096
1097                 stats->q_obytes[i] = txStats.ucastBytesTxOK +
1098                         txStats.mcastBytesTxOK +
1099                         txStats.bcastBytesTxOK;
1100
1101                 stats->opackets += stats->q_opackets[i];
1102                 stats->obytes += stats->q_obytes[i];
1103                 stats->oerrors += txStats.pktsTxError + txStats.pktsTxDiscard;
1104         }
1105
1106         RTE_BUILD_BUG_ON(RTE_ETHDEV_QUEUE_STAT_CNTRS < VMXNET3_MAX_RX_QUEUES);
1107         for (i = 0; i < hw->num_rx_queues; i++) {
1108                 vmxnet3_rx_stats_get(hw, i, &rxStats);
1109
1110                 stats->q_ipackets[i] = rxStats.ucastPktsRxOK +
1111                         rxStats.mcastPktsRxOK +
1112                         rxStats.bcastPktsRxOK;
1113
1114                 stats->q_ibytes[i] = rxStats.ucastBytesRxOK +
1115                         rxStats.mcastBytesRxOK +
1116                         rxStats.bcastBytesRxOK;
1117
1118                 stats->ipackets += stats->q_ipackets[i];
1119                 stats->ibytes += stats->q_ibytes[i];
1120
1121                 stats->q_errors[i] = rxStats.pktsRxError;
1122                 stats->ierrors += rxStats.pktsRxError;
1123                 stats->imissed += rxStats.pktsRxOutOfBuf;
1124         }
1125
1126         return 0;
1127 }
1128
1129 static int
1130 vmxnet3_dev_stats_reset(struct rte_eth_dev *dev)
1131 {
1132         unsigned int i;
1133         struct vmxnet3_hw *hw = dev->data->dev_private;
1134         struct UPT1_TxStats txStats = {0};
1135         struct UPT1_RxStats rxStats = {0};
1136
1137         VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, VMXNET3_CMD_GET_STATS);
1138
1139         RTE_BUILD_BUG_ON(RTE_ETHDEV_QUEUE_STAT_CNTRS < VMXNET3_MAX_TX_QUEUES);
1140
1141         for (i = 0; i < hw->num_tx_queues; i++) {
1142                 vmxnet3_hw_tx_stats_get(hw, i, &txStats);
1143                 memcpy(&hw->snapshot_tx_stats[i], &txStats,
1144                         sizeof(hw->snapshot_tx_stats[0]));
1145         }
1146         for (i = 0; i < hw->num_rx_queues; i++) {
1147                 vmxnet3_hw_rx_stats_get(hw, i, &rxStats);
1148                 memcpy(&hw->snapshot_rx_stats[i], &rxStats,
1149                         sizeof(hw->snapshot_rx_stats[0]));
1150         }
1151
1152         return 0;
1153 }
1154
1155 static int
1156 vmxnet3_dev_info_get(struct rte_eth_dev *dev,
1157                      struct rte_eth_dev_info *dev_info)
1158 {
1159         struct vmxnet3_hw *hw = dev->data->dev_private;
1160
1161         dev_info->max_rx_queues = VMXNET3_MAX_RX_QUEUES;
1162         dev_info->max_tx_queues = VMXNET3_MAX_TX_QUEUES;
1163         dev_info->min_rx_bufsize = 1518 + RTE_PKTMBUF_HEADROOM;
1164         dev_info->max_rx_pktlen = 16384; /* includes CRC, cf MAXFRS register */
1165         dev_info->min_mtu = VMXNET3_MIN_MTU;
1166         dev_info->max_mtu = VMXNET3_MAX_MTU;
1167         dev_info->speed_capa = ETH_LINK_SPEED_10G;
1168         dev_info->max_mac_addrs = VMXNET3_MAX_MAC_ADDRS;
1169
1170         dev_info->flow_type_rss_offloads = VMXNET3_RSS_OFFLOAD_ALL;
1171
1172         if (VMXNET3_VERSION_GE_4(hw)) {
1173                 dev_info->flow_type_rss_offloads |= VMXNET3_V4_RSS_MASK;
1174         }
1175
1176         dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
1177                 .nb_max = VMXNET3_RX_RING_MAX_SIZE,
1178                 .nb_min = VMXNET3_DEF_RX_RING_SIZE,
1179                 .nb_align = 1,
1180         };
1181
1182         dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
1183                 .nb_max = VMXNET3_TX_RING_MAX_SIZE,
1184                 .nb_min = VMXNET3_DEF_TX_RING_SIZE,
1185                 .nb_align = 1,
1186                 .nb_seg_max = VMXNET3_TX_MAX_SEG,
1187                 .nb_mtu_seg_max = VMXNET3_MAX_TXD_PER_PKT,
1188         };
1189
1190         dev_info->rx_offload_capa = VMXNET3_RX_OFFLOAD_CAP;
1191         dev_info->rx_queue_offload_capa = 0;
1192         dev_info->tx_offload_capa = VMXNET3_TX_OFFLOAD_CAP;
1193         dev_info->tx_queue_offload_capa = 0;
1194
1195         return 0;
1196 }
1197
1198 static const uint32_t *
1199 vmxnet3_dev_supported_ptypes_get(struct rte_eth_dev *dev)
1200 {
1201         static const uint32_t ptypes[] = {
1202                 RTE_PTYPE_L3_IPV4_EXT,
1203                 RTE_PTYPE_L3_IPV4,
1204                 RTE_PTYPE_UNKNOWN
1205         };
1206
1207         if (dev->rx_pkt_burst == vmxnet3_recv_pkts)
1208                 return ptypes;
1209         return NULL;
1210 }
1211
1212 static int
1213 vmxnet3_dev_mtu_set(struct rte_eth_dev *dev, __rte_unused uint16_t mtu)
1214 {
1215         if (dev->data->dev_started) {
1216                 PMD_DRV_LOG(ERR, "Port %d must be stopped to configure MTU",
1217                             dev->data->port_id);
1218                 return -EBUSY;
1219         }
1220
1221         return 0;
1222 }
1223
1224 static int
1225 vmxnet3_mac_addr_set(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr)
1226 {
1227         struct vmxnet3_hw *hw = dev->data->dev_private;
1228
1229         rte_ether_addr_copy(mac_addr, (struct rte_ether_addr *)(hw->perm_addr));
1230         vmxnet3_write_mac(hw, mac_addr->addr_bytes);
1231         return 0;
1232 }
1233
1234 /* return 0 means link status changed, -1 means not changed */
1235 static int
1236 __vmxnet3_dev_link_update(struct rte_eth_dev *dev,
1237                           __rte_unused int wait_to_complete)
1238 {
1239         struct vmxnet3_hw *hw = dev->data->dev_private;
1240         struct rte_eth_link link;
1241         uint32_t ret;
1242
1243         memset(&link, 0, sizeof(link));
1244
1245         VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, VMXNET3_CMD_GET_LINK);
1246         ret = VMXNET3_READ_BAR1_REG(hw, VMXNET3_REG_CMD);
1247
1248         if (ret & 0x1)
1249                 link.link_status = ETH_LINK_UP;
1250         link.link_duplex = ETH_LINK_FULL_DUPLEX;
1251         link.link_speed = ETH_SPEED_NUM_10G;
1252         link.link_autoneg = ETH_LINK_FIXED;
1253
1254         return rte_eth_linkstatus_set(dev, &link);
1255 }
1256
1257 static int
1258 vmxnet3_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
1259 {
1260         /* Link status doesn't change for stopped dev */
1261         if (dev->data->dev_started == 0)
1262                 return -1;
1263
1264         return __vmxnet3_dev_link_update(dev, wait_to_complete);
1265 }
1266
1267 /* Updating rxmode through Vmxnet3_DriverShared structure in adapter */
1268 static void
1269 vmxnet3_dev_set_rxmode(struct vmxnet3_hw *hw, uint32_t feature, int set)
1270 {
1271         struct Vmxnet3_RxFilterConf *rxConf = &hw->shared->devRead.rxFilterConf;
1272
1273         if (set)
1274                 rxConf->rxMode = rxConf->rxMode | feature;
1275         else
1276                 rxConf->rxMode = rxConf->rxMode & (~feature);
1277
1278         VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, VMXNET3_CMD_UPDATE_RX_MODE);
1279 }
1280
1281 /* Promiscuous supported only if Vmxnet3_DriverShared is initialized in adapter */
1282 static int
1283 vmxnet3_dev_promiscuous_enable(struct rte_eth_dev *dev)
1284 {
1285         struct vmxnet3_hw *hw = dev->data->dev_private;
1286         uint32_t *vf_table = hw->shared->devRead.rxFilterConf.vfTable;
1287
1288         memset(vf_table, 0, VMXNET3_VFT_TABLE_SIZE);
1289         vmxnet3_dev_set_rxmode(hw, VMXNET3_RXM_PROMISC, 1);
1290
1291         VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD,
1292                                VMXNET3_CMD_UPDATE_VLAN_FILTERS);
1293
1294         return 0;
1295 }
1296
1297 /* Promiscuous supported only if Vmxnet3_DriverShared is initialized in adapter */
1298 static int
1299 vmxnet3_dev_promiscuous_disable(struct rte_eth_dev *dev)
1300 {
1301         struct vmxnet3_hw *hw = dev->data->dev_private;
1302         uint32_t *vf_table = hw->shared->devRead.rxFilterConf.vfTable;
1303         uint64_t rx_offloads = dev->data->dev_conf.rxmode.offloads;
1304
1305         if (rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
1306                 memcpy(vf_table, hw->shadow_vfta, VMXNET3_VFT_TABLE_SIZE);
1307         else
1308                 memset(vf_table, 0xff, VMXNET3_VFT_TABLE_SIZE);
1309         vmxnet3_dev_set_rxmode(hw, VMXNET3_RXM_PROMISC, 0);
1310         VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD,
1311                                VMXNET3_CMD_UPDATE_VLAN_FILTERS);
1312
1313         return 0;
1314 }
1315
1316 /* Allmulticast supported only if Vmxnet3_DriverShared is initialized in adapter */
1317 static int
1318 vmxnet3_dev_allmulticast_enable(struct rte_eth_dev *dev)
1319 {
1320         struct vmxnet3_hw *hw = dev->data->dev_private;
1321
1322         vmxnet3_dev_set_rxmode(hw, VMXNET3_RXM_ALL_MULTI, 1);
1323
1324         return 0;
1325 }
1326
1327 /* Allmulticast supported only if Vmxnet3_DriverShared is initialized in adapter */
1328 static int
1329 vmxnet3_dev_allmulticast_disable(struct rte_eth_dev *dev)
1330 {
1331         struct vmxnet3_hw *hw = dev->data->dev_private;
1332
1333         vmxnet3_dev_set_rxmode(hw, VMXNET3_RXM_ALL_MULTI, 0);
1334
1335         return 0;
1336 }
1337
1338 /* Enable/disable filter on vlan */
1339 static int
1340 vmxnet3_dev_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vid, int on)
1341 {
1342         struct vmxnet3_hw *hw = dev->data->dev_private;
1343         struct Vmxnet3_RxFilterConf *rxConf = &hw->shared->devRead.rxFilterConf;
1344         uint32_t *vf_table = rxConf->vfTable;
1345
1346         /* save state for restore */
1347         if (on)
1348                 VMXNET3_SET_VFTABLE_ENTRY(hw->shadow_vfta, vid);
1349         else
1350                 VMXNET3_CLEAR_VFTABLE_ENTRY(hw->shadow_vfta, vid);
1351
1352         /* don't change active filter if in promiscuous mode */
1353         if (rxConf->rxMode & VMXNET3_RXM_PROMISC)
1354                 return 0;
1355
1356         /* set in hardware */
1357         if (on)
1358                 VMXNET3_SET_VFTABLE_ENTRY(vf_table, vid);
1359         else
1360                 VMXNET3_CLEAR_VFTABLE_ENTRY(vf_table, vid);
1361
1362         VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD,
1363                                VMXNET3_CMD_UPDATE_VLAN_FILTERS);
1364         return 0;
1365 }
1366
1367 static int
1368 vmxnet3_dev_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1369 {
1370         struct vmxnet3_hw *hw = dev->data->dev_private;
1371         Vmxnet3_DSDevRead *devRead = &hw->shared->devRead;
1372         uint32_t *vf_table = devRead->rxFilterConf.vfTable;
1373         uint64_t rx_offloads = dev->data->dev_conf.rxmode.offloads;
1374
1375         if (mask & ETH_VLAN_STRIP_MASK) {
1376                 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
1377                         devRead->misc.uptFeatures |= UPT1_F_RXVLAN;
1378                 else
1379                         devRead->misc.uptFeatures &= ~UPT1_F_RXVLAN;
1380
1381                 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD,
1382                                        VMXNET3_CMD_UPDATE_FEATURE);
1383         }
1384
1385         if (mask & ETH_VLAN_FILTER_MASK) {
1386                 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
1387                         memcpy(vf_table, hw->shadow_vfta, VMXNET3_VFT_TABLE_SIZE);
1388                 else
1389                         memset(vf_table, 0xff, VMXNET3_VFT_TABLE_SIZE);
1390
1391                 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD,
1392                                        VMXNET3_CMD_UPDATE_VLAN_FILTERS);
1393         }
1394
1395         return 0;
1396 }
1397
1398 static void
1399 vmxnet3_process_events(struct rte_eth_dev *dev)
1400 {
1401         struct vmxnet3_hw *hw = dev->data->dev_private;
1402         uint32_t events = hw->shared->ecr;
1403
1404         if (!events)
1405                 return;
1406
1407         /*
1408          * ECR bits when written with 1b are cleared. Hence write
1409          * events back to ECR so that the bits which were set will be reset.
1410          */
1411         VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_ECR, events);
1412
1413         /* Check if link state has changed */
1414         if (events & VMXNET3_ECR_LINK) {
1415                 PMD_DRV_LOG(DEBUG, "Process events: VMXNET3_ECR_LINK event");
1416                 if (vmxnet3_dev_link_update(dev, 0) == 0)
1417                         rte_eth_dev_callback_process(dev,
1418                                                      RTE_ETH_EVENT_INTR_LSC,
1419                                                      NULL);
1420         }
1421
1422         /* Check if there is an error on xmit/recv queues */
1423         if (events & (VMXNET3_ECR_TQERR | VMXNET3_ECR_RQERR)) {
1424                 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD,
1425                                        VMXNET3_CMD_GET_QUEUE_STATUS);
1426
1427                 if (hw->tqd_start->status.stopped)
1428                         PMD_DRV_LOG(ERR, "tq error 0x%x",
1429                                     hw->tqd_start->status.error);
1430
1431                 if (hw->rqd_start->status.stopped)
1432                         PMD_DRV_LOG(ERR, "rq error 0x%x",
1433                                      hw->rqd_start->status.error);
1434
1435                 /* Reset the device */
1436                 /* Have to reset the device */
1437         }
1438
1439         if (events & VMXNET3_ECR_DIC)
1440                 PMD_DRV_LOG(DEBUG, "Device implementation change event.");
1441
1442         if (events & VMXNET3_ECR_DEBUG)
1443                 PMD_DRV_LOG(DEBUG, "Debug event generated by device.");
1444 }
1445
1446 static void
1447 vmxnet3_interrupt_handler(void *param)
1448 {
1449         struct rte_eth_dev *dev = param;
1450         struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev->device);
1451
1452         vmxnet3_process_events(dev);
1453
1454         if (rte_intr_ack(&pci_dev->intr_handle) < 0)
1455                 PMD_DRV_LOG(ERR, "interrupt enable failed");
1456 }
1457
1458 RTE_PMD_REGISTER_PCI(net_vmxnet3, rte_vmxnet3_pmd);
1459 RTE_PMD_REGISTER_PCI_TABLE(net_vmxnet3, pci_id_vmxnet3_map);
1460 RTE_PMD_REGISTER_KMOD_DEP(net_vmxnet3, "* igb_uio | uio_pci_generic | vfio-pci");
1461 RTE_LOG_REGISTER(vmxnet3_logtype_init, pmd.net.vmxnet3.init, NOTICE);
1462 RTE_LOG_REGISTER(vmxnet3_logtype_driver, pmd.net.vmxnet3.driver, NOTICE);