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34 #include <sys/queue.h>
43 #include <rte_byteorder.h>
44 #include <rte_common.h>
45 #include <rte_cycles.h>
47 #include <rte_interrupts.h>
49 #include <rte_debug.h>
51 #include <rte_atomic.h>
52 #include <rte_branch_prediction.h>
53 #include <rte_memory.h>
54 #include <rte_memzone.h>
56 #include <rte_alarm.h>
57 #include <rte_ether.h>
58 #include <rte_ethdev.h>
59 #include <rte_atomic.h>
60 #include <rte_string_fns.h>
61 #include <rte_malloc.h>
64 #include "base/vmxnet3_defs.h"
66 #include "vmxnet3_ring.h"
67 #include "vmxnet3_logs.h"
68 #include "vmxnet3_ethdev.h"
70 #define PROCESS_SYS_EVENTS 0
72 #define VMXNET3_TX_MAX_SEG UINT8_MAX
74 static int eth_vmxnet3_dev_init(struct rte_eth_dev *eth_dev);
75 static int eth_vmxnet3_dev_uninit(struct rte_eth_dev *eth_dev);
76 static int vmxnet3_dev_configure(struct rte_eth_dev *dev);
77 static int vmxnet3_dev_start(struct rte_eth_dev *dev);
78 static void vmxnet3_dev_stop(struct rte_eth_dev *dev);
79 static void vmxnet3_dev_close(struct rte_eth_dev *dev);
80 static void vmxnet3_dev_set_rxmode(struct vmxnet3_hw *hw, uint32_t feature, int set);
81 static void vmxnet3_dev_promiscuous_enable(struct rte_eth_dev *dev);
82 static void vmxnet3_dev_promiscuous_disable(struct rte_eth_dev *dev);
83 static void vmxnet3_dev_allmulticast_enable(struct rte_eth_dev *dev);
84 static void vmxnet3_dev_allmulticast_disable(struct rte_eth_dev *dev);
85 static int vmxnet3_dev_link_update(struct rte_eth_dev *dev,
86 int wait_to_complete);
87 static void vmxnet3_dev_stats_get(struct rte_eth_dev *dev,
88 struct rte_eth_stats *stats);
89 static void vmxnet3_dev_info_get(struct rte_eth_dev *dev,
90 struct rte_eth_dev_info *dev_info);
91 static const uint32_t *
92 vmxnet3_dev_supported_ptypes_get(struct rte_eth_dev *dev);
93 static int vmxnet3_dev_vlan_filter_set(struct rte_eth_dev *dev,
94 uint16_t vid, int on);
95 static void vmxnet3_dev_vlan_offload_set(struct rte_eth_dev *dev, int mask);
96 static void vmxnet3_mac_addr_set(struct rte_eth_dev *dev,
97 struct ether_addr *mac_addr);
99 #if PROCESS_SYS_EVENTS == 1
100 static void vmxnet3_process_events(struct vmxnet3_hw *);
103 * The set of PCI devices this driver supports
105 #define VMWARE_PCI_VENDOR_ID 0x15AD
106 #define VMWARE_DEV_ID_VMXNET3 0x07B0
107 static const struct rte_pci_id pci_id_vmxnet3_map[] = {
108 { RTE_PCI_DEVICE(VMWARE_PCI_VENDOR_ID, VMWARE_DEV_ID_VMXNET3) },
109 { .vendor_id = 0, /* sentinel */ },
112 static const struct eth_dev_ops vmxnet3_eth_dev_ops = {
113 .dev_configure = vmxnet3_dev_configure,
114 .dev_start = vmxnet3_dev_start,
115 .dev_stop = vmxnet3_dev_stop,
116 .dev_close = vmxnet3_dev_close,
117 .promiscuous_enable = vmxnet3_dev_promiscuous_enable,
118 .promiscuous_disable = vmxnet3_dev_promiscuous_disable,
119 .allmulticast_enable = vmxnet3_dev_allmulticast_enable,
120 .allmulticast_disable = vmxnet3_dev_allmulticast_disable,
121 .link_update = vmxnet3_dev_link_update,
122 .stats_get = vmxnet3_dev_stats_get,
123 .mac_addr_set = vmxnet3_mac_addr_set,
124 .dev_infos_get = vmxnet3_dev_info_get,
125 .dev_supported_ptypes_get = vmxnet3_dev_supported_ptypes_get,
126 .vlan_filter_set = vmxnet3_dev_vlan_filter_set,
127 .vlan_offload_set = vmxnet3_dev_vlan_offload_set,
128 .rx_queue_setup = vmxnet3_dev_rx_queue_setup,
129 .rx_queue_release = vmxnet3_dev_rx_queue_release,
130 .tx_queue_setup = vmxnet3_dev_tx_queue_setup,
131 .tx_queue_release = vmxnet3_dev_tx_queue_release,
134 static const struct rte_memzone *
135 gpa_zone_reserve(struct rte_eth_dev *dev, uint32_t size,
136 const char *post_string, int socket_id,
137 uint16_t align, bool reuse)
139 char z_name[RTE_MEMZONE_NAMESIZE];
140 const struct rte_memzone *mz;
142 snprintf(z_name, sizeof(z_name), "%s_%d_%s",
143 dev->data->drv_name, dev->data->port_id, post_string);
145 mz = rte_memzone_lookup(z_name);
148 rte_memzone_free(mz);
149 return rte_memzone_reserve_aligned(z_name, size, socket_id,
156 return rte_memzone_reserve_aligned(z_name, size, socket_id, 0, align);
160 * Atomically reads the link status information from global
161 * structure rte_eth_dev.
164 * - Pointer to the structure rte_eth_dev to read from.
165 * - Pointer to the buffer to be saved with the link status.
168 * - On success, zero.
169 * - On failure, negative value.
173 vmxnet3_dev_atomic_read_link_status(struct rte_eth_dev *dev,
174 struct rte_eth_link *link)
176 struct rte_eth_link *dst = link;
177 struct rte_eth_link *src = &(dev->data->dev_link);
179 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
180 *(uint64_t *)src) == 0)
187 * Atomically writes the link status information into global
188 * structure rte_eth_dev.
191 * - Pointer to the structure rte_eth_dev to write to.
192 * - Pointer to the buffer to be saved with the link status.
195 * - On success, zero.
196 * - On failure, negative value.
199 vmxnet3_dev_atomic_write_link_status(struct rte_eth_dev *dev,
200 struct rte_eth_link *link)
202 struct rte_eth_link *dst = &(dev->data->dev_link);
203 struct rte_eth_link *src = link;
205 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
206 *(uint64_t *)src) == 0)
213 * This function is based on vmxnet3_disable_intr()
216 vmxnet3_disable_intr(struct vmxnet3_hw *hw)
220 PMD_INIT_FUNC_TRACE();
222 hw->shared->devRead.intrConf.intrCtrl |= VMXNET3_IC_DISABLE_ALL;
223 for (i = 0; i < VMXNET3_MAX_INTRS; i++)
224 VMXNET3_WRITE_BAR0_REG(hw, VMXNET3_REG_IMR + i * 8, 1);
228 * It returns 0 on success.
231 eth_vmxnet3_dev_init(struct rte_eth_dev *eth_dev)
233 struct rte_pci_device *pci_dev;
234 struct vmxnet3_hw *hw = eth_dev->data->dev_private;
235 uint32_t mac_hi, mac_lo, ver;
237 PMD_INIT_FUNC_TRACE();
239 eth_dev->dev_ops = &vmxnet3_eth_dev_ops;
240 eth_dev->rx_pkt_burst = &vmxnet3_recv_pkts;
241 eth_dev->tx_pkt_burst = &vmxnet3_xmit_pkts;
242 eth_dev->tx_pkt_prepare = vmxnet3_prep_pkts;
243 pci_dev = RTE_DEV_TO_PCI(eth_dev->device);
246 * for secondary processes, we don't initialize any further as primary
247 * has already done this work.
249 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
252 rte_eth_copy_pci_info(eth_dev, pci_dev);
254 /* Vendor and Device ID need to be set before init of shared code */
255 hw->device_id = pci_dev->id.device_id;
256 hw->vendor_id = pci_dev->id.vendor_id;
257 hw->hw_addr0 = (void *)pci_dev->mem_resource[0].addr;
258 hw->hw_addr1 = (void *)pci_dev->mem_resource[1].addr;
260 hw->num_rx_queues = 1;
261 hw->num_tx_queues = 1;
262 hw->bufs_per_pkt = 1;
264 /* Check h/w version compatibility with driver. */
265 ver = VMXNET3_READ_BAR1_REG(hw, VMXNET3_REG_VRRS);
266 PMD_INIT_LOG(DEBUG, "Hardware version : %d", ver);
268 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_VRRS, 1);
270 PMD_INIT_LOG(ERR, "Incompatible h/w version, should be 0x1");
274 /* Check UPT version compatibility with driver. */
275 ver = VMXNET3_READ_BAR1_REG(hw, VMXNET3_REG_UVRS);
276 PMD_INIT_LOG(DEBUG, "UPT hardware version : %d", ver);
278 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_UVRS, 1);
280 PMD_INIT_LOG(ERR, "Incompatible UPT version.");
284 /* Getting MAC Address */
285 mac_lo = VMXNET3_READ_BAR1_REG(hw, VMXNET3_REG_MACL);
286 mac_hi = VMXNET3_READ_BAR1_REG(hw, VMXNET3_REG_MACH);
287 memcpy(hw->perm_addr, &mac_lo, 4);
288 memcpy(hw->perm_addr + 4, &mac_hi, 2);
290 /* Allocate memory for storing MAC addresses */
291 eth_dev->data->mac_addrs = rte_zmalloc("vmxnet3", ETHER_ADDR_LEN *
292 VMXNET3_MAX_MAC_ADDRS, 0);
293 if (eth_dev->data->mac_addrs == NULL) {
295 "Failed to allocate %d bytes needed to store MAC addresses",
296 ETHER_ADDR_LEN * VMXNET3_MAX_MAC_ADDRS);
299 /* Copy the permanent MAC address */
300 ether_addr_copy((struct ether_addr *) hw->perm_addr,
301 ð_dev->data->mac_addrs[0]);
303 PMD_INIT_LOG(DEBUG, "MAC Address : %02x:%02x:%02x:%02x:%02x:%02x",
304 hw->perm_addr[0], hw->perm_addr[1], hw->perm_addr[2],
305 hw->perm_addr[3], hw->perm_addr[4], hw->perm_addr[5]);
307 /* Put device in Quiesce Mode */
308 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, VMXNET3_CMD_QUIESCE_DEV);
310 /* allow untagged pkts */
311 VMXNET3_SET_VFTABLE_ENTRY(hw->shadow_vfta, 0);
317 eth_vmxnet3_dev_uninit(struct rte_eth_dev *eth_dev)
319 struct vmxnet3_hw *hw = eth_dev->data->dev_private;
321 PMD_INIT_FUNC_TRACE();
323 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
326 if (hw->adapter_stopped == 0)
327 vmxnet3_dev_close(eth_dev);
329 eth_dev->dev_ops = NULL;
330 eth_dev->rx_pkt_burst = NULL;
331 eth_dev->tx_pkt_burst = NULL;
332 eth_dev->tx_pkt_prepare = NULL;
334 rte_free(eth_dev->data->mac_addrs);
335 eth_dev->data->mac_addrs = NULL;
340 static struct eth_driver rte_vmxnet3_pmd = {
342 .id_table = pci_id_vmxnet3_map,
343 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_DETACHABLE,
344 .probe = rte_eth_dev_pci_probe,
345 .remove = rte_eth_dev_pci_remove,
347 .eth_dev_init = eth_vmxnet3_dev_init,
348 .eth_dev_uninit = eth_vmxnet3_dev_uninit,
349 .dev_private_size = sizeof(struct vmxnet3_hw),
353 vmxnet3_dev_configure(struct rte_eth_dev *dev)
355 const struct rte_memzone *mz;
356 struct vmxnet3_hw *hw = dev->data->dev_private;
359 PMD_INIT_FUNC_TRACE();
361 if (dev->data->nb_tx_queues > VMXNET3_MAX_TX_QUEUES ||
362 dev->data->nb_rx_queues > VMXNET3_MAX_RX_QUEUES) {
363 PMD_INIT_LOG(ERR, "ERROR: Number of queues not supported");
367 if (!rte_is_power_of_2(dev->data->nb_rx_queues)) {
368 PMD_INIT_LOG(ERR, "ERROR: Number of rx queues not power of 2");
372 size = dev->data->nb_rx_queues * sizeof(struct Vmxnet3_TxQueueDesc) +
373 dev->data->nb_tx_queues * sizeof(struct Vmxnet3_RxQueueDesc);
375 if (size > UINT16_MAX)
378 hw->num_rx_queues = (uint8_t)dev->data->nb_rx_queues;
379 hw->num_tx_queues = (uint8_t)dev->data->nb_tx_queues;
382 * Allocate a memzone for Vmxnet3_DriverShared - Vmxnet3_DSDevRead
385 mz = gpa_zone_reserve(dev, sizeof(struct Vmxnet3_DriverShared),
386 "shared", rte_socket_id(), 8, 1);
389 PMD_INIT_LOG(ERR, "ERROR: Creating shared zone");
392 memset(mz->addr, 0, mz->len);
394 hw->shared = mz->addr;
395 hw->sharedPA = mz->phys_addr;
398 * Allocate a memzone for Vmxnet3_RxQueueDesc - Vmxnet3_TxQueueDesc
401 * We cannot reuse this memzone from previous allocation as its size
402 * depends on the number of tx and rx queues, which could be different
403 * from one config to another.
405 mz = gpa_zone_reserve(dev, size, "queuedesc", rte_socket_id(),
406 VMXNET3_QUEUE_DESC_ALIGN, 0);
408 PMD_INIT_LOG(ERR, "ERROR: Creating queue descriptors zone");
411 memset(mz->addr, 0, mz->len);
413 hw->tqd_start = (Vmxnet3_TxQueueDesc *)mz->addr;
414 hw->rqd_start = (Vmxnet3_RxQueueDesc *)(hw->tqd_start + hw->num_tx_queues);
416 hw->queueDescPA = mz->phys_addr;
417 hw->queue_desc_len = (uint16_t)size;
419 if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_RSS) {
420 /* Allocate memory structure for UPT1_RSSConf and configure */
421 mz = gpa_zone_reserve(dev, sizeof(struct VMXNET3_RSSConf),
422 "rss_conf", rte_socket_id(),
423 RTE_CACHE_LINE_SIZE, 1);
426 "ERROR: Creating rss_conf structure zone");
429 memset(mz->addr, 0, mz->len);
431 hw->rss_conf = mz->addr;
432 hw->rss_confPA = mz->phys_addr;
439 vmxnet3_write_mac(struct vmxnet3_hw *hw, const uint8_t *addr)
444 "Writing MAC Address : %02x:%02x:%02x:%02x:%02x:%02x",
445 addr[0], addr[1], addr[2],
446 addr[3], addr[4], addr[5]);
448 val = *(const uint32_t *)addr;
449 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_MACL, val);
451 val = (addr[5] << 8) | addr[4];
452 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_MACH, val);
456 vmxnet3_setup_driver_shared(struct rte_eth_dev *dev)
458 struct rte_eth_conf port_conf = dev->data->dev_conf;
459 struct vmxnet3_hw *hw = dev->data->dev_private;
460 uint32_t mtu = dev->data->mtu;
461 Vmxnet3_DriverShared *shared = hw->shared;
462 Vmxnet3_DSDevRead *devRead = &shared->devRead;
466 shared->magic = VMXNET3_REV1_MAGIC;
467 devRead->misc.driverInfo.version = VMXNET3_DRIVER_VERSION_NUM;
469 /* Setting up Guest OS information */
470 devRead->misc.driverInfo.gos.gosBits = sizeof(void *) == 4 ?
471 VMXNET3_GOS_BITS_32 : VMXNET3_GOS_BITS_64;
472 devRead->misc.driverInfo.gos.gosType = VMXNET3_GOS_TYPE_LINUX;
473 devRead->misc.driverInfo.vmxnet3RevSpt = 1;
474 devRead->misc.driverInfo.uptVerSpt = 1;
476 devRead->misc.mtu = rte_le_to_cpu_32(mtu);
477 devRead->misc.queueDescPA = hw->queueDescPA;
478 devRead->misc.queueDescLen = hw->queue_desc_len;
479 devRead->misc.numTxQueues = hw->num_tx_queues;
480 devRead->misc.numRxQueues = hw->num_rx_queues;
483 * Set number of interrupts to 1
484 * PMD disables all the interrupts but this is MUST to activate device
485 * It needs at least one interrupt for link events to handle
486 * So we'll disable it later after device activation if needed
488 devRead->intrConf.numIntrs = 1;
489 devRead->intrConf.intrCtrl |= VMXNET3_IC_DISABLE_ALL;
491 for (i = 0; i < hw->num_tx_queues; i++) {
492 Vmxnet3_TxQueueDesc *tqd = &hw->tqd_start[i];
493 vmxnet3_tx_queue_t *txq = dev->data->tx_queues[i];
495 tqd->ctrl.txNumDeferred = 0;
496 tqd->ctrl.txThreshold = 1;
497 tqd->conf.txRingBasePA = txq->cmd_ring.basePA;
498 tqd->conf.compRingBasePA = txq->comp_ring.basePA;
499 tqd->conf.dataRingBasePA = txq->data_ring.basePA;
501 tqd->conf.txRingSize = txq->cmd_ring.size;
502 tqd->conf.compRingSize = txq->comp_ring.size;
503 tqd->conf.dataRingSize = txq->data_ring.size;
504 tqd->conf.intrIdx = txq->comp_ring.intr_idx;
505 tqd->status.stopped = TRUE;
506 tqd->status.error = 0;
507 memset(&tqd->stats, 0, sizeof(tqd->stats));
510 for (i = 0; i < hw->num_rx_queues; i++) {
511 Vmxnet3_RxQueueDesc *rqd = &hw->rqd_start[i];
512 vmxnet3_rx_queue_t *rxq = dev->data->rx_queues[i];
514 rqd->conf.rxRingBasePA[0] = rxq->cmd_ring[0].basePA;
515 rqd->conf.rxRingBasePA[1] = rxq->cmd_ring[1].basePA;
516 rqd->conf.compRingBasePA = rxq->comp_ring.basePA;
518 rqd->conf.rxRingSize[0] = rxq->cmd_ring[0].size;
519 rqd->conf.rxRingSize[1] = rxq->cmd_ring[1].size;
520 rqd->conf.compRingSize = rxq->comp_ring.size;
521 rqd->conf.intrIdx = rxq->comp_ring.intr_idx;
522 rqd->status.stopped = TRUE;
523 rqd->status.error = 0;
524 memset(&rqd->stats, 0, sizeof(rqd->stats));
527 /* RxMode set to 0 of VMXNET3_RXM_xxx */
528 devRead->rxFilterConf.rxMode = 0;
530 /* Setting up feature flags */
531 if (dev->data->dev_conf.rxmode.hw_ip_checksum)
532 devRead->misc.uptFeatures |= VMXNET3_F_RXCSUM;
534 if (dev->data->dev_conf.rxmode.enable_lro) {
535 devRead->misc.uptFeatures |= VMXNET3_F_LRO;
536 devRead->misc.maxNumRxSG = 0;
539 if (port_conf.rxmode.mq_mode == ETH_MQ_RX_RSS) {
540 ret = vmxnet3_rss_configure(dev);
541 if (ret != VMXNET3_SUCCESS)
544 devRead->misc.uptFeatures |= VMXNET3_F_RSS;
545 devRead->rssConfDesc.confVer = 1;
546 devRead->rssConfDesc.confLen = sizeof(struct VMXNET3_RSSConf);
547 devRead->rssConfDesc.confPA = hw->rss_confPA;
550 vmxnet3_dev_vlan_offload_set(dev,
551 ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK);
553 vmxnet3_write_mac(hw, hw->perm_addr);
555 return VMXNET3_SUCCESS;
559 * Configure device link speed and setup link.
560 * Must be called after eth_vmxnet3_dev_init. Other wise it might fail
561 * It returns 0 on success.
564 vmxnet3_dev_start(struct rte_eth_dev *dev)
567 struct vmxnet3_hw *hw = dev->data->dev_private;
569 PMD_INIT_FUNC_TRACE();
571 ret = vmxnet3_setup_driver_shared(dev);
572 if (ret != VMXNET3_SUCCESS)
575 /* Exchange shared data with device */
576 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_DSAL,
577 VMXNET3_GET_ADDR_LO(hw->sharedPA));
578 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_DSAH,
579 VMXNET3_GET_ADDR_HI(hw->sharedPA));
581 /* Activate device by register write */
582 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, VMXNET3_CMD_ACTIVATE_DEV);
583 ret = VMXNET3_READ_BAR1_REG(hw, VMXNET3_REG_CMD);
586 PMD_INIT_LOG(ERR, "Device activation: UNSUCCESSFUL");
590 /* Disable interrupts */
591 vmxnet3_disable_intr(hw);
594 * Load RX queues with blank mbufs and update next2fill index for device
595 * Update RxMode of the device
597 ret = vmxnet3_dev_rxtx_init(dev);
598 if (ret != VMXNET3_SUCCESS) {
599 PMD_INIT_LOG(ERR, "Device queue init: UNSUCCESSFUL");
603 /* Setting proper Rx Mode and issue Rx Mode Update command */
604 vmxnet3_dev_set_rxmode(hw, VMXNET3_RXM_UCAST | VMXNET3_RXM_BCAST, 1);
607 * Don't need to handle events for now
609 #if PROCESS_SYS_EVENTS == 1
610 events = VMXNET3_READ_BAR1_REG(hw, VMXNET3_REG_ECR);
611 PMD_INIT_LOG(DEBUG, "Reading events: 0x%X", events);
612 vmxnet3_process_events(hw);
614 return VMXNET3_SUCCESS;
618 * Stop device: disable rx and tx functions to allow for reconfiguring.
621 vmxnet3_dev_stop(struct rte_eth_dev *dev)
623 struct rte_eth_link link;
624 struct vmxnet3_hw *hw = dev->data->dev_private;
626 PMD_INIT_FUNC_TRACE();
628 if (hw->adapter_stopped == 1) {
629 PMD_INIT_LOG(DEBUG, "Device already closed.");
633 /* disable interrupts */
634 vmxnet3_disable_intr(hw);
636 /* quiesce the device first */
637 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, VMXNET3_CMD_QUIESCE_DEV);
638 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_DSAL, 0);
639 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_DSAH, 0);
641 /* reset the device */
642 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, VMXNET3_CMD_RESET_DEV);
643 PMD_INIT_LOG(DEBUG, "Device reset.");
644 hw->adapter_stopped = 0;
646 vmxnet3_dev_clear_queues(dev);
648 /* Clear recorded link status */
649 memset(&link, 0, sizeof(link));
650 vmxnet3_dev_atomic_write_link_status(dev, &link);
654 * Reset and stop device.
657 vmxnet3_dev_close(struct rte_eth_dev *dev)
659 struct vmxnet3_hw *hw = dev->data->dev_private;
661 PMD_INIT_FUNC_TRACE();
663 vmxnet3_dev_stop(dev);
664 hw->adapter_stopped = 1;
668 vmxnet3_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
671 struct vmxnet3_hw *hw = dev->data->dev_private;
673 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, VMXNET3_CMD_GET_STATS);
675 RTE_BUILD_BUG_ON(RTE_ETHDEV_QUEUE_STAT_CNTRS < VMXNET3_MAX_TX_QUEUES);
676 for (i = 0; i < hw->num_tx_queues; i++) {
677 struct UPT1_TxStats *txStats = &hw->tqd_start[i].stats;
679 stats->q_opackets[i] = txStats->ucastPktsTxOK +
680 txStats->mcastPktsTxOK +
681 txStats->bcastPktsTxOK;
682 stats->q_obytes[i] = txStats->ucastBytesTxOK +
683 txStats->mcastBytesTxOK +
684 txStats->bcastBytesTxOK;
686 stats->opackets += stats->q_opackets[i];
687 stats->obytes += stats->q_obytes[i];
688 stats->oerrors += txStats->pktsTxError + txStats->pktsTxDiscard;
691 RTE_BUILD_BUG_ON(RTE_ETHDEV_QUEUE_STAT_CNTRS < VMXNET3_MAX_RX_QUEUES);
692 for (i = 0; i < hw->num_rx_queues; i++) {
693 struct UPT1_RxStats *rxStats = &hw->rqd_start[i].stats;
695 stats->q_ipackets[i] = rxStats->ucastPktsRxOK +
696 rxStats->mcastPktsRxOK +
697 rxStats->bcastPktsRxOK;
699 stats->q_ibytes[i] = rxStats->ucastBytesRxOK +
700 rxStats->mcastBytesRxOK +
701 rxStats->bcastBytesRxOK;
703 stats->ipackets += stats->q_ipackets[i];
704 stats->ibytes += stats->q_ibytes[i];
706 stats->q_errors[i] = rxStats->pktsRxError;
707 stats->ierrors += rxStats->pktsRxError;
708 stats->rx_nombuf += rxStats->pktsRxOutOfBuf;
713 vmxnet3_dev_info_get(struct rte_eth_dev *dev,
714 struct rte_eth_dev_info *dev_info)
716 dev_info->pci_dev = RTE_DEV_TO_PCI(dev->device);
718 dev_info->max_rx_queues = VMXNET3_MAX_RX_QUEUES;
719 dev_info->max_tx_queues = VMXNET3_MAX_TX_QUEUES;
720 dev_info->min_rx_bufsize = 1518 + RTE_PKTMBUF_HEADROOM;
721 dev_info->max_rx_pktlen = 16384; /* includes CRC, cf MAXFRS register */
722 dev_info->max_mac_addrs = VMXNET3_MAX_MAC_ADDRS;
724 dev_info->default_txconf.txq_flags = ETH_TXQ_FLAGS_NOXSUMSCTP;
725 dev_info->flow_type_rss_offloads = VMXNET3_RSS_OFFLOAD_ALL;
727 dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
728 .nb_max = VMXNET3_RX_RING_MAX_SIZE,
729 .nb_min = VMXNET3_DEF_RX_RING_SIZE,
733 dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
734 .nb_max = VMXNET3_TX_RING_MAX_SIZE,
735 .nb_min = VMXNET3_DEF_TX_RING_SIZE,
737 .nb_seg_max = VMXNET3_TX_MAX_SEG,
738 .nb_mtu_seg_max = VMXNET3_MAX_TXD_PER_PKT,
741 dev_info->rx_offload_capa =
742 DEV_RX_OFFLOAD_VLAN_STRIP |
743 DEV_RX_OFFLOAD_UDP_CKSUM |
744 DEV_RX_OFFLOAD_TCP_CKSUM |
745 DEV_RX_OFFLOAD_TCP_LRO;
747 dev_info->tx_offload_capa =
748 DEV_TX_OFFLOAD_VLAN_INSERT |
749 DEV_TX_OFFLOAD_TCP_CKSUM |
750 DEV_TX_OFFLOAD_UDP_CKSUM |
751 DEV_TX_OFFLOAD_TCP_TSO;
754 static const uint32_t *
755 vmxnet3_dev_supported_ptypes_get(struct rte_eth_dev *dev)
757 static const uint32_t ptypes[] = {
758 RTE_PTYPE_L3_IPV4_EXT,
763 if (dev->rx_pkt_burst == vmxnet3_recv_pkts)
769 vmxnet3_mac_addr_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr)
771 struct vmxnet3_hw *hw = dev->data->dev_private;
773 vmxnet3_write_mac(hw, mac_addr->addr_bytes);
776 /* return 0 means link status changed, -1 means not changed */
778 vmxnet3_dev_link_update(struct rte_eth_dev *dev,
779 __rte_unused int wait_to_complete)
781 struct vmxnet3_hw *hw = dev->data->dev_private;
782 struct rte_eth_link old, link;
785 /* Link status doesn't change for stopped dev */
786 if (dev->data->dev_started == 0)
789 memset(&link, 0, sizeof(link));
790 vmxnet3_dev_atomic_read_link_status(dev, &old);
792 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, VMXNET3_CMD_GET_LINK);
793 ret = VMXNET3_READ_BAR1_REG(hw, VMXNET3_REG_CMD);
796 link.link_status = ETH_LINK_UP;
797 link.link_duplex = ETH_LINK_FULL_DUPLEX;
798 link.link_speed = ETH_SPEED_NUM_10G;
799 link.link_autoneg = ETH_LINK_SPEED_FIXED;
802 vmxnet3_dev_atomic_write_link_status(dev, &link);
804 return (old.link_status == link.link_status) ? -1 : 0;
807 /* Updating rxmode through Vmxnet3_DriverShared structure in adapter */
809 vmxnet3_dev_set_rxmode(struct vmxnet3_hw *hw, uint32_t feature, int set)
811 struct Vmxnet3_RxFilterConf *rxConf = &hw->shared->devRead.rxFilterConf;
814 rxConf->rxMode = rxConf->rxMode | feature;
816 rxConf->rxMode = rxConf->rxMode & (~feature);
818 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, VMXNET3_CMD_UPDATE_RX_MODE);
821 /* Promiscuous supported only if Vmxnet3_DriverShared is initialized in adapter */
823 vmxnet3_dev_promiscuous_enable(struct rte_eth_dev *dev)
825 struct vmxnet3_hw *hw = dev->data->dev_private;
826 uint32_t *vf_table = hw->shared->devRead.rxFilterConf.vfTable;
828 memset(vf_table, 0, VMXNET3_VFT_TABLE_SIZE);
829 vmxnet3_dev_set_rxmode(hw, VMXNET3_RXM_PROMISC, 1);
831 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD,
832 VMXNET3_CMD_UPDATE_VLAN_FILTERS);
835 /* Promiscuous supported only if Vmxnet3_DriverShared is initialized in adapter */
837 vmxnet3_dev_promiscuous_disable(struct rte_eth_dev *dev)
839 struct vmxnet3_hw *hw = dev->data->dev_private;
840 uint32_t *vf_table = hw->shared->devRead.rxFilterConf.vfTable;
842 memcpy(vf_table, hw->shadow_vfta, VMXNET3_VFT_TABLE_SIZE);
843 vmxnet3_dev_set_rxmode(hw, VMXNET3_RXM_PROMISC, 0);
844 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD,
845 VMXNET3_CMD_UPDATE_VLAN_FILTERS);
848 /* Allmulticast supported only if Vmxnet3_DriverShared is initialized in adapter */
850 vmxnet3_dev_allmulticast_enable(struct rte_eth_dev *dev)
852 struct vmxnet3_hw *hw = dev->data->dev_private;
854 vmxnet3_dev_set_rxmode(hw, VMXNET3_RXM_ALL_MULTI, 1);
857 /* Allmulticast supported only if Vmxnet3_DriverShared is initialized in adapter */
859 vmxnet3_dev_allmulticast_disable(struct rte_eth_dev *dev)
861 struct vmxnet3_hw *hw = dev->data->dev_private;
863 vmxnet3_dev_set_rxmode(hw, VMXNET3_RXM_ALL_MULTI, 0);
866 /* Enable/disable filter on vlan */
868 vmxnet3_dev_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vid, int on)
870 struct vmxnet3_hw *hw = dev->data->dev_private;
871 struct Vmxnet3_RxFilterConf *rxConf = &hw->shared->devRead.rxFilterConf;
872 uint32_t *vf_table = rxConf->vfTable;
874 /* save state for restore */
876 VMXNET3_SET_VFTABLE_ENTRY(hw->shadow_vfta, vid);
878 VMXNET3_CLEAR_VFTABLE_ENTRY(hw->shadow_vfta, vid);
880 /* don't change active filter if in promiscuous mode */
881 if (rxConf->rxMode & VMXNET3_RXM_PROMISC)
884 /* set in hardware */
886 VMXNET3_SET_VFTABLE_ENTRY(vf_table, vid);
888 VMXNET3_CLEAR_VFTABLE_ENTRY(vf_table, vid);
890 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD,
891 VMXNET3_CMD_UPDATE_VLAN_FILTERS);
896 vmxnet3_dev_vlan_offload_set(struct rte_eth_dev *dev, int mask)
898 struct vmxnet3_hw *hw = dev->data->dev_private;
899 Vmxnet3_DSDevRead *devRead = &hw->shared->devRead;
900 uint32_t *vf_table = devRead->rxFilterConf.vfTable;
902 if (mask & ETH_VLAN_STRIP_MASK) {
903 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
904 devRead->misc.uptFeatures |= UPT1_F_RXVLAN;
906 devRead->misc.uptFeatures &= ~UPT1_F_RXVLAN;
908 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD,
909 VMXNET3_CMD_UPDATE_FEATURE);
912 if (mask & ETH_VLAN_FILTER_MASK) {
913 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
914 memcpy(vf_table, hw->shadow_vfta, VMXNET3_VFT_TABLE_SIZE);
916 memset(vf_table, 0xff, VMXNET3_VFT_TABLE_SIZE);
918 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD,
919 VMXNET3_CMD_UPDATE_VLAN_FILTERS);
923 #if PROCESS_SYS_EVENTS == 1
925 vmxnet3_process_events(struct vmxnet3_hw *hw)
927 uint32_t events = hw->shared->ecr;
930 PMD_INIT_LOG(ERR, "No events to process");
935 * ECR bits when written with 1b are cleared. Hence write
936 * events back to ECR so that the bits which were set will be reset.
938 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_ECR, events);
940 /* Check if link state has changed */
941 if (events & VMXNET3_ECR_LINK)
943 "Process events in %s(): VMXNET3_ECR_LINK event",
946 /* Check if there is an error on xmit/recv queues */
947 if (events & (VMXNET3_ECR_TQERR | VMXNET3_ECR_RQERR)) {
948 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD,
949 VMXNET3_CMD_GET_QUEUE_STATUS);
951 if (hw->tqd_start->status.stopped)
952 PMD_INIT_LOG(ERR, "tq error 0x%x",
953 hw->tqd_start->status.error);
955 if (hw->rqd_start->status.stopped)
956 PMD_INIT_LOG(ERR, "rq error 0x%x",
957 hw->rqd_start->status.error);
959 /* Reset the device */
960 /* Have to reset the device */
963 if (events & VMXNET3_ECR_DIC)
964 PMD_INIT_LOG(ERR, "Device implementation change event.");
966 if (events & VMXNET3_ECR_DEBUG)
967 PMD_INIT_LOG(ERR, "Debug event generated by device.");
971 RTE_PMD_REGISTER_PCI(net_vmxnet3, rte_vmxnet3_pmd.pci_drv);
972 RTE_PMD_REGISTER_PCI_TABLE(net_vmxnet3, pci_id_vmxnet3_map);
973 RTE_PMD_REGISTER_KMOD_DEP(net_vmxnet3, "* igb_uio | uio_pci_generic | vfio");