1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2010-2015 Intel Corporation
14 #include <rte_byteorder.h>
15 #include <rte_common.h>
16 #include <rte_cycles.h>
18 #include <rte_interrupts.h>
20 #include <rte_debug.h>
22 #include <rte_bus_pci.h>
23 #include <rte_branch_prediction.h>
24 #include <rte_memory.h>
25 #include <rte_memzone.h>
27 #include <rte_alarm.h>
28 #include <rte_ether.h>
29 #include <rte_ethdev_driver.h>
30 #include <rte_ethdev_pci.h>
31 #include <rte_string_fns.h>
32 #include <rte_malloc.h>
35 #include "base/vmxnet3_defs.h"
37 #include "vmxnet3_ring.h"
38 #include "vmxnet3_logs.h"
39 #include "vmxnet3_ethdev.h"
41 #define PROCESS_SYS_EVENTS 0
43 #define VMXNET3_TX_MAX_SEG UINT8_MAX
45 #define VMXNET3_TX_OFFLOAD_CAP \
46 (DEV_TX_OFFLOAD_VLAN_INSERT | \
47 DEV_TX_OFFLOAD_IPV4_CKSUM | \
48 DEV_TX_OFFLOAD_TCP_CKSUM | \
49 DEV_TX_OFFLOAD_UDP_CKSUM | \
50 DEV_TX_OFFLOAD_TCP_TSO | \
51 DEV_TX_OFFLOAD_MULTI_SEGS)
53 #define VMXNET3_RX_OFFLOAD_CAP \
54 (DEV_RX_OFFLOAD_VLAN_STRIP | \
55 DEV_RX_OFFLOAD_SCATTER | \
56 DEV_RX_OFFLOAD_IPV4_CKSUM | \
57 DEV_RX_OFFLOAD_UDP_CKSUM | \
58 DEV_RX_OFFLOAD_TCP_CKSUM | \
59 DEV_RX_OFFLOAD_TCP_LRO | \
60 DEV_RX_OFFLOAD_JUMBO_FRAME)
62 static int eth_vmxnet3_dev_init(struct rte_eth_dev *eth_dev);
63 static int eth_vmxnet3_dev_uninit(struct rte_eth_dev *eth_dev);
64 static int vmxnet3_dev_configure(struct rte_eth_dev *dev);
65 static int vmxnet3_dev_start(struct rte_eth_dev *dev);
66 static void vmxnet3_dev_stop(struct rte_eth_dev *dev);
67 static void vmxnet3_dev_close(struct rte_eth_dev *dev);
68 static void vmxnet3_dev_set_rxmode(struct vmxnet3_hw *hw, uint32_t feature, int set);
69 static void vmxnet3_dev_promiscuous_enable(struct rte_eth_dev *dev);
70 static void vmxnet3_dev_promiscuous_disable(struct rte_eth_dev *dev);
71 static void vmxnet3_dev_allmulticast_enable(struct rte_eth_dev *dev);
72 static void vmxnet3_dev_allmulticast_disable(struct rte_eth_dev *dev);
73 static int __vmxnet3_dev_link_update(struct rte_eth_dev *dev,
74 int wait_to_complete);
75 static int vmxnet3_dev_link_update(struct rte_eth_dev *dev,
76 int wait_to_complete);
77 static void vmxnet3_hw_stats_save(struct vmxnet3_hw *hw);
78 static int vmxnet3_dev_stats_get(struct rte_eth_dev *dev,
79 struct rte_eth_stats *stats);
80 static void vmxnet3_dev_stats_reset(struct rte_eth_dev *dev);
81 static int vmxnet3_dev_xstats_get_names(struct rte_eth_dev *dev,
82 struct rte_eth_xstat_name *xstats,
84 static int vmxnet3_dev_xstats_get(struct rte_eth_dev *dev,
85 struct rte_eth_xstat *xstats, unsigned int n);
86 static void vmxnet3_dev_info_get(struct rte_eth_dev *dev,
87 struct rte_eth_dev_info *dev_info);
88 static const uint32_t *
89 vmxnet3_dev_supported_ptypes_get(struct rte_eth_dev *dev);
90 static int vmxnet3_dev_vlan_filter_set(struct rte_eth_dev *dev,
91 uint16_t vid, int on);
92 static int vmxnet3_dev_vlan_offload_set(struct rte_eth_dev *dev, int mask);
93 static int vmxnet3_mac_addr_set(struct rte_eth_dev *dev,
94 struct ether_addr *mac_addr);
95 static void vmxnet3_interrupt_handler(void *param);
97 int vmxnet3_logtype_init;
98 int vmxnet3_logtype_driver;
101 * The set of PCI devices this driver supports
103 #define VMWARE_PCI_VENDOR_ID 0x15AD
104 #define VMWARE_DEV_ID_VMXNET3 0x07B0
105 static const struct rte_pci_id pci_id_vmxnet3_map[] = {
106 { RTE_PCI_DEVICE(VMWARE_PCI_VENDOR_ID, VMWARE_DEV_ID_VMXNET3) },
107 { .vendor_id = 0, /* sentinel */ },
110 static const struct eth_dev_ops vmxnet3_eth_dev_ops = {
111 .dev_configure = vmxnet3_dev_configure,
112 .dev_start = vmxnet3_dev_start,
113 .dev_stop = vmxnet3_dev_stop,
114 .dev_close = vmxnet3_dev_close,
115 .promiscuous_enable = vmxnet3_dev_promiscuous_enable,
116 .promiscuous_disable = vmxnet3_dev_promiscuous_disable,
117 .allmulticast_enable = vmxnet3_dev_allmulticast_enable,
118 .allmulticast_disable = vmxnet3_dev_allmulticast_disable,
119 .link_update = vmxnet3_dev_link_update,
120 .stats_get = vmxnet3_dev_stats_get,
121 .xstats_get_names = vmxnet3_dev_xstats_get_names,
122 .xstats_get = vmxnet3_dev_xstats_get,
123 .stats_reset = vmxnet3_dev_stats_reset,
124 .mac_addr_set = vmxnet3_mac_addr_set,
125 .dev_infos_get = vmxnet3_dev_info_get,
126 .dev_supported_ptypes_get = vmxnet3_dev_supported_ptypes_get,
127 .vlan_filter_set = vmxnet3_dev_vlan_filter_set,
128 .vlan_offload_set = vmxnet3_dev_vlan_offload_set,
129 .rx_queue_setup = vmxnet3_dev_rx_queue_setup,
130 .rx_queue_release = vmxnet3_dev_rx_queue_release,
131 .tx_queue_setup = vmxnet3_dev_tx_queue_setup,
132 .tx_queue_release = vmxnet3_dev_tx_queue_release,
135 struct vmxnet3_xstats_name_off {
136 char name[RTE_ETH_XSTATS_NAME_SIZE];
140 /* tx_qX_ is prepended to the name string here */
141 static const struct vmxnet3_xstats_name_off vmxnet3_txq_stat_strings[] = {
142 {"drop_total", offsetof(struct vmxnet3_txq_stats, drop_total)},
143 {"drop_too_many_segs", offsetof(struct vmxnet3_txq_stats, drop_too_many_segs)},
144 {"drop_tso", offsetof(struct vmxnet3_txq_stats, drop_tso)},
145 {"tx_ring_full", offsetof(struct vmxnet3_txq_stats, tx_ring_full)},
148 /* rx_qX_ is prepended to the name string here */
149 static const struct vmxnet3_xstats_name_off vmxnet3_rxq_stat_strings[] = {
150 {"drop_total", offsetof(struct vmxnet3_rxq_stats, drop_total)},
151 {"drop_err", offsetof(struct vmxnet3_rxq_stats, drop_err)},
152 {"drop_fcs", offsetof(struct vmxnet3_rxq_stats, drop_fcs)},
153 {"rx_buf_alloc_failure", offsetof(struct vmxnet3_rxq_stats, rx_buf_alloc_failure)},
156 static const struct rte_memzone *
157 gpa_zone_reserve(struct rte_eth_dev *dev, uint32_t size,
158 const char *post_string, int socket_id,
159 uint16_t align, bool reuse)
161 char z_name[RTE_MEMZONE_NAMESIZE];
162 const struct rte_memzone *mz;
164 snprintf(z_name, sizeof(z_name), "eth_p%d_%s",
165 dev->data->port_id, post_string);
167 mz = rte_memzone_lookup(z_name);
170 rte_memzone_free(mz);
171 return rte_memzone_reserve_aligned(z_name, size, socket_id,
172 RTE_MEMZONE_IOVA_CONTIG, align);
178 return rte_memzone_reserve_aligned(z_name, size, socket_id,
179 RTE_MEMZONE_IOVA_CONTIG, align);
183 * This function is based on vmxnet3_disable_intr()
186 vmxnet3_disable_intr(struct vmxnet3_hw *hw)
190 PMD_INIT_FUNC_TRACE();
192 hw->shared->devRead.intrConf.intrCtrl |= VMXNET3_IC_DISABLE_ALL;
193 for (i = 0; i < hw->num_intrs; i++)
194 VMXNET3_WRITE_BAR0_REG(hw, VMXNET3_REG_IMR + i * 8, 1);
198 vmxnet3_enable_intr(struct vmxnet3_hw *hw)
202 PMD_INIT_FUNC_TRACE();
204 hw->shared->devRead.intrConf.intrCtrl &= ~VMXNET3_IC_DISABLE_ALL;
205 for (i = 0; i < hw->num_intrs; i++)
206 VMXNET3_WRITE_BAR0_REG(hw, VMXNET3_REG_IMR + i * 8, 0);
210 * Gets tx data ring descriptor size.
213 eth_vmxnet3_txdata_get(struct vmxnet3_hw *hw)
215 uint16 txdata_desc_size;
217 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD,
218 VMXNET3_CMD_GET_TXDATA_DESC_SIZE);
219 txdata_desc_size = VMXNET3_READ_BAR1_REG(hw, VMXNET3_REG_CMD);
221 return (txdata_desc_size < VMXNET3_TXDATA_DESC_MIN_SIZE ||
222 txdata_desc_size > VMXNET3_TXDATA_DESC_MAX_SIZE ||
223 txdata_desc_size & VMXNET3_TXDATA_DESC_SIZE_MASK) ?
224 sizeof(struct Vmxnet3_TxDataDesc) : txdata_desc_size;
228 * It returns 0 on success.
231 eth_vmxnet3_dev_init(struct rte_eth_dev *eth_dev)
233 struct rte_pci_device *pci_dev;
234 struct vmxnet3_hw *hw = eth_dev->data->dev_private;
235 uint32_t mac_hi, mac_lo, ver;
236 struct rte_eth_link link;
238 PMD_INIT_FUNC_TRACE();
240 eth_dev->dev_ops = &vmxnet3_eth_dev_ops;
241 eth_dev->rx_pkt_burst = &vmxnet3_recv_pkts;
242 eth_dev->tx_pkt_burst = &vmxnet3_xmit_pkts;
243 eth_dev->tx_pkt_prepare = vmxnet3_prep_pkts;
244 pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
247 * for secondary processes, we don't initialize any further as primary
248 * has already done this work.
250 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
253 rte_eth_copy_pci_info(eth_dev, pci_dev);
255 /* Vendor and Device ID need to be set before init of shared code */
256 hw->device_id = pci_dev->id.device_id;
257 hw->vendor_id = pci_dev->id.vendor_id;
258 hw->hw_addr0 = (void *)pci_dev->mem_resource[0].addr;
259 hw->hw_addr1 = (void *)pci_dev->mem_resource[1].addr;
261 hw->num_rx_queues = 1;
262 hw->num_tx_queues = 1;
263 hw->bufs_per_pkt = 1;
265 /* Check h/w version compatibility with driver. */
266 ver = VMXNET3_READ_BAR1_REG(hw, VMXNET3_REG_VRRS);
267 PMD_INIT_LOG(DEBUG, "Hardware version : %d", ver);
269 if (ver & (1 << VMXNET3_REV_3)) {
270 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_VRRS,
272 hw->version = VMXNET3_REV_3 + 1;
273 } else if (ver & (1 << VMXNET3_REV_2)) {
274 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_VRRS,
276 hw->version = VMXNET3_REV_2 + 1;
277 } else if (ver & (1 << VMXNET3_REV_1)) {
278 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_VRRS,
280 hw->version = VMXNET3_REV_1 + 1;
282 PMD_INIT_LOG(ERR, "Incompatible hardware version: %d", ver);
286 PMD_INIT_LOG(DEBUG, "Using device version %d\n", hw->version);
288 /* Check UPT version compatibility with driver. */
289 ver = VMXNET3_READ_BAR1_REG(hw, VMXNET3_REG_UVRS);
290 PMD_INIT_LOG(DEBUG, "UPT hardware version : %d", ver);
292 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_UVRS, 1);
294 PMD_INIT_LOG(ERR, "Incompatible UPT version.");
298 /* Getting MAC Address */
299 mac_lo = VMXNET3_READ_BAR1_REG(hw, VMXNET3_REG_MACL);
300 mac_hi = VMXNET3_READ_BAR1_REG(hw, VMXNET3_REG_MACH);
301 memcpy(hw->perm_addr, &mac_lo, 4);
302 memcpy(hw->perm_addr + 4, &mac_hi, 2);
304 /* Allocate memory for storing MAC addresses */
305 eth_dev->data->mac_addrs = rte_zmalloc("vmxnet3", ETHER_ADDR_LEN *
306 VMXNET3_MAX_MAC_ADDRS, 0);
307 if (eth_dev->data->mac_addrs == NULL) {
309 "Failed to allocate %d bytes needed to store MAC addresses",
310 ETHER_ADDR_LEN * VMXNET3_MAX_MAC_ADDRS);
313 /* Copy the permanent MAC address */
314 ether_addr_copy((struct ether_addr *) hw->perm_addr,
315 ð_dev->data->mac_addrs[0]);
317 PMD_INIT_LOG(DEBUG, "MAC Address : %02x:%02x:%02x:%02x:%02x:%02x",
318 hw->perm_addr[0], hw->perm_addr[1], hw->perm_addr[2],
319 hw->perm_addr[3], hw->perm_addr[4], hw->perm_addr[5]);
321 /* Flag to call rte_eth_dev_release_port() in rte_eth_dev_close(). */
322 eth_dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE;
324 /* Put device in Quiesce Mode */
325 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, VMXNET3_CMD_QUIESCE_DEV);
327 /* allow untagged pkts */
328 VMXNET3_SET_VFTABLE_ENTRY(hw->shadow_vfta, 0);
330 hw->txdata_desc_size = VMXNET3_VERSION_GE_3(hw) ?
331 eth_vmxnet3_txdata_get(hw) : sizeof(struct Vmxnet3_TxDataDesc);
333 hw->rxdata_desc_size = VMXNET3_VERSION_GE_3(hw) ?
334 VMXNET3_DEF_RXDATA_DESC_SIZE : 0;
335 RTE_ASSERT((hw->rxdata_desc_size & ~VMXNET3_RXDATA_DESC_SIZE_MASK) ==
336 hw->rxdata_desc_size);
338 /* clear shadow stats */
339 memset(hw->saved_tx_stats, 0, sizeof(hw->saved_tx_stats));
340 memset(hw->saved_rx_stats, 0, sizeof(hw->saved_rx_stats));
342 /* clear snapshot stats */
343 memset(hw->snapshot_tx_stats, 0, sizeof(hw->snapshot_tx_stats));
344 memset(hw->snapshot_rx_stats, 0, sizeof(hw->snapshot_rx_stats));
346 /* set the initial link status */
347 memset(&link, 0, sizeof(link));
348 link.link_duplex = ETH_LINK_FULL_DUPLEX;
349 link.link_speed = ETH_SPEED_NUM_10G;
350 link.link_autoneg = ETH_LINK_FIXED;
351 rte_eth_linkstatus_set(eth_dev, &link);
357 eth_vmxnet3_dev_uninit(struct rte_eth_dev *eth_dev)
359 struct vmxnet3_hw *hw = eth_dev->data->dev_private;
361 PMD_INIT_FUNC_TRACE();
363 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
366 if (hw->adapter_stopped == 0) {
367 PMD_INIT_LOG(DEBUG, "Device has not been closed.");
371 eth_dev->dev_ops = NULL;
372 eth_dev->rx_pkt_burst = NULL;
373 eth_dev->tx_pkt_burst = NULL;
374 eth_dev->tx_pkt_prepare = NULL;
379 static int eth_vmxnet3_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
380 struct rte_pci_device *pci_dev)
382 return rte_eth_dev_pci_generic_probe(pci_dev,
383 sizeof(struct vmxnet3_hw), eth_vmxnet3_dev_init);
386 static int eth_vmxnet3_pci_remove(struct rte_pci_device *pci_dev)
388 return rte_eth_dev_pci_generic_remove(pci_dev, eth_vmxnet3_dev_uninit);
391 static struct rte_pci_driver rte_vmxnet3_pmd = {
392 .id_table = pci_id_vmxnet3_map,
393 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
394 .probe = eth_vmxnet3_pci_probe,
395 .remove = eth_vmxnet3_pci_remove,
399 vmxnet3_dev_configure(struct rte_eth_dev *dev)
401 const struct rte_memzone *mz;
402 struct vmxnet3_hw *hw = dev->data->dev_private;
405 PMD_INIT_FUNC_TRACE();
407 if (dev->data->nb_tx_queues > VMXNET3_MAX_TX_QUEUES ||
408 dev->data->nb_rx_queues > VMXNET3_MAX_RX_QUEUES) {
409 PMD_INIT_LOG(ERR, "ERROR: Number of queues not supported");
413 if (!rte_is_power_of_2(dev->data->nb_rx_queues)) {
414 PMD_INIT_LOG(ERR, "ERROR: Number of rx queues not power of 2");
418 size = dev->data->nb_rx_queues * sizeof(struct Vmxnet3_TxQueueDesc) +
419 dev->data->nb_tx_queues * sizeof(struct Vmxnet3_RxQueueDesc);
421 if (size > UINT16_MAX)
424 hw->num_rx_queues = (uint8_t)dev->data->nb_rx_queues;
425 hw->num_tx_queues = (uint8_t)dev->data->nb_tx_queues;
428 * Allocate a memzone for Vmxnet3_DriverShared - Vmxnet3_DSDevRead
431 mz = gpa_zone_reserve(dev, sizeof(struct Vmxnet3_DriverShared),
432 "shared", rte_socket_id(), 8, 1);
435 PMD_INIT_LOG(ERR, "ERROR: Creating shared zone");
438 memset(mz->addr, 0, mz->len);
440 hw->shared = mz->addr;
441 hw->sharedPA = mz->iova;
444 * Allocate a memzone for Vmxnet3_RxQueueDesc - Vmxnet3_TxQueueDesc
447 * We cannot reuse this memzone from previous allocation as its size
448 * depends on the number of tx and rx queues, which could be different
449 * from one config to another.
451 mz = gpa_zone_reserve(dev, size, "queuedesc", rte_socket_id(),
452 VMXNET3_QUEUE_DESC_ALIGN, 0);
454 PMD_INIT_LOG(ERR, "ERROR: Creating queue descriptors zone");
457 memset(mz->addr, 0, mz->len);
459 hw->tqd_start = (Vmxnet3_TxQueueDesc *)mz->addr;
460 hw->rqd_start = (Vmxnet3_RxQueueDesc *)(hw->tqd_start + hw->num_tx_queues);
462 hw->queueDescPA = mz->iova;
463 hw->queue_desc_len = (uint16_t)size;
465 if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_RSS) {
466 /* Allocate memory structure for UPT1_RSSConf and configure */
467 mz = gpa_zone_reserve(dev, sizeof(struct VMXNET3_RSSConf),
468 "rss_conf", rte_socket_id(),
469 RTE_CACHE_LINE_SIZE, 1);
472 "ERROR: Creating rss_conf structure zone");
475 memset(mz->addr, 0, mz->len);
477 hw->rss_conf = mz->addr;
478 hw->rss_confPA = mz->iova;
485 vmxnet3_write_mac(struct vmxnet3_hw *hw, const uint8_t *addr)
490 "Writing MAC Address : %02x:%02x:%02x:%02x:%02x:%02x",
491 addr[0], addr[1], addr[2],
492 addr[3], addr[4], addr[5]);
494 memcpy(&val, addr, 4);
495 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_MACL, val);
497 memcpy(&val, addr + 4, 2);
498 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_MACH, val);
502 vmxnet3_dev_setup_memreg(struct rte_eth_dev *dev)
504 struct vmxnet3_hw *hw = dev->data->dev_private;
505 Vmxnet3_DriverShared *shared = hw->shared;
506 Vmxnet3_CmdInfo *cmdInfo;
507 struct rte_mempool *mp[VMXNET3_MAX_RX_QUEUES];
508 uint8_t index[VMXNET3_MAX_RX_QUEUES + VMXNET3_MAX_TX_QUEUES];
509 uint32_t num, i, j, size;
511 if (hw->memRegsPA == 0) {
512 const struct rte_memzone *mz;
514 size = sizeof(Vmxnet3_MemRegs) +
515 (VMXNET3_MAX_RX_QUEUES + VMXNET3_MAX_TX_QUEUES) *
516 sizeof(Vmxnet3_MemoryRegion);
518 mz = gpa_zone_reserve(dev, size, "memRegs", rte_socket_id(), 8,
521 PMD_INIT_LOG(ERR, "ERROR: Creating memRegs zone");
524 memset(mz->addr, 0, mz->len);
525 hw->memRegs = mz->addr;
526 hw->memRegsPA = mz->iova;
529 num = hw->num_rx_queues;
531 for (i = 0; i < num; i++) {
532 vmxnet3_rx_queue_t *rxq = dev->data->rx_queues[i];
539 * The same mempool could be used by multiple queues. In such a case,
540 * remove duplicate mempool entries. Only one entry is kept with
541 * bitmask indicating queues that are using this mempool.
543 for (i = 1; i < num; i++) {
544 for (j = 0; j < i; j++) {
545 if (mp[i] == mp[j]) {
554 for (i = 0; i < num; i++) {
558 Vmxnet3_MemoryRegion *mr = &hw->memRegs->memRegs[j];
561 (uintptr_t)STAILQ_FIRST(&mp[i]->mem_list)->iova;
562 mr->length = STAILQ_FIRST(&mp[i]->mem_list)->len <= INT32_MAX ?
563 STAILQ_FIRST(&mp[i]->mem_list)->len : INT32_MAX;
564 mr->txQueueBits = index[i];
565 mr->rxQueueBits = index[i];
568 "index: %u startPA: %" PRIu64 " length: %u, "
570 j, mr->startPA, mr->length, mr->rxQueueBits);
573 hw->memRegs->numRegs = j;
574 PMD_INIT_LOG(INFO, "numRegs: %u", j);
576 size = sizeof(Vmxnet3_MemRegs) +
577 (j - 1) * sizeof(Vmxnet3_MemoryRegion);
579 cmdInfo = &shared->cu.cmdInfo;
580 cmdInfo->varConf.confVer = 1;
581 cmdInfo->varConf.confLen = size;
582 cmdInfo->varConf.confPA = hw->memRegsPA;
588 vmxnet3_setup_driver_shared(struct rte_eth_dev *dev)
590 struct rte_eth_conf port_conf = dev->data->dev_conf;
591 struct vmxnet3_hw *hw = dev->data->dev_private;
592 uint32_t mtu = dev->data->mtu;
593 Vmxnet3_DriverShared *shared = hw->shared;
594 Vmxnet3_DSDevRead *devRead = &shared->devRead;
595 uint64_t rx_offloads = dev->data->dev_conf.rxmode.offloads;
601 shared->magic = VMXNET3_REV1_MAGIC;
602 devRead->misc.driverInfo.version = VMXNET3_DRIVER_VERSION_NUM;
604 /* Setting up Guest OS information */
605 devRead->misc.driverInfo.gos.gosBits = sizeof(void *) == 4 ?
606 VMXNET3_GOS_BITS_32 : VMXNET3_GOS_BITS_64;
607 devRead->misc.driverInfo.gos.gosType = VMXNET3_GOS_TYPE_LINUX;
608 devRead->misc.driverInfo.vmxnet3RevSpt = 1;
609 devRead->misc.driverInfo.uptVerSpt = 1;
611 devRead->misc.mtu = rte_le_to_cpu_32(mtu);
612 devRead->misc.queueDescPA = hw->queueDescPA;
613 devRead->misc.queueDescLen = hw->queue_desc_len;
614 devRead->misc.numTxQueues = hw->num_tx_queues;
615 devRead->misc.numRxQueues = hw->num_rx_queues;
618 * Set number of interrupts to 1
619 * PMD by default disables all the interrupts but this is MUST
620 * to activate device. It needs at least one interrupt for
621 * link events to handle
623 hw->num_intrs = devRead->intrConf.numIntrs = 1;
624 devRead->intrConf.intrCtrl |= VMXNET3_IC_DISABLE_ALL;
626 for (i = 0; i < hw->num_tx_queues; i++) {
627 Vmxnet3_TxQueueDesc *tqd = &hw->tqd_start[i];
628 vmxnet3_tx_queue_t *txq = dev->data->tx_queues[i];
630 txq->shared = &hw->tqd_start[i];
632 tqd->ctrl.txNumDeferred = 0;
633 tqd->ctrl.txThreshold = 1;
634 tqd->conf.txRingBasePA = txq->cmd_ring.basePA;
635 tqd->conf.compRingBasePA = txq->comp_ring.basePA;
636 tqd->conf.dataRingBasePA = txq->data_ring.basePA;
638 tqd->conf.txRingSize = txq->cmd_ring.size;
639 tqd->conf.compRingSize = txq->comp_ring.size;
640 tqd->conf.dataRingSize = txq->data_ring.size;
641 tqd->conf.txDataRingDescSize = txq->txdata_desc_size;
642 tqd->conf.intrIdx = txq->comp_ring.intr_idx;
643 tqd->status.stopped = TRUE;
644 tqd->status.error = 0;
645 memset(&tqd->stats, 0, sizeof(tqd->stats));
648 for (i = 0; i < hw->num_rx_queues; i++) {
649 Vmxnet3_RxQueueDesc *rqd = &hw->rqd_start[i];
650 vmxnet3_rx_queue_t *rxq = dev->data->rx_queues[i];
652 rxq->shared = &hw->rqd_start[i];
654 rqd->conf.rxRingBasePA[0] = rxq->cmd_ring[0].basePA;
655 rqd->conf.rxRingBasePA[1] = rxq->cmd_ring[1].basePA;
656 rqd->conf.compRingBasePA = rxq->comp_ring.basePA;
658 rqd->conf.rxRingSize[0] = rxq->cmd_ring[0].size;
659 rqd->conf.rxRingSize[1] = rxq->cmd_ring[1].size;
660 rqd->conf.compRingSize = rxq->comp_ring.size;
661 rqd->conf.intrIdx = rxq->comp_ring.intr_idx;
662 if (VMXNET3_VERSION_GE_3(hw)) {
663 rqd->conf.rxDataRingBasePA = rxq->data_ring.basePA;
664 rqd->conf.rxDataRingDescSize = rxq->data_desc_size;
666 rqd->status.stopped = TRUE;
667 rqd->status.error = 0;
668 memset(&rqd->stats, 0, sizeof(rqd->stats));
671 /* RxMode set to 0 of VMXNET3_RXM_xxx */
672 devRead->rxFilterConf.rxMode = 0;
674 /* Setting up feature flags */
675 if (rx_offloads & DEV_RX_OFFLOAD_CHECKSUM)
676 devRead->misc.uptFeatures |= VMXNET3_F_RXCSUM;
678 if (rx_offloads & DEV_RX_OFFLOAD_TCP_LRO) {
679 devRead->misc.uptFeatures |= VMXNET3_F_LRO;
680 devRead->misc.maxNumRxSG = 0;
683 if (port_conf.rxmode.mq_mode == ETH_MQ_RX_RSS) {
684 ret = vmxnet3_rss_configure(dev);
685 if (ret != VMXNET3_SUCCESS)
688 devRead->misc.uptFeatures |= VMXNET3_F_RSS;
689 devRead->rssConfDesc.confVer = 1;
690 devRead->rssConfDesc.confLen = sizeof(struct VMXNET3_RSSConf);
691 devRead->rssConfDesc.confPA = hw->rss_confPA;
694 ret = vmxnet3_dev_vlan_offload_set(dev,
695 ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK);
699 vmxnet3_write_mac(hw, dev->data->mac_addrs->addr_bytes);
701 return VMXNET3_SUCCESS;
705 * Configure device link speed and setup link.
706 * Must be called after eth_vmxnet3_dev_init. Other wise it might fail
707 * It returns 0 on success.
710 vmxnet3_dev_start(struct rte_eth_dev *dev)
713 struct vmxnet3_hw *hw = dev->data->dev_private;
715 PMD_INIT_FUNC_TRACE();
717 /* Save stats before it is reset by CMD_ACTIVATE */
718 vmxnet3_hw_stats_save(hw);
720 ret = vmxnet3_setup_driver_shared(dev);
721 if (ret != VMXNET3_SUCCESS)
724 /* check if lsc interrupt feature is enabled */
725 if (dev->data->dev_conf.intr_conf.lsc) {
726 struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev->device);
728 /* Setup interrupt callback */
729 rte_intr_callback_register(&pci_dev->intr_handle,
730 vmxnet3_interrupt_handler, dev);
732 if (rte_intr_enable(&pci_dev->intr_handle) < 0) {
733 PMD_INIT_LOG(ERR, "interrupt enable failed");
738 /* Exchange shared data with device */
739 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_DSAL,
740 VMXNET3_GET_ADDR_LO(hw->sharedPA));
741 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_DSAH,
742 VMXNET3_GET_ADDR_HI(hw->sharedPA));
744 /* Activate device by register write */
745 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, VMXNET3_CMD_ACTIVATE_DEV);
746 ret = VMXNET3_READ_BAR1_REG(hw, VMXNET3_REG_CMD);
749 PMD_INIT_LOG(ERR, "Device activation: UNSUCCESSFUL");
753 /* Setup memory region for rx buffers */
754 ret = vmxnet3_dev_setup_memreg(dev);
756 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD,
757 VMXNET3_CMD_REGISTER_MEMREGS);
758 ret = VMXNET3_READ_BAR1_REG(hw, VMXNET3_REG_CMD);
761 "Failed in setup memory region cmd\n");
764 PMD_INIT_LOG(DEBUG, "Failed to setup memory region\n");
767 /* Disable interrupts */
768 vmxnet3_disable_intr(hw);
771 * Load RX queues with blank mbufs and update next2fill index for device
772 * Update RxMode of the device
774 ret = vmxnet3_dev_rxtx_init(dev);
775 if (ret != VMXNET3_SUCCESS) {
776 PMD_INIT_LOG(ERR, "Device queue init: UNSUCCESSFUL");
780 hw->adapter_stopped = FALSE;
782 /* Setting proper Rx Mode and issue Rx Mode Update command */
783 vmxnet3_dev_set_rxmode(hw, VMXNET3_RXM_UCAST | VMXNET3_RXM_BCAST, 1);
785 if (dev->data->dev_conf.intr_conf.lsc) {
786 vmxnet3_enable_intr(hw);
789 * Update link state from device since this won't be
790 * done upon starting with lsc in use. This is done
791 * only after enabling interrupts to avoid any race
792 * where the link state could change without an
793 * interrupt being fired.
795 __vmxnet3_dev_link_update(dev, 0);
798 return VMXNET3_SUCCESS;
802 * Stop device: disable rx and tx functions to allow for reconfiguring.
805 vmxnet3_dev_stop(struct rte_eth_dev *dev)
807 struct rte_eth_link link;
808 struct vmxnet3_hw *hw = dev->data->dev_private;
810 PMD_INIT_FUNC_TRACE();
812 if (hw->adapter_stopped == 1) {
813 PMD_INIT_LOG(DEBUG, "Device already stopped.");
817 /* disable interrupts */
818 vmxnet3_disable_intr(hw);
820 if (dev->data->dev_conf.intr_conf.lsc) {
821 struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev->device);
823 rte_intr_disable(&pci_dev->intr_handle);
825 rte_intr_callback_unregister(&pci_dev->intr_handle,
826 vmxnet3_interrupt_handler, dev);
829 /* quiesce the device first */
830 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, VMXNET3_CMD_QUIESCE_DEV);
831 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_DSAL, 0);
832 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_DSAH, 0);
834 /* reset the device */
835 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, VMXNET3_CMD_RESET_DEV);
836 PMD_INIT_LOG(DEBUG, "Device reset.");
838 vmxnet3_dev_clear_queues(dev);
840 /* Clear recorded link status */
841 memset(&link, 0, sizeof(link));
842 link.link_duplex = ETH_LINK_FULL_DUPLEX;
843 link.link_speed = ETH_SPEED_NUM_10G;
844 link.link_autoneg = ETH_LINK_FIXED;
845 rte_eth_linkstatus_set(dev, &link);
847 hw->adapter_stopped = 1;
851 vmxnet3_free_queues(struct rte_eth_dev *dev)
855 PMD_INIT_FUNC_TRACE();
857 for (i = 0; i < dev->data->nb_rx_queues; i++) {
858 void *rxq = dev->data->rx_queues[i];
860 vmxnet3_dev_rx_queue_release(rxq);
862 dev->data->nb_rx_queues = 0;
864 for (i = 0; i < dev->data->nb_tx_queues; i++) {
865 void *txq = dev->data->tx_queues[i];
867 vmxnet3_dev_tx_queue_release(txq);
869 dev->data->nb_tx_queues = 0;
873 * Reset and stop device.
876 vmxnet3_dev_close(struct rte_eth_dev *dev)
878 PMD_INIT_FUNC_TRACE();
880 vmxnet3_dev_stop(dev);
881 vmxnet3_free_queues(dev);
885 vmxnet3_hw_tx_stats_get(struct vmxnet3_hw *hw, unsigned int q,
886 struct UPT1_TxStats *res)
888 #define VMXNET3_UPDATE_TX_STAT(h, i, f, r) \
889 ((r)->f = (h)->tqd_start[(i)].stats.f + \
890 (h)->saved_tx_stats[(i)].f)
892 VMXNET3_UPDATE_TX_STAT(hw, q, ucastPktsTxOK, res);
893 VMXNET3_UPDATE_TX_STAT(hw, q, mcastPktsTxOK, res);
894 VMXNET3_UPDATE_TX_STAT(hw, q, bcastPktsTxOK, res);
895 VMXNET3_UPDATE_TX_STAT(hw, q, ucastBytesTxOK, res);
896 VMXNET3_UPDATE_TX_STAT(hw, q, mcastBytesTxOK, res);
897 VMXNET3_UPDATE_TX_STAT(hw, q, bcastBytesTxOK, res);
898 VMXNET3_UPDATE_TX_STAT(hw, q, pktsTxError, res);
899 VMXNET3_UPDATE_TX_STAT(hw, q, pktsTxDiscard, res);
901 #undef VMXNET3_UPDATE_TX_STAT
905 vmxnet3_hw_rx_stats_get(struct vmxnet3_hw *hw, unsigned int q,
906 struct UPT1_RxStats *res)
908 #define VMXNET3_UPDATE_RX_STAT(h, i, f, r) \
909 ((r)->f = (h)->rqd_start[(i)].stats.f + \
910 (h)->saved_rx_stats[(i)].f)
912 VMXNET3_UPDATE_RX_STAT(hw, q, ucastPktsRxOK, res);
913 VMXNET3_UPDATE_RX_STAT(hw, q, mcastPktsRxOK, res);
914 VMXNET3_UPDATE_RX_STAT(hw, q, bcastPktsRxOK, res);
915 VMXNET3_UPDATE_RX_STAT(hw, q, ucastBytesRxOK, res);
916 VMXNET3_UPDATE_RX_STAT(hw, q, mcastBytesRxOK, res);
917 VMXNET3_UPDATE_RX_STAT(hw, q, bcastBytesRxOK, res);
918 VMXNET3_UPDATE_RX_STAT(hw, q, pktsRxError, res);
919 VMXNET3_UPDATE_RX_STAT(hw, q, pktsRxOutOfBuf, res);
921 #undef VMXNET3_UPDATE_RX_STAT
925 vmxnet3_tx_stats_get(struct vmxnet3_hw *hw, unsigned int q,
926 struct UPT1_TxStats *res)
928 vmxnet3_hw_tx_stats_get(hw, q, res);
930 #define VMXNET3_REDUCE_SNAPSHOT_TX_STAT(h, i, f, r) \
931 ((r)->f -= (h)->snapshot_tx_stats[(i)].f)
933 VMXNET3_REDUCE_SNAPSHOT_TX_STAT(hw, q, ucastPktsTxOK, res);
934 VMXNET3_REDUCE_SNAPSHOT_TX_STAT(hw, q, mcastPktsTxOK, res);
935 VMXNET3_REDUCE_SNAPSHOT_TX_STAT(hw, q, bcastPktsTxOK, res);
936 VMXNET3_REDUCE_SNAPSHOT_TX_STAT(hw, q, ucastBytesTxOK, res);
937 VMXNET3_REDUCE_SNAPSHOT_TX_STAT(hw, q, mcastBytesTxOK, res);
938 VMXNET3_REDUCE_SNAPSHOT_TX_STAT(hw, q, bcastBytesTxOK, res);
939 VMXNET3_REDUCE_SNAPSHOT_TX_STAT(hw, q, pktsTxError, res);
940 VMXNET3_REDUCE_SNAPSHOT_TX_STAT(hw, q, pktsTxDiscard, res);
942 #undef VMXNET3_REDUCE_SNAPSHOT_TX_STAT
946 vmxnet3_rx_stats_get(struct vmxnet3_hw *hw, unsigned int q,
947 struct UPT1_RxStats *res)
949 vmxnet3_hw_rx_stats_get(hw, q, res);
951 #define VMXNET3_REDUCE_SNAPSHOT_RX_STAT(h, i, f, r) \
952 ((r)->f -= (h)->snapshot_rx_stats[(i)].f)
954 VMXNET3_REDUCE_SNAPSHOT_RX_STAT(hw, q, ucastPktsRxOK, res);
955 VMXNET3_REDUCE_SNAPSHOT_RX_STAT(hw, q, mcastPktsRxOK, res);
956 VMXNET3_REDUCE_SNAPSHOT_RX_STAT(hw, q, bcastPktsRxOK, res);
957 VMXNET3_REDUCE_SNAPSHOT_RX_STAT(hw, q, ucastBytesRxOK, res);
958 VMXNET3_REDUCE_SNAPSHOT_RX_STAT(hw, q, mcastBytesRxOK, res);
959 VMXNET3_REDUCE_SNAPSHOT_RX_STAT(hw, q, bcastBytesRxOK, res);
960 VMXNET3_REDUCE_SNAPSHOT_RX_STAT(hw, q, pktsRxError, res);
961 VMXNET3_REDUCE_SNAPSHOT_RX_STAT(hw, q, pktsRxOutOfBuf, res);
963 #undef VMXNET3_REDUCE_SNAPSHOT_RX_STAT
967 vmxnet3_hw_stats_save(struct vmxnet3_hw *hw)
971 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, VMXNET3_CMD_GET_STATS);
973 RTE_BUILD_BUG_ON(RTE_ETHDEV_QUEUE_STAT_CNTRS < VMXNET3_MAX_TX_QUEUES);
975 for (i = 0; i < hw->num_tx_queues; i++)
976 vmxnet3_hw_tx_stats_get(hw, i, &hw->saved_tx_stats[i]);
977 for (i = 0; i < hw->num_rx_queues; i++)
978 vmxnet3_hw_rx_stats_get(hw, i, &hw->saved_rx_stats[i]);
982 vmxnet3_dev_xstats_get_names(struct rte_eth_dev *dev,
983 struct rte_eth_xstat_name *xstats_names,
986 unsigned int i, t, count = 0;
987 unsigned int nstats =
988 dev->data->nb_tx_queues * RTE_DIM(vmxnet3_txq_stat_strings) +
989 dev->data->nb_rx_queues * RTE_DIM(vmxnet3_rxq_stat_strings);
991 if (!xstats_names || n < nstats)
994 for (i = 0; i < dev->data->nb_rx_queues; i++) {
995 if (!dev->data->rx_queues[i])
998 for (t = 0; t < RTE_DIM(vmxnet3_rxq_stat_strings); t++) {
999 snprintf(xstats_names[count].name,
1000 sizeof(xstats_names[count].name),
1002 vmxnet3_rxq_stat_strings[t].name);
1007 for (i = 0; i < dev->data->nb_tx_queues; i++) {
1008 if (!dev->data->tx_queues[i])
1011 for (t = 0; t < RTE_DIM(vmxnet3_txq_stat_strings); t++) {
1012 snprintf(xstats_names[count].name,
1013 sizeof(xstats_names[count].name),
1015 vmxnet3_txq_stat_strings[t].name);
1024 vmxnet3_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
1027 unsigned int i, t, count = 0;
1028 unsigned int nstats =
1029 dev->data->nb_tx_queues * RTE_DIM(vmxnet3_txq_stat_strings) +
1030 dev->data->nb_rx_queues * RTE_DIM(vmxnet3_rxq_stat_strings);
1035 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1036 struct vmxnet3_rx_queue *rxq = dev->data->rx_queues[i];
1041 for (t = 0; t < RTE_DIM(vmxnet3_rxq_stat_strings); t++) {
1042 xstats[count].value = *(uint64_t *)(((char *)&rxq->stats) +
1043 vmxnet3_rxq_stat_strings[t].offset);
1044 xstats[count].id = count;
1049 for (i = 0; i < dev->data->nb_tx_queues; i++) {
1050 struct vmxnet3_tx_queue *txq = dev->data->tx_queues[i];
1055 for (t = 0; t < RTE_DIM(vmxnet3_txq_stat_strings); t++) {
1056 xstats[count].value = *(uint64_t *)(((char *)&txq->stats) +
1057 vmxnet3_txq_stat_strings[t].offset);
1058 xstats[count].id = count;
1067 vmxnet3_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
1070 struct vmxnet3_hw *hw = dev->data->dev_private;
1071 struct UPT1_TxStats txStats;
1072 struct UPT1_RxStats rxStats;
1074 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, VMXNET3_CMD_GET_STATS);
1076 RTE_BUILD_BUG_ON(RTE_ETHDEV_QUEUE_STAT_CNTRS < VMXNET3_MAX_TX_QUEUES);
1077 for (i = 0; i < hw->num_tx_queues; i++) {
1078 vmxnet3_tx_stats_get(hw, i, &txStats);
1080 stats->q_opackets[i] = txStats.ucastPktsTxOK +
1081 txStats.mcastPktsTxOK +
1082 txStats.bcastPktsTxOK;
1084 stats->q_obytes[i] = txStats.ucastBytesTxOK +
1085 txStats.mcastBytesTxOK +
1086 txStats.bcastBytesTxOK;
1088 stats->opackets += stats->q_opackets[i];
1089 stats->obytes += stats->q_obytes[i];
1090 stats->oerrors += txStats.pktsTxError + txStats.pktsTxDiscard;
1093 RTE_BUILD_BUG_ON(RTE_ETHDEV_QUEUE_STAT_CNTRS < VMXNET3_MAX_RX_QUEUES);
1094 for (i = 0; i < hw->num_rx_queues; i++) {
1095 vmxnet3_rx_stats_get(hw, i, &rxStats);
1097 stats->q_ipackets[i] = rxStats.ucastPktsRxOK +
1098 rxStats.mcastPktsRxOK +
1099 rxStats.bcastPktsRxOK;
1101 stats->q_ibytes[i] = rxStats.ucastBytesRxOK +
1102 rxStats.mcastBytesRxOK +
1103 rxStats.bcastBytesRxOK;
1105 stats->ipackets += stats->q_ipackets[i];
1106 stats->ibytes += stats->q_ibytes[i];
1108 stats->q_errors[i] = rxStats.pktsRxError;
1109 stats->ierrors += rxStats.pktsRxError;
1110 stats->imissed += rxStats.pktsRxOutOfBuf;
1117 vmxnet3_dev_stats_reset(struct rte_eth_dev *dev)
1120 struct vmxnet3_hw *hw = dev->data->dev_private;
1121 struct UPT1_TxStats txStats;
1122 struct UPT1_RxStats rxStats;
1124 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, VMXNET3_CMD_GET_STATS);
1126 RTE_BUILD_BUG_ON(RTE_ETHDEV_QUEUE_STAT_CNTRS < VMXNET3_MAX_TX_QUEUES);
1128 for (i = 0; i < hw->num_tx_queues; i++) {
1129 vmxnet3_hw_tx_stats_get(hw, i, &txStats);
1130 memcpy(&hw->snapshot_tx_stats[i], &txStats,
1131 sizeof(hw->snapshot_tx_stats[0]));
1133 for (i = 0; i < hw->num_rx_queues; i++) {
1134 vmxnet3_hw_rx_stats_get(hw, i, &rxStats);
1135 memcpy(&hw->snapshot_rx_stats[i], &rxStats,
1136 sizeof(hw->snapshot_rx_stats[0]));
1141 vmxnet3_dev_info_get(struct rte_eth_dev *dev __rte_unused,
1142 struct rte_eth_dev_info *dev_info)
1144 dev_info->max_rx_queues = VMXNET3_MAX_RX_QUEUES;
1145 dev_info->max_tx_queues = VMXNET3_MAX_TX_QUEUES;
1146 dev_info->min_rx_bufsize = 1518 + RTE_PKTMBUF_HEADROOM;
1147 dev_info->max_rx_pktlen = 16384; /* includes CRC, cf MAXFRS register */
1148 dev_info->speed_capa = ETH_LINK_SPEED_10G;
1149 dev_info->max_mac_addrs = VMXNET3_MAX_MAC_ADDRS;
1151 dev_info->flow_type_rss_offloads = VMXNET3_RSS_OFFLOAD_ALL;
1153 dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
1154 .nb_max = VMXNET3_RX_RING_MAX_SIZE,
1155 .nb_min = VMXNET3_DEF_RX_RING_SIZE,
1159 dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
1160 .nb_max = VMXNET3_TX_RING_MAX_SIZE,
1161 .nb_min = VMXNET3_DEF_TX_RING_SIZE,
1163 .nb_seg_max = VMXNET3_TX_MAX_SEG,
1164 .nb_mtu_seg_max = VMXNET3_MAX_TXD_PER_PKT,
1167 dev_info->rx_offload_capa = VMXNET3_RX_OFFLOAD_CAP;
1168 dev_info->rx_queue_offload_capa = 0;
1169 dev_info->tx_offload_capa = VMXNET3_TX_OFFLOAD_CAP;
1170 dev_info->tx_queue_offload_capa = 0;
1173 static const uint32_t *
1174 vmxnet3_dev_supported_ptypes_get(struct rte_eth_dev *dev)
1176 static const uint32_t ptypes[] = {
1177 RTE_PTYPE_L3_IPV4_EXT,
1182 if (dev->rx_pkt_burst == vmxnet3_recv_pkts)
1188 vmxnet3_mac_addr_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr)
1190 struct vmxnet3_hw *hw = dev->data->dev_private;
1192 ether_addr_copy(mac_addr, (struct ether_addr *)(hw->perm_addr));
1193 vmxnet3_write_mac(hw, mac_addr->addr_bytes);
1197 /* return 0 means link status changed, -1 means not changed */
1199 __vmxnet3_dev_link_update(struct rte_eth_dev *dev,
1200 __rte_unused int wait_to_complete)
1202 struct vmxnet3_hw *hw = dev->data->dev_private;
1203 struct rte_eth_link link;
1206 memset(&link, 0, sizeof(link));
1208 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, VMXNET3_CMD_GET_LINK);
1209 ret = VMXNET3_READ_BAR1_REG(hw, VMXNET3_REG_CMD);
1212 link.link_status = ETH_LINK_UP;
1213 link.link_duplex = ETH_LINK_FULL_DUPLEX;
1214 link.link_speed = ETH_SPEED_NUM_10G;
1215 link.link_autoneg = ETH_LINK_FIXED;
1217 return rte_eth_linkstatus_set(dev, &link);
1221 vmxnet3_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
1223 /* Link status doesn't change for stopped dev */
1224 if (dev->data->dev_started == 0)
1227 return __vmxnet3_dev_link_update(dev, wait_to_complete);
1230 /* Updating rxmode through Vmxnet3_DriverShared structure in adapter */
1232 vmxnet3_dev_set_rxmode(struct vmxnet3_hw *hw, uint32_t feature, int set)
1234 struct Vmxnet3_RxFilterConf *rxConf = &hw->shared->devRead.rxFilterConf;
1237 rxConf->rxMode = rxConf->rxMode | feature;
1239 rxConf->rxMode = rxConf->rxMode & (~feature);
1241 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, VMXNET3_CMD_UPDATE_RX_MODE);
1244 /* Promiscuous supported only if Vmxnet3_DriverShared is initialized in adapter */
1246 vmxnet3_dev_promiscuous_enable(struct rte_eth_dev *dev)
1248 struct vmxnet3_hw *hw = dev->data->dev_private;
1249 uint32_t *vf_table = hw->shared->devRead.rxFilterConf.vfTable;
1251 memset(vf_table, 0, VMXNET3_VFT_TABLE_SIZE);
1252 vmxnet3_dev_set_rxmode(hw, VMXNET3_RXM_PROMISC, 1);
1254 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD,
1255 VMXNET3_CMD_UPDATE_VLAN_FILTERS);
1258 /* Promiscuous supported only if Vmxnet3_DriverShared is initialized in adapter */
1260 vmxnet3_dev_promiscuous_disable(struct rte_eth_dev *dev)
1262 struct vmxnet3_hw *hw = dev->data->dev_private;
1263 uint32_t *vf_table = hw->shared->devRead.rxFilterConf.vfTable;
1264 uint64_t rx_offloads = dev->data->dev_conf.rxmode.offloads;
1266 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
1267 memcpy(vf_table, hw->shadow_vfta, VMXNET3_VFT_TABLE_SIZE);
1269 memset(vf_table, 0xff, VMXNET3_VFT_TABLE_SIZE);
1270 vmxnet3_dev_set_rxmode(hw, VMXNET3_RXM_PROMISC, 0);
1271 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD,
1272 VMXNET3_CMD_UPDATE_VLAN_FILTERS);
1275 /* Allmulticast supported only if Vmxnet3_DriverShared is initialized in adapter */
1277 vmxnet3_dev_allmulticast_enable(struct rte_eth_dev *dev)
1279 struct vmxnet3_hw *hw = dev->data->dev_private;
1281 vmxnet3_dev_set_rxmode(hw, VMXNET3_RXM_ALL_MULTI, 1);
1284 /* Allmulticast supported only if Vmxnet3_DriverShared is initialized in adapter */
1286 vmxnet3_dev_allmulticast_disable(struct rte_eth_dev *dev)
1288 struct vmxnet3_hw *hw = dev->data->dev_private;
1290 vmxnet3_dev_set_rxmode(hw, VMXNET3_RXM_ALL_MULTI, 0);
1293 /* Enable/disable filter on vlan */
1295 vmxnet3_dev_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vid, int on)
1297 struct vmxnet3_hw *hw = dev->data->dev_private;
1298 struct Vmxnet3_RxFilterConf *rxConf = &hw->shared->devRead.rxFilterConf;
1299 uint32_t *vf_table = rxConf->vfTable;
1301 /* save state for restore */
1303 VMXNET3_SET_VFTABLE_ENTRY(hw->shadow_vfta, vid);
1305 VMXNET3_CLEAR_VFTABLE_ENTRY(hw->shadow_vfta, vid);
1307 /* don't change active filter if in promiscuous mode */
1308 if (rxConf->rxMode & VMXNET3_RXM_PROMISC)
1311 /* set in hardware */
1313 VMXNET3_SET_VFTABLE_ENTRY(vf_table, vid);
1315 VMXNET3_CLEAR_VFTABLE_ENTRY(vf_table, vid);
1317 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD,
1318 VMXNET3_CMD_UPDATE_VLAN_FILTERS);
1323 vmxnet3_dev_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1325 struct vmxnet3_hw *hw = dev->data->dev_private;
1326 Vmxnet3_DSDevRead *devRead = &hw->shared->devRead;
1327 uint32_t *vf_table = devRead->rxFilterConf.vfTable;
1328 uint64_t rx_offloads = dev->data->dev_conf.rxmode.offloads;
1330 if (mask & ETH_VLAN_STRIP_MASK) {
1331 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
1332 devRead->misc.uptFeatures |= UPT1_F_RXVLAN;
1334 devRead->misc.uptFeatures &= ~UPT1_F_RXVLAN;
1336 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD,
1337 VMXNET3_CMD_UPDATE_FEATURE);
1340 if (mask & ETH_VLAN_FILTER_MASK) {
1341 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
1342 memcpy(vf_table, hw->shadow_vfta, VMXNET3_VFT_TABLE_SIZE);
1344 memset(vf_table, 0xff, VMXNET3_VFT_TABLE_SIZE);
1346 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD,
1347 VMXNET3_CMD_UPDATE_VLAN_FILTERS);
1354 vmxnet3_process_events(struct rte_eth_dev *dev)
1356 struct vmxnet3_hw *hw = dev->data->dev_private;
1357 uint32_t events = hw->shared->ecr;
1363 * ECR bits when written with 1b are cleared. Hence write
1364 * events back to ECR so that the bits which were set will be reset.
1366 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_ECR, events);
1368 /* Check if link state has changed */
1369 if (events & VMXNET3_ECR_LINK) {
1370 PMD_DRV_LOG(DEBUG, "Process events: VMXNET3_ECR_LINK event");
1371 if (vmxnet3_dev_link_update(dev, 0) == 0)
1372 _rte_eth_dev_callback_process(dev,
1373 RTE_ETH_EVENT_INTR_LSC,
1377 /* Check if there is an error on xmit/recv queues */
1378 if (events & (VMXNET3_ECR_TQERR | VMXNET3_ECR_RQERR)) {
1379 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD,
1380 VMXNET3_CMD_GET_QUEUE_STATUS);
1382 if (hw->tqd_start->status.stopped)
1383 PMD_DRV_LOG(ERR, "tq error 0x%x",
1384 hw->tqd_start->status.error);
1386 if (hw->rqd_start->status.stopped)
1387 PMD_DRV_LOG(ERR, "rq error 0x%x",
1388 hw->rqd_start->status.error);
1390 /* Reset the device */
1391 /* Have to reset the device */
1394 if (events & VMXNET3_ECR_DIC)
1395 PMD_DRV_LOG(DEBUG, "Device implementation change event.");
1397 if (events & VMXNET3_ECR_DEBUG)
1398 PMD_DRV_LOG(DEBUG, "Debug event generated by device.");
1402 vmxnet3_interrupt_handler(void *param)
1404 struct rte_eth_dev *dev = param;
1405 struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev->device);
1407 vmxnet3_process_events(dev);
1409 if (rte_intr_enable(&pci_dev->intr_handle) < 0)
1410 PMD_DRV_LOG(ERR, "interrupt enable failed");
1413 RTE_PMD_REGISTER_PCI(net_vmxnet3, rte_vmxnet3_pmd);
1414 RTE_PMD_REGISTER_PCI_TABLE(net_vmxnet3, pci_id_vmxnet3_map);
1415 RTE_PMD_REGISTER_KMOD_DEP(net_vmxnet3, "* igb_uio | uio_pci_generic | vfio-pci");
1417 RTE_INIT(vmxnet3_init_log)
1419 vmxnet3_logtype_init = rte_log_register("pmd.net.vmxnet3.init");
1420 if (vmxnet3_logtype_init >= 0)
1421 rte_log_set_level(vmxnet3_logtype_init, RTE_LOG_NOTICE);
1422 vmxnet3_logtype_driver = rte_log_register("pmd.net.vmxnet3.driver");
1423 if (vmxnet3_logtype_driver >= 0)
1424 rte_log_set_level(vmxnet3_logtype_driver, RTE_LOG_NOTICE);