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34 #include <sys/queue.h>
43 #include <rte_byteorder.h>
44 #include <rte_common.h>
45 #include <rte_cycles.h>
47 #include <rte_interrupts.h>
49 #include <rte_debug.h>
51 #include <rte_atomic.h>
52 #include <rte_branch_prediction.h>
53 #include <rte_memory.h>
54 #include <rte_memzone.h>
56 #include <rte_alarm.h>
57 #include <rte_ether.h>
58 #include <rte_ethdev.h>
59 #include <rte_atomic.h>
60 #include <rte_string_fns.h>
61 #include <rte_malloc.h>
64 #include "base/vmxnet3_defs.h"
66 #include "vmxnet3_ring.h"
67 #include "vmxnet3_logs.h"
68 #include "vmxnet3_ethdev.h"
70 #define PROCESS_SYS_EVENTS 0
72 #define VMXNET3_TX_MAX_SEG UINT8_MAX
74 static int eth_vmxnet3_dev_init(struct rte_eth_dev *eth_dev);
75 static int eth_vmxnet3_dev_uninit(struct rte_eth_dev *eth_dev);
76 static int vmxnet3_dev_configure(struct rte_eth_dev *dev);
77 static int vmxnet3_dev_start(struct rte_eth_dev *dev);
78 static void vmxnet3_dev_stop(struct rte_eth_dev *dev);
79 static void vmxnet3_dev_close(struct rte_eth_dev *dev);
80 static void vmxnet3_dev_set_rxmode(struct vmxnet3_hw *hw, uint32_t feature, int set);
81 static void vmxnet3_dev_promiscuous_enable(struct rte_eth_dev *dev);
82 static void vmxnet3_dev_promiscuous_disable(struct rte_eth_dev *dev);
83 static void vmxnet3_dev_allmulticast_enable(struct rte_eth_dev *dev);
84 static void vmxnet3_dev_allmulticast_disable(struct rte_eth_dev *dev);
85 static int vmxnet3_dev_link_update(struct rte_eth_dev *dev,
86 int wait_to_complete);
87 static void vmxnet3_dev_stats_get(struct rte_eth_dev *dev,
88 struct rte_eth_stats *stats);
89 static void vmxnet3_dev_info_get(struct rte_eth_dev *dev,
90 struct rte_eth_dev_info *dev_info);
91 static const uint32_t *
92 vmxnet3_dev_supported_ptypes_get(struct rte_eth_dev *dev);
93 static int vmxnet3_dev_vlan_filter_set(struct rte_eth_dev *dev,
94 uint16_t vid, int on);
95 static void vmxnet3_dev_vlan_offload_set(struct rte_eth_dev *dev, int mask);
96 static void vmxnet3_mac_addr_set(struct rte_eth_dev *dev,
97 struct ether_addr *mac_addr);
99 #if PROCESS_SYS_EVENTS == 1
100 static void vmxnet3_process_events(struct vmxnet3_hw *);
103 * The set of PCI devices this driver supports
105 #define VMWARE_PCI_VENDOR_ID 0x15AD
106 #define VMWARE_DEV_ID_VMXNET3 0x07B0
107 static const struct rte_pci_id pci_id_vmxnet3_map[] = {
108 { RTE_PCI_DEVICE(VMWARE_PCI_VENDOR_ID, VMWARE_DEV_ID_VMXNET3) },
109 { .vendor_id = 0, /* sentinel */ },
112 static const struct eth_dev_ops vmxnet3_eth_dev_ops = {
113 .dev_configure = vmxnet3_dev_configure,
114 .dev_start = vmxnet3_dev_start,
115 .dev_stop = vmxnet3_dev_stop,
116 .dev_close = vmxnet3_dev_close,
117 .promiscuous_enable = vmxnet3_dev_promiscuous_enable,
118 .promiscuous_disable = vmxnet3_dev_promiscuous_disable,
119 .allmulticast_enable = vmxnet3_dev_allmulticast_enable,
120 .allmulticast_disable = vmxnet3_dev_allmulticast_disable,
121 .link_update = vmxnet3_dev_link_update,
122 .stats_get = vmxnet3_dev_stats_get,
123 .mac_addr_set = vmxnet3_mac_addr_set,
124 .dev_infos_get = vmxnet3_dev_info_get,
125 .dev_supported_ptypes_get = vmxnet3_dev_supported_ptypes_get,
126 .vlan_filter_set = vmxnet3_dev_vlan_filter_set,
127 .vlan_offload_set = vmxnet3_dev_vlan_offload_set,
128 .rx_queue_setup = vmxnet3_dev_rx_queue_setup,
129 .rx_queue_release = vmxnet3_dev_rx_queue_release,
130 .tx_queue_setup = vmxnet3_dev_tx_queue_setup,
131 .tx_queue_release = vmxnet3_dev_tx_queue_release,
134 static const struct rte_memzone *
135 gpa_zone_reserve(struct rte_eth_dev *dev, uint32_t size,
136 const char *post_string, int socket_id,
137 uint16_t align, bool reuse)
139 char z_name[RTE_MEMZONE_NAMESIZE];
140 const struct rte_memzone *mz;
142 snprintf(z_name, sizeof(z_name), "%s_%d_%s",
143 dev->data->drv_name, dev->data->port_id, post_string);
145 mz = rte_memzone_lookup(z_name);
148 rte_memzone_free(mz);
149 return rte_memzone_reserve_aligned(z_name, size, socket_id,
156 return rte_memzone_reserve_aligned(z_name, size, socket_id, 0, align);
160 * Atomically reads the link status information from global
161 * structure rte_eth_dev.
164 * - Pointer to the structure rte_eth_dev to read from.
165 * - Pointer to the buffer to be saved with the link status.
168 * - On success, zero.
169 * - On failure, negative value.
173 vmxnet3_dev_atomic_read_link_status(struct rte_eth_dev *dev,
174 struct rte_eth_link *link)
176 struct rte_eth_link *dst = link;
177 struct rte_eth_link *src = &(dev->data->dev_link);
179 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
180 *(uint64_t *)src) == 0)
187 * Atomically writes the link status information into global
188 * structure rte_eth_dev.
191 * - Pointer to the structure rte_eth_dev to write to.
192 * - Pointer to the buffer to be saved with the link status.
195 * - On success, zero.
196 * - On failure, negative value.
199 vmxnet3_dev_atomic_write_link_status(struct rte_eth_dev *dev,
200 struct rte_eth_link *link)
202 struct rte_eth_link *dst = &(dev->data->dev_link);
203 struct rte_eth_link *src = link;
205 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
206 *(uint64_t *)src) == 0)
213 * This function is based on vmxnet3_disable_intr()
216 vmxnet3_disable_intr(struct vmxnet3_hw *hw)
220 PMD_INIT_FUNC_TRACE();
222 hw->shared->devRead.intrConf.intrCtrl |= VMXNET3_IC_DISABLE_ALL;
223 for (i = 0; i < VMXNET3_MAX_INTRS; i++)
224 VMXNET3_WRITE_BAR0_REG(hw, VMXNET3_REG_IMR + i * 8, 1);
228 * It returns 0 on success.
231 eth_vmxnet3_dev_init(struct rte_eth_dev *eth_dev)
233 struct rte_pci_device *pci_dev;
234 struct vmxnet3_hw *hw = eth_dev->data->dev_private;
235 uint32_t mac_hi, mac_lo, ver;
237 PMD_INIT_FUNC_TRACE();
239 eth_dev->dev_ops = &vmxnet3_eth_dev_ops;
240 eth_dev->rx_pkt_burst = &vmxnet3_recv_pkts;
241 eth_dev->tx_pkt_burst = &vmxnet3_xmit_pkts;
242 eth_dev->tx_pkt_prepare = vmxnet3_prep_pkts;
243 pci_dev = RTE_DEV_TO_PCI(eth_dev->device);
246 * for secondary processes, we don't initialize any further as primary
247 * has already done this work.
249 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
252 rte_eth_copy_pci_info(eth_dev, pci_dev);
253 eth_dev->data->dev_flags |= RTE_ETH_DEV_DETACHABLE;
255 /* Vendor and Device ID need to be set before init of shared code */
256 hw->device_id = pci_dev->id.device_id;
257 hw->vendor_id = pci_dev->id.vendor_id;
258 hw->hw_addr0 = (void *)pci_dev->mem_resource[0].addr;
259 hw->hw_addr1 = (void *)pci_dev->mem_resource[1].addr;
261 hw->num_rx_queues = 1;
262 hw->num_tx_queues = 1;
263 hw->bufs_per_pkt = 1;
265 /* Check h/w version compatibility with driver. */
266 ver = VMXNET3_READ_BAR1_REG(hw, VMXNET3_REG_VRRS);
267 PMD_INIT_LOG(DEBUG, "Hardware version : %d", ver);
269 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_VRRS, 1);
271 PMD_INIT_LOG(ERR, "Incompatible h/w version, should be 0x1");
275 /* Check UPT version compatibility with driver. */
276 ver = VMXNET3_READ_BAR1_REG(hw, VMXNET3_REG_UVRS);
277 PMD_INIT_LOG(DEBUG, "UPT hardware version : %d", ver);
279 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_UVRS, 1);
281 PMD_INIT_LOG(ERR, "Incompatible UPT version.");
285 /* Getting MAC Address */
286 mac_lo = VMXNET3_READ_BAR1_REG(hw, VMXNET3_REG_MACL);
287 mac_hi = VMXNET3_READ_BAR1_REG(hw, VMXNET3_REG_MACH);
288 memcpy(hw->perm_addr, &mac_lo, 4);
289 memcpy(hw->perm_addr + 4, &mac_hi, 2);
291 /* Allocate memory for storing MAC addresses */
292 eth_dev->data->mac_addrs = rte_zmalloc("vmxnet3", ETHER_ADDR_LEN *
293 VMXNET3_MAX_MAC_ADDRS, 0);
294 if (eth_dev->data->mac_addrs == NULL) {
296 "Failed to allocate %d bytes needed to store MAC addresses",
297 ETHER_ADDR_LEN * VMXNET3_MAX_MAC_ADDRS);
300 /* Copy the permanent MAC address */
301 ether_addr_copy((struct ether_addr *) hw->perm_addr,
302 ð_dev->data->mac_addrs[0]);
304 PMD_INIT_LOG(DEBUG, "MAC Address : %02x:%02x:%02x:%02x:%02x:%02x",
305 hw->perm_addr[0], hw->perm_addr[1], hw->perm_addr[2],
306 hw->perm_addr[3], hw->perm_addr[4], hw->perm_addr[5]);
308 /* Put device in Quiesce Mode */
309 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, VMXNET3_CMD_QUIESCE_DEV);
311 /* allow untagged pkts */
312 VMXNET3_SET_VFTABLE_ENTRY(hw->shadow_vfta, 0);
318 eth_vmxnet3_dev_uninit(struct rte_eth_dev *eth_dev)
320 struct vmxnet3_hw *hw = eth_dev->data->dev_private;
322 PMD_INIT_FUNC_TRACE();
324 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
327 if (hw->adapter_stopped == 0)
328 vmxnet3_dev_close(eth_dev);
330 eth_dev->dev_ops = NULL;
331 eth_dev->rx_pkt_burst = NULL;
332 eth_dev->tx_pkt_burst = NULL;
333 eth_dev->tx_pkt_prepare = NULL;
335 rte_free(eth_dev->data->mac_addrs);
336 eth_dev->data->mac_addrs = NULL;
341 static struct eth_driver rte_vmxnet3_pmd = {
343 .id_table = pci_id_vmxnet3_map,
344 .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
345 .probe = rte_eth_dev_pci_probe,
346 .remove = rte_eth_dev_pci_remove,
348 .eth_dev_init = eth_vmxnet3_dev_init,
349 .eth_dev_uninit = eth_vmxnet3_dev_uninit,
350 .dev_private_size = sizeof(struct vmxnet3_hw),
354 vmxnet3_dev_configure(struct rte_eth_dev *dev)
356 const struct rte_memzone *mz;
357 struct vmxnet3_hw *hw = dev->data->dev_private;
360 PMD_INIT_FUNC_TRACE();
362 if (dev->data->nb_tx_queues > VMXNET3_MAX_TX_QUEUES ||
363 dev->data->nb_rx_queues > VMXNET3_MAX_RX_QUEUES) {
364 PMD_INIT_LOG(ERR, "ERROR: Number of queues not supported");
368 if (!rte_is_power_of_2(dev->data->nb_rx_queues)) {
369 PMD_INIT_LOG(ERR, "ERROR: Number of rx queues not power of 2");
373 size = dev->data->nb_rx_queues * sizeof(struct Vmxnet3_TxQueueDesc) +
374 dev->data->nb_tx_queues * sizeof(struct Vmxnet3_RxQueueDesc);
376 if (size > UINT16_MAX)
379 hw->num_rx_queues = (uint8_t)dev->data->nb_rx_queues;
380 hw->num_tx_queues = (uint8_t)dev->data->nb_tx_queues;
383 * Allocate a memzone for Vmxnet3_DriverShared - Vmxnet3_DSDevRead
386 mz = gpa_zone_reserve(dev, sizeof(struct Vmxnet3_DriverShared),
387 "shared", rte_socket_id(), 8, 1);
390 PMD_INIT_LOG(ERR, "ERROR: Creating shared zone");
393 memset(mz->addr, 0, mz->len);
395 hw->shared = mz->addr;
396 hw->sharedPA = mz->phys_addr;
399 * Allocate a memzone for Vmxnet3_RxQueueDesc - Vmxnet3_TxQueueDesc
402 * We cannot reuse this memzone from previous allocation as its size
403 * depends on the number of tx and rx queues, which could be different
404 * from one config to another.
406 mz = gpa_zone_reserve(dev, size, "queuedesc", rte_socket_id(),
407 VMXNET3_QUEUE_DESC_ALIGN, 0);
409 PMD_INIT_LOG(ERR, "ERROR: Creating queue descriptors zone");
412 memset(mz->addr, 0, mz->len);
414 hw->tqd_start = (Vmxnet3_TxQueueDesc *)mz->addr;
415 hw->rqd_start = (Vmxnet3_RxQueueDesc *)(hw->tqd_start + hw->num_tx_queues);
417 hw->queueDescPA = mz->phys_addr;
418 hw->queue_desc_len = (uint16_t)size;
420 if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_RSS) {
421 /* Allocate memory structure for UPT1_RSSConf and configure */
422 mz = gpa_zone_reserve(dev, sizeof(struct VMXNET3_RSSConf),
423 "rss_conf", rte_socket_id(),
424 RTE_CACHE_LINE_SIZE, 1);
427 "ERROR: Creating rss_conf structure zone");
430 memset(mz->addr, 0, mz->len);
432 hw->rss_conf = mz->addr;
433 hw->rss_confPA = mz->phys_addr;
440 vmxnet3_write_mac(struct vmxnet3_hw *hw, const uint8_t *addr)
445 "Writing MAC Address : %02x:%02x:%02x:%02x:%02x:%02x",
446 addr[0], addr[1], addr[2],
447 addr[3], addr[4], addr[5]);
449 val = *(const uint32_t *)addr;
450 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_MACL, val);
452 val = (addr[5] << 8) | addr[4];
453 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_MACH, val);
457 vmxnet3_setup_driver_shared(struct rte_eth_dev *dev)
459 struct rte_eth_conf port_conf = dev->data->dev_conf;
460 struct vmxnet3_hw *hw = dev->data->dev_private;
461 uint32_t mtu = dev->data->mtu;
462 Vmxnet3_DriverShared *shared = hw->shared;
463 Vmxnet3_DSDevRead *devRead = &shared->devRead;
467 shared->magic = VMXNET3_REV1_MAGIC;
468 devRead->misc.driverInfo.version = VMXNET3_DRIVER_VERSION_NUM;
470 /* Setting up Guest OS information */
471 devRead->misc.driverInfo.gos.gosBits = sizeof(void *) == 4 ?
472 VMXNET3_GOS_BITS_32 : VMXNET3_GOS_BITS_64;
473 devRead->misc.driverInfo.gos.gosType = VMXNET3_GOS_TYPE_LINUX;
474 devRead->misc.driverInfo.vmxnet3RevSpt = 1;
475 devRead->misc.driverInfo.uptVerSpt = 1;
477 devRead->misc.mtu = rte_le_to_cpu_32(mtu);
478 devRead->misc.queueDescPA = hw->queueDescPA;
479 devRead->misc.queueDescLen = hw->queue_desc_len;
480 devRead->misc.numTxQueues = hw->num_tx_queues;
481 devRead->misc.numRxQueues = hw->num_rx_queues;
484 * Set number of interrupts to 1
485 * PMD disables all the interrupts but this is MUST to activate device
486 * It needs at least one interrupt for link events to handle
487 * So we'll disable it later after device activation if needed
489 devRead->intrConf.numIntrs = 1;
490 devRead->intrConf.intrCtrl |= VMXNET3_IC_DISABLE_ALL;
492 for (i = 0; i < hw->num_tx_queues; i++) {
493 Vmxnet3_TxQueueDesc *tqd = &hw->tqd_start[i];
494 vmxnet3_tx_queue_t *txq = dev->data->tx_queues[i];
496 tqd->ctrl.txNumDeferred = 0;
497 tqd->ctrl.txThreshold = 1;
498 tqd->conf.txRingBasePA = txq->cmd_ring.basePA;
499 tqd->conf.compRingBasePA = txq->comp_ring.basePA;
500 tqd->conf.dataRingBasePA = txq->data_ring.basePA;
502 tqd->conf.txRingSize = txq->cmd_ring.size;
503 tqd->conf.compRingSize = txq->comp_ring.size;
504 tqd->conf.dataRingSize = txq->data_ring.size;
505 tqd->conf.intrIdx = txq->comp_ring.intr_idx;
506 tqd->status.stopped = TRUE;
507 tqd->status.error = 0;
508 memset(&tqd->stats, 0, sizeof(tqd->stats));
511 for (i = 0; i < hw->num_rx_queues; i++) {
512 Vmxnet3_RxQueueDesc *rqd = &hw->rqd_start[i];
513 vmxnet3_rx_queue_t *rxq = dev->data->rx_queues[i];
515 rqd->conf.rxRingBasePA[0] = rxq->cmd_ring[0].basePA;
516 rqd->conf.rxRingBasePA[1] = rxq->cmd_ring[1].basePA;
517 rqd->conf.compRingBasePA = rxq->comp_ring.basePA;
519 rqd->conf.rxRingSize[0] = rxq->cmd_ring[0].size;
520 rqd->conf.rxRingSize[1] = rxq->cmd_ring[1].size;
521 rqd->conf.compRingSize = rxq->comp_ring.size;
522 rqd->conf.intrIdx = rxq->comp_ring.intr_idx;
523 rqd->status.stopped = TRUE;
524 rqd->status.error = 0;
525 memset(&rqd->stats, 0, sizeof(rqd->stats));
528 /* RxMode set to 0 of VMXNET3_RXM_xxx */
529 devRead->rxFilterConf.rxMode = 0;
531 /* Setting up feature flags */
532 if (dev->data->dev_conf.rxmode.hw_ip_checksum)
533 devRead->misc.uptFeatures |= VMXNET3_F_RXCSUM;
535 if (dev->data->dev_conf.rxmode.enable_lro) {
536 devRead->misc.uptFeatures |= VMXNET3_F_LRO;
537 devRead->misc.maxNumRxSG = 0;
540 if (port_conf.rxmode.mq_mode == ETH_MQ_RX_RSS) {
541 ret = vmxnet3_rss_configure(dev);
542 if (ret != VMXNET3_SUCCESS)
545 devRead->misc.uptFeatures |= VMXNET3_F_RSS;
546 devRead->rssConfDesc.confVer = 1;
547 devRead->rssConfDesc.confLen = sizeof(struct VMXNET3_RSSConf);
548 devRead->rssConfDesc.confPA = hw->rss_confPA;
551 vmxnet3_dev_vlan_offload_set(dev,
552 ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK);
554 vmxnet3_write_mac(hw, hw->perm_addr);
556 return VMXNET3_SUCCESS;
560 * Configure device link speed and setup link.
561 * Must be called after eth_vmxnet3_dev_init. Other wise it might fail
562 * It returns 0 on success.
565 vmxnet3_dev_start(struct rte_eth_dev *dev)
568 struct vmxnet3_hw *hw = dev->data->dev_private;
570 PMD_INIT_FUNC_TRACE();
572 ret = vmxnet3_setup_driver_shared(dev);
573 if (ret != VMXNET3_SUCCESS)
576 /* Exchange shared data with device */
577 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_DSAL,
578 VMXNET3_GET_ADDR_LO(hw->sharedPA));
579 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_DSAH,
580 VMXNET3_GET_ADDR_HI(hw->sharedPA));
582 /* Activate device by register write */
583 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, VMXNET3_CMD_ACTIVATE_DEV);
584 ret = VMXNET3_READ_BAR1_REG(hw, VMXNET3_REG_CMD);
587 PMD_INIT_LOG(ERR, "Device activation: UNSUCCESSFUL");
591 /* Disable interrupts */
592 vmxnet3_disable_intr(hw);
595 * Load RX queues with blank mbufs and update next2fill index for device
596 * Update RxMode of the device
598 ret = vmxnet3_dev_rxtx_init(dev);
599 if (ret != VMXNET3_SUCCESS) {
600 PMD_INIT_LOG(ERR, "Device queue init: UNSUCCESSFUL");
604 /* Setting proper Rx Mode and issue Rx Mode Update command */
605 vmxnet3_dev_set_rxmode(hw, VMXNET3_RXM_UCAST | VMXNET3_RXM_BCAST, 1);
608 * Don't need to handle events for now
610 #if PROCESS_SYS_EVENTS == 1
611 events = VMXNET3_READ_BAR1_REG(hw, VMXNET3_REG_ECR);
612 PMD_INIT_LOG(DEBUG, "Reading events: 0x%X", events);
613 vmxnet3_process_events(hw);
615 return VMXNET3_SUCCESS;
619 * Stop device: disable rx and tx functions to allow for reconfiguring.
622 vmxnet3_dev_stop(struct rte_eth_dev *dev)
624 struct rte_eth_link link;
625 struct vmxnet3_hw *hw = dev->data->dev_private;
627 PMD_INIT_FUNC_TRACE();
629 if (hw->adapter_stopped == 1) {
630 PMD_INIT_LOG(DEBUG, "Device already closed.");
634 /* disable interrupts */
635 vmxnet3_disable_intr(hw);
637 /* quiesce the device first */
638 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, VMXNET3_CMD_QUIESCE_DEV);
639 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_DSAL, 0);
640 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_DSAH, 0);
642 /* reset the device */
643 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, VMXNET3_CMD_RESET_DEV);
644 PMD_INIT_LOG(DEBUG, "Device reset.");
645 hw->adapter_stopped = 0;
647 vmxnet3_dev_clear_queues(dev);
649 /* Clear recorded link status */
650 memset(&link, 0, sizeof(link));
651 vmxnet3_dev_atomic_write_link_status(dev, &link);
655 * Reset and stop device.
658 vmxnet3_dev_close(struct rte_eth_dev *dev)
660 struct vmxnet3_hw *hw = dev->data->dev_private;
662 PMD_INIT_FUNC_TRACE();
664 vmxnet3_dev_stop(dev);
665 hw->adapter_stopped = 1;
669 vmxnet3_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
672 struct vmxnet3_hw *hw = dev->data->dev_private;
674 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, VMXNET3_CMD_GET_STATS);
676 RTE_BUILD_BUG_ON(RTE_ETHDEV_QUEUE_STAT_CNTRS < VMXNET3_MAX_TX_QUEUES);
677 for (i = 0; i < hw->num_tx_queues; i++) {
678 struct UPT1_TxStats *txStats = &hw->tqd_start[i].stats;
680 stats->q_opackets[i] = txStats->ucastPktsTxOK +
681 txStats->mcastPktsTxOK +
682 txStats->bcastPktsTxOK;
683 stats->q_obytes[i] = txStats->ucastBytesTxOK +
684 txStats->mcastBytesTxOK +
685 txStats->bcastBytesTxOK;
687 stats->opackets += stats->q_opackets[i];
688 stats->obytes += stats->q_obytes[i];
689 stats->oerrors += txStats->pktsTxError + txStats->pktsTxDiscard;
692 RTE_BUILD_BUG_ON(RTE_ETHDEV_QUEUE_STAT_CNTRS < VMXNET3_MAX_RX_QUEUES);
693 for (i = 0; i < hw->num_rx_queues; i++) {
694 struct UPT1_RxStats *rxStats = &hw->rqd_start[i].stats;
696 stats->q_ipackets[i] = rxStats->ucastPktsRxOK +
697 rxStats->mcastPktsRxOK +
698 rxStats->bcastPktsRxOK;
700 stats->q_ibytes[i] = rxStats->ucastBytesRxOK +
701 rxStats->mcastBytesRxOK +
702 rxStats->bcastBytesRxOK;
704 stats->ipackets += stats->q_ipackets[i];
705 stats->ibytes += stats->q_ibytes[i];
707 stats->q_errors[i] = rxStats->pktsRxError;
708 stats->ierrors += rxStats->pktsRxError;
709 stats->rx_nombuf += rxStats->pktsRxOutOfBuf;
714 vmxnet3_dev_info_get(struct rte_eth_dev *dev,
715 struct rte_eth_dev_info *dev_info)
717 dev_info->pci_dev = RTE_DEV_TO_PCI(dev->device);
719 dev_info->max_rx_queues = VMXNET3_MAX_RX_QUEUES;
720 dev_info->max_tx_queues = VMXNET3_MAX_TX_QUEUES;
721 dev_info->min_rx_bufsize = 1518 + RTE_PKTMBUF_HEADROOM;
722 dev_info->max_rx_pktlen = 16384; /* includes CRC, cf MAXFRS register */
723 dev_info->speed_capa = ETH_LINK_SPEED_10G;
724 dev_info->max_mac_addrs = VMXNET3_MAX_MAC_ADDRS;
726 dev_info->default_txconf.txq_flags = ETH_TXQ_FLAGS_NOXSUMSCTP;
727 dev_info->flow_type_rss_offloads = VMXNET3_RSS_OFFLOAD_ALL;
729 dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
730 .nb_max = VMXNET3_RX_RING_MAX_SIZE,
731 .nb_min = VMXNET3_DEF_RX_RING_SIZE,
735 dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
736 .nb_max = VMXNET3_TX_RING_MAX_SIZE,
737 .nb_min = VMXNET3_DEF_TX_RING_SIZE,
739 .nb_seg_max = VMXNET3_TX_MAX_SEG,
740 .nb_mtu_seg_max = VMXNET3_MAX_TXD_PER_PKT,
743 dev_info->rx_offload_capa =
744 DEV_RX_OFFLOAD_VLAN_STRIP |
745 DEV_RX_OFFLOAD_UDP_CKSUM |
746 DEV_RX_OFFLOAD_TCP_CKSUM |
747 DEV_RX_OFFLOAD_TCP_LRO;
749 dev_info->tx_offload_capa =
750 DEV_TX_OFFLOAD_VLAN_INSERT |
751 DEV_TX_OFFLOAD_TCP_CKSUM |
752 DEV_TX_OFFLOAD_UDP_CKSUM |
753 DEV_TX_OFFLOAD_TCP_TSO;
756 static const uint32_t *
757 vmxnet3_dev_supported_ptypes_get(struct rte_eth_dev *dev)
759 static const uint32_t ptypes[] = {
760 RTE_PTYPE_L3_IPV4_EXT,
765 if (dev->rx_pkt_burst == vmxnet3_recv_pkts)
771 vmxnet3_mac_addr_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr)
773 struct vmxnet3_hw *hw = dev->data->dev_private;
775 vmxnet3_write_mac(hw, mac_addr->addr_bytes);
778 /* return 0 means link status changed, -1 means not changed */
780 vmxnet3_dev_link_update(struct rte_eth_dev *dev,
781 __rte_unused int wait_to_complete)
783 struct vmxnet3_hw *hw = dev->data->dev_private;
784 struct rte_eth_link old, link;
787 /* Link status doesn't change for stopped dev */
788 if (dev->data->dev_started == 0)
791 memset(&link, 0, sizeof(link));
792 vmxnet3_dev_atomic_read_link_status(dev, &old);
794 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, VMXNET3_CMD_GET_LINK);
795 ret = VMXNET3_READ_BAR1_REG(hw, VMXNET3_REG_CMD);
798 link.link_status = ETH_LINK_UP;
799 link.link_duplex = ETH_LINK_FULL_DUPLEX;
800 link.link_speed = ETH_SPEED_NUM_10G;
801 link.link_autoneg = ETH_LINK_SPEED_FIXED;
804 vmxnet3_dev_atomic_write_link_status(dev, &link);
806 return (old.link_status == link.link_status) ? -1 : 0;
809 /* Updating rxmode through Vmxnet3_DriverShared structure in adapter */
811 vmxnet3_dev_set_rxmode(struct vmxnet3_hw *hw, uint32_t feature, int set)
813 struct Vmxnet3_RxFilterConf *rxConf = &hw->shared->devRead.rxFilterConf;
816 rxConf->rxMode = rxConf->rxMode | feature;
818 rxConf->rxMode = rxConf->rxMode & (~feature);
820 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, VMXNET3_CMD_UPDATE_RX_MODE);
823 /* Promiscuous supported only if Vmxnet3_DriverShared is initialized in adapter */
825 vmxnet3_dev_promiscuous_enable(struct rte_eth_dev *dev)
827 struct vmxnet3_hw *hw = dev->data->dev_private;
828 uint32_t *vf_table = hw->shared->devRead.rxFilterConf.vfTable;
830 memset(vf_table, 0, VMXNET3_VFT_TABLE_SIZE);
831 vmxnet3_dev_set_rxmode(hw, VMXNET3_RXM_PROMISC, 1);
833 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD,
834 VMXNET3_CMD_UPDATE_VLAN_FILTERS);
837 /* Promiscuous supported only if Vmxnet3_DriverShared is initialized in adapter */
839 vmxnet3_dev_promiscuous_disable(struct rte_eth_dev *dev)
841 struct vmxnet3_hw *hw = dev->data->dev_private;
842 uint32_t *vf_table = hw->shared->devRead.rxFilterConf.vfTable;
844 memcpy(vf_table, hw->shadow_vfta, VMXNET3_VFT_TABLE_SIZE);
845 vmxnet3_dev_set_rxmode(hw, VMXNET3_RXM_PROMISC, 0);
846 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD,
847 VMXNET3_CMD_UPDATE_VLAN_FILTERS);
850 /* Allmulticast supported only if Vmxnet3_DriverShared is initialized in adapter */
852 vmxnet3_dev_allmulticast_enable(struct rte_eth_dev *dev)
854 struct vmxnet3_hw *hw = dev->data->dev_private;
856 vmxnet3_dev_set_rxmode(hw, VMXNET3_RXM_ALL_MULTI, 1);
859 /* Allmulticast supported only if Vmxnet3_DriverShared is initialized in adapter */
861 vmxnet3_dev_allmulticast_disable(struct rte_eth_dev *dev)
863 struct vmxnet3_hw *hw = dev->data->dev_private;
865 vmxnet3_dev_set_rxmode(hw, VMXNET3_RXM_ALL_MULTI, 0);
868 /* Enable/disable filter on vlan */
870 vmxnet3_dev_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vid, int on)
872 struct vmxnet3_hw *hw = dev->data->dev_private;
873 struct Vmxnet3_RxFilterConf *rxConf = &hw->shared->devRead.rxFilterConf;
874 uint32_t *vf_table = rxConf->vfTable;
876 /* save state for restore */
878 VMXNET3_SET_VFTABLE_ENTRY(hw->shadow_vfta, vid);
880 VMXNET3_CLEAR_VFTABLE_ENTRY(hw->shadow_vfta, vid);
882 /* don't change active filter if in promiscuous mode */
883 if (rxConf->rxMode & VMXNET3_RXM_PROMISC)
886 /* set in hardware */
888 VMXNET3_SET_VFTABLE_ENTRY(vf_table, vid);
890 VMXNET3_CLEAR_VFTABLE_ENTRY(vf_table, vid);
892 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD,
893 VMXNET3_CMD_UPDATE_VLAN_FILTERS);
898 vmxnet3_dev_vlan_offload_set(struct rte_eth_dev *dev, int mask)
900 struct vmxnet3_hw *hw = dev->data->dev_private;
901 Vmxnet3_DSDevRead *devRead = &hw->shared->devRead;
902 uint32_t *vf_table = devRead->rxFilterConf.vfTable;
904 if (mask & ETH_VLAN_STRIP_MASK) {
905 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
906 devRead->misc.uptFeatures |= UPT1_F_RXVLAN;
908 devRead->misc.uptFeatures &= ~UPT1_F_RXVLAN;
910 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD,
911 VMXNET3_CMD_UPDATE_FEATURE);
914 if (mask & ETH_VLAN_FILTER_MASK) {
915 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
916 memcpy(vf_table, hw->shadow_vfta, VMXNET3_VFT_TABLE_SIZE);
918 memset(vf_table, 0xff, VMXNET3_VFT_TABLE_SIZE);
920 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD,
921 VMXNET3_CMD_UPDATE_VLAN_FILTERS);
925 #if PROCESS_SYS_EVENTS == 1
927 vmxnet3_process_events(struct vmxnet3_hw *hw)
929 uint32_t events = hw->shared->ecr;
932 PMD_INIT_LOG(ERR, "No events to process");
937 * ECR bits when written with 1b are cleared. Hence write
938 * events back to ECR so that the bits which were set will be reset.
940 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_ECR, events);
942 /* Check if link state has changed */
943 if (events & VMXNET3_ECR_LINK)
945 "Process events in %s(): VMXNET3_ECR_LINK event",
948 /* Check if there is an error on xmit/recv queues */
949 if (events & (VMXNET3_ECR_TQERR | VMXNET3_ECR_RQERR)) {
950 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD,
951 VMXNET3_CMD_GET_QUEUE_STATUS);
953 if (hw->tqd_start->status.stopped)
954 PMD_INIT_LOG(ERR, "tq error 0x%x",
955 hw->tqd_start->status.error);
957 if (hw->rqd_start->status.stopped)
958 PMD_INIT_LOG(ERR, "rq error 0x%x",
959 hw->rqd_start->status.error);
961 /* Reset the device */
962 /* Have to reset the device */
965 if (events & VMXNET3_ECR_DIC)
966 PMD_INIT_LOG(ERR, "Device implementation change event.");
968 if (events & VMXNET3_ECR_DEBUG)
969 PMD_INIT_LOG(ERR, "Debug event generated by device.");
973 RTE_PMD_REGISTER_PCI(net_vmxnet3, rte_vmxnet3_pmd.pci_drv);
974 RTE_PMD_REGISTER_PCI_TABLE(net_vmxnet3, pci_id_vmxnet3_map);
975 RTE_PMD_REGISTER_KMOD_DEP(net_vmxnet3, "* igb_uio | uio_pci_generic | vfio");