drivers/net/vmxnet3/vmxnet3_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2010-2015 Intel Corporation
   3  */
   4
   5 #include <sys/queue.h>
   6 #include <stdio.h>
   7 #include <errno.h>
   8 #include <stdint.h>
   9 #include <string.h>
  10 #include <unistd.h>
  11 #include <stdarg.h>
  12 #include <fcntl.h>
  13 #include <inttypes.h>
  14 #include <rte_byteorder.h>
  15 #include <rte_common.h>
  16 #include <rte_cycles.h>
  17
  18 #include <rte_interrupts.h>
  19 #include <rte_log.h>
  20 #include <rte_debug.h>
  21 #include <rte_pci.h>
  22 #include <rte_bus_pci.h>
  23 #include <rte_branch_prediction.h>
  24 #include <rte_memory.h>
  25 #include <rte_memzone.h>
  26 #include <rte_eal.h>
  27 #include <rte_alarm.h>
  28 #include <rte_ether.h>
  29 #include <ethdev_driver.h>
  30 #include <ethdev_pci.h>
  31 #include <rte_string_fns.h>
  32 #include <rte_malloc.h>
  33 #include <rte_dev.h>
  34
  35 #include "base/vmxnet3_defs.h"
  36
  37 #include "vmxnet3_ring.h"
  38 #include "vmxnet3_logs.h"
  39 #include "vmxnet3_ethdev.h"
  40
  41 #define PROCESS_SYS_EVENTS 0
  42
  43 #define VMXNET3_TX_MAX_SEG      UINT8_MAX
  44
  45 #define VMXNET3_TX_OFFLOAD_CAP          \
  46         (DEV_TX_OFFLOAD_VLAN_INSERT |   \
  47          DEV_TX_OFFLOAD_TCP_CKSUM |     \
  48          DEV_TX_OFFLOAD_UDP_CKSUM |     \
  49          DEV_TX_OFFLOAD_TCP_TSO |       \
  50          DEV_TX_OFFLOAD_MULTI_SEGS)
  51
  52 #define VMXNET3_RX_OFFLOAD_CAP          \
  53         (DEV_RX_OFFLOAD_VLAN_STRIP |    \
  54          DEV_RX_OFFLOAD_VLAN_FILTER |   \
  55          DEV_RX_OFFLOAD_SCATTER |       \
  56          DEV_RX_OFFLOAD_UDP_CKSUM |     \
  57          DEV_RX_OFFLOAD_TCP_CKSUM |     \
  58          DEV_RX_OFFLOAD_TCP_LRO |       \
  59          DEV_RX_OFFLOAD_JUMBO_FRAME |   \
  60          DEV_RX_OFFLOAD_RSS_HASH)
  61
  62 int vmxnet3_segs_dynfield_offset = -1;
  63
  64 static int eth_vmxnet3_dev_init(struct rte_eth_dev *eth_dev);
  65 static int eth_vmxnet3_dev_uninit(struct rte_eth_dev *eth_dev);
  66 static int vmxnet3_dev_configure(struct rte_eth_dev *dev);
  67 static int vmxnet3_dev_start(struct rte_eth_dev *dev);
  68 static int vmxnet3_dev_stop(struct rte_eth_dev *dev);
  69 static int vmxnet3_dev_close(struct rte_eth_dev *dev);
  70 static int vmxnet3_dev_reset(struct rte_eth_dev *dev);
  71 static void vmxnet3_dev_set_rxmode(struct vmxnet3_hw *hw, uint32_t feature, int set);
  72 static int vmxnet3_dev_promiscuous_enable(struct rte_eth_dev *dev);
  73 static int vmxnet3_dev_promiscuous_disable(struct rte_eth_dev *dev);
  74 static int vmxnet3_dev_allmulticast_enable(struct rte_eth_dev *dev);
  75 static int vmxnet3_dev_allmulticast_disable(struct rte_eth_dev *dev);
  76 static int __vmxnet3_dev_link_update(struct rte_eth_dev *dev,
  77                                      int wait_to_complete);
  78 static int vmxnet3_dev_link_update(struct rte_eth_dev *dev,
  79                                    int wait_to_complete);
  80 static void vmxnet3_hw_stats_save(struct vmxnet3_hw *hw);
  81 static int vmxnet3_dev_stats_get(struct rte_eth_dev *dev,
  82                                   struct rte_eth_stats *stats);
  83 static int vmxnet3_dev_stats_reset(struct rte_eth_dev *dev);
  84 static int vmxnet3_dev_xstats_get_names(struct rte_eth_dev *dev,
  85                                         struct rte_eth_xstat_name *xstats,
  86                                         unsigned int n);
  87 static int vmxnet3_dev_xstats_get(struct rte_eth_dev *dev,
  88                                   struct rte_eth_xstat *xstats, unsigned int n);
  89 static int vmxnet3_dev_info_get(struct rte_eth_dev *dev,
  90                                 struct rte_eth_dev_info *dev_info);
  91 static const uint32_t *
  92 vmxnet3_dev_supported_ptypes_get(struct rte_eth_dev *dev);
  93 static int vmxnet3_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
  94 static int vmxnet3_dev_vlan_filter_set(struct rte_eth_dev *dev,
  95                                        uint16_t vid, int on);
  96 static int vmxnet3_dev_vlan_offload_set(struct rte_eth_dev *dev, int mask);
  97 static int vmxnet3_mac_addr_set(struct rte_eth_dev *dev,
  98                                  struct rte_ether_addr *mac_addr);
  99 static void vmxnet3_interrupt_handler(void *param);
 100
 101 /*
 102  * The set of PCI devices this driver supports
 103  */
 104 #define VMWARE_PCI_VENDOR_ID 0x15AD
 105 #define VMWARE_DEV_ID_VMXNET3 0x07B0
 106 static const struct rte_pci_id pci_id_vmxnet3_map[] = {
 107         { RTE_PCI_DEVICE(VMWARE_PCI_VENDOR_ID, VMWARE_DEV_ID_VMXNET3) },
 108         { .vendor_id = 0, /* sentinel */ },
 109 };
 110
 111 static const struct eth_dev_ops vmxnet3_eth_dev_ops = {
 112         .dev_configure        = vmxnet3_dev_configure,
 113         .dev_start            = vmxnet3_dev_start,
 114         .dev_stop             = vmxnet3_dev_stop,
 115         .dev_close            = vmxnet3_dev_close,
 116         .dev_reset            = vmxnet3_dev_reset,
 117         .promiscuous_enable   = vmxnet3_dev_promiscuous_enable,
 118         .promiscuous_disable  = vmxnet3_dev_promiscuous_disable,
 119         .allmulticast_enable  = vmxnet3_dev_allmulticast_enable,
 120         .allmulticast_disable = vmxnet3_dev_allmulticast_disable,
 121         .link_update          = vmxnet3_dev_link_update,
 122         .stats_get            = vmxnet3_dev_stats_get,
 123         .xstats_get_names     = vmxnet3_dev_xstats_get_names,
 124         .xstats_get           = vmxnet3_dev_xstats_get,
 125         .stats_reset          = vmxnet3_dev_stats_reset,
 126         .mac_addr_set         = vmxnet3_mac_addr_set,
 127         .dev_infos_get        = vmxnet3_dev_info_get,
 128         .dev_supported_ptypes_get = vmxnet3_dev_supported_ptypes_get,
 129         .mtu_set              = vmxnet3_dev_mtu_set,
 130         .vlan_filter_set      = vmxnet3_dev_vlan_filter_set,
 131         .vlan_offload_set     = vmxnet3_dev_vlan_offload_set,
 132         .rx_queue_setup       = vmxnet3_dev_rx_queue_setup,
 133         .rx_queue_release     = vmxnet3_dev_rx_queue_release,
 134         .tx_queue_setup       = vmxnet3_dev_tx_queue_setup,
 135         .tx_queue_release     = vmxnet3_dev_tx_queue_release,
 136 };
 137
 138 struct vmxnet3_xstats_name_off {
 139         char name[RTE_ETH_XSTATS_NAME_SIZE];
 140         unsigned int offset;
 141 };
 142
 143 /* tx_qX_ is prepended to the name string here */
 144 static const struct vmxnet3_xstats_name_off vmxnet3_txq_stat_strings[] = {
 145         {"drop_total",         offsetof(struct vmxnet3_txq_stats, drop_total)},
 146         {"drop_too_many_segs", offsetof(struct vmxnet3_txq_stats, drop_too_many_segs)},
 147         {"drop_tso",           offsetof(struct vmxnet3_txq_stats, drop_tso)},
 148         {"tx_ring_full",       offsetof(struct vmxnet3_txq_stats, tx_ring_full)},
 149 };
 150
 151 /* rx_qX_ is prepended to the name string here */
 152 static const struct vmxnet3_xstats_name_off vmxnet3_rxq_stat_strings[] = {
 153         {"drop_total",           offsetof(struct vmxnet3_rxq_stats, drop_total)},
 154         {"drop_err",             offsetof(struct vmxnet3_rxq_stats, drop_err)},
 155         {"drop_fcs",             offsetof(struct vmxnet3_rxq_stats, drop_fcs)},
 156         {"rx_buf_alloc_failure", offsetof(struct vmxnet3_rxq_stats, rx_buf_alloc_failure)},
 157 };
 158
 159 static const struct rte_memzone *
 160 gpa_zone_reserve(struct rte_eth_dev *dev, uint32_t size,
 161                  const char *post_string, int socket_id,
 162                  uint16_t align, bool reuse)
 163 {
 164         char z_name[RTE_MEMZONE_NAMESIZE];
 165         const struct rte_memzone *mz;
 166
 167         snprintf(z_name, sizeof(z_name), "eth_p%d_%s",
 168                         dev->data->port_id, post_string);
 169
 170         mz = rte_memzone_lookup(z_name);
 171         if (!reuse) {
 172                 if (mz)
 173                         rte_memzone_free(mz);
 174                 return rte_memzone_reserve_aligned(z_name, size, socket_id,
 175                                 RTE_MEMZONE_IOVA_CONTIG, align);
 176         }
 177
 178         if (mz)
 179                 return mz;
 180
 181         return rte_memzone_reserve_aligned(z_name, size, socket_id,
 182                         RTE_MEMZONE_IOVA_CONTIG, align);
 183 }
 184
 185 /*
 186  * This function is based on vmxnet3_disable_intr()
 187  */
 188 static void
 189 vmxnet3_disable_intr(struct vmxnet3_hw *hw)
 190 {
 191         int i;
 192
 193         PMD_INIT_FUNC_TRACE();
 194
 195         hw->shared->devRead.intrConf.intrCtrl |= VMXNET3_IC_DISABLE_ALL;
 196         for (i = 0; i < hw->num_intrs; i++)
 197                 VMXNET3_WRITE_BAR0_REG(hw, VMXNET3_REG_IMR + i * 8, 1);
 198 }
 199
 200 static void
 201 vmxnet3_enable_intr(struct vmxnet3_hw *hw)
 202 {
 203         int i;
 204
 205         PMD_INIT_FUNC_TRACE();
 206
 207         hw->shared->devRead.intrConf.intrCtrl &= ~VMXNET3_IC_DISABLE_ALL;
 208         for (i = 0; i < hw->num_intrs; i++)
 209                 VMXNET3_WRITE_BAR0_REG(hw, VMXNET3_REG_IMR + i * 8, 0);
 210 }
 211
 212 /*
 213  * Gets tx data ring descriptor size.
 214  */
 215 static uint16_t
 216 eth_vmxnet3_txdata_get(struct vmxnet3_hw *hw)
 217 {
 218         uint16 txdata_desc_size;
 219
 220         VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD,
 221                                VMXNET3_CMD_GET_TXDATA_DESC_SIZE);
 222         txdata_desc_size = VMXNET3_READ_BAR1_REG(hw, VMXNET3_REG_CMD);
 223
 224         return (txdata_desc_size < VMXNET3_TXDATA_DESC_MIN_SIZE ||
 225                 txdata_desc_size > VMXNET3_TXDATA_DESC_MAX_SIZE ||
 226                 txdata_desc_size & VMXNET3_TXDATA_DESC_SIZE_MASK) ?
 227                 sizeof(struct Vmxnet3_TxDataDesc) : txdata_desc_size;
 228 }
 229
 230 /*
 231  * It returns 0 on success.
 232  */
 233 static int
 234 eth_vmxnet3_dev_init(struct rte_eth_dev *eth_dev)
 235 {
 236         struct rte_pci_device *pci_dev;
 237         struct vmxnet3_hw *hw = eth_dev->data->dev_private;
 238         uint32_t mac_hi, mac_lo, ver;
 239         struct rte_eth_link link;
 240         static const struct rte_mbuf_dynfield vmxnet3_segs_dynfield_desc = {
 241                 .name = VMXNET3_SEGS_DYNFIELD_NAME,
 242                 .size = sizeof(vmxnet3_segs_dynfield_t),
 243                 .align = __alignof__(vmxnet3_segs_dynfield_t),
 244         };
 245
 246         PMD_INIT_FUNC_TRACE();
 247
 248         eth_dev->dev_ops = &vmxnet3_eth_dev_ops;
 249         eth_dev->rx_pkt_burst = &vmxnet3_recv_pkts;
 250         eth_dev->tx_pkt_burst = &vmxnet3_xmit_pkts;
 251         eth_dev->tx_pkt_prepare = vmxnet3_prep_pkts;
 252         pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
 253
 254         /* extra mbuf field is required to guess MSS */
 255         vmxnet3_segs_dynfield_offset =
 256                 rte_mbuf_dynfield_register(&vmxnet3_segs_dynfield_desc);
 257         if (vmxnet3_segs_dynfield_offset < 0) {
 258                 PMD_INIT_LOG(ERR, "Cannot register mbuf field.");
 259                 return -rte_errno;
 260         }
 261
 262         /*
 263          * for secondary processes, we don't initialize any further as primary
 264          * has already done this work.
 265          */
 266         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
 267                 return 0;
 268
 269         rte_eth_copy_pci_info(eth_dev, pci_dev);
 270         eth_dev->data->dev_flags |= RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS;
 271
 272         /* Vendor and Device ID need to be set before init of shared code */
 273         hw->device_id = pci_dev->id.device_id;
 274         hw->vendor_id = pci_dev->id.vendor_id;
 275         hw->hw_addr0 = (void *)pci_dev->mem_resource[0].addr;
 276         hw->hw_addr1 = (void *)pci_dev->mem_resource[1].addr;
 277
 278         hw->num_rx_queues = 1;
 279         hw->num_tx_queues = 1;
 280         hw->bufs_per_pkt = 1;
 281
 282         /* Check h/w version compatibility with driver. */
 283         ver = VMXNET3_READ_BAR1_REG(hw, VMXNET3_REG_VRRS);
 284         PMD_INIT_LOG(DEBUG, "Hardware version : %d", ver);
 285
 286         if (ver & (1 << VMXNET3_REV_4)) {
 287                 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_VRRS,
 288                                        1 << VMXNET3_REV_4);
 289                 hw->version = VMXNET3_REV_4 + 1;
 290         } else if (ver & (1 << VMXNET3_REV_3)) {
 291                 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_VRRS,
 292                                        1 << VMXNET3_REV_3);
 293                 hw->version = VMXNET3_REV_3 + 1;
 294         } else if (ver & (1 << VMXNET3_REV_2)) {
 295                 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_VRRS,
 296                                        1 << VMXNET3_REV_2);
 297                 hw->version = VMXNET3_REV_2 + 1;
 298         } else if (ver & (1 << VMXNET3_REV_1)) {
 299                 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_VRRS,
 300                                        1 << VMXNET3_REV_1);
 301                 hw->version = VMXNET3_REV_1 + 1;
 302         } else {
 303                 PMD_INIT_LOG(ERR, "Incompatible hardware version: %d", ver);
 304                 return -EIO;
 305         }
 306
 307         PMD_INIT_LOG(DEBUG, "Using device version %d\n", hw->version);
 308
 309         /* Check UPT version compatibility with driver. */
 310         ver = VMXNET3_READ_BAR1_REG(hw, VMXNET3_REG_UVRS);
 311         PMD_INIT_LOG(DEBUG, "UPT hardware version : %d", ver);
 312         if (ver & 0x1)
 313                 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_UVRS, 1);
 314         else {
 315                 PMD_INIT_LOG(ERR, "Incompatible UPT version.");
 316                 return -EIO;
 317         }
 318
 319         /* Getting MAC Address */
 320         mac_lo = VMXNET3_READ_BAR1_REG(hw, VMXNET3_REG_MACL);
 321         mac_hi = VMXNET3_READ_BAR1_REG(hw, VMXNET3_REG_MACH);
 322         memcpy(hw->perm_addr, &mac_lo, 4);
 323         memcpy(hw->perm_addr + 4, &mac_hi, 2);
 324
 325         /* Allocate memory for storing MAC addresses */
 326         eth_dev->data->mac_addrs = rte_zmalloc("vmxnet3", RTE_ETHER_ADDR_LEN *
 327                                                VMXNET3_MAX_MAC_ADDRS, 0);
 328         if (eth_dev->data->mac_addrs == NULL) {
 329                 PMD_INIT_LOG(ERR,
 330                              "Failed to allocate %d bytes needed to store MAC addresses",
 331                              RTE_ETHER_ADDR_LEN * VMXNET3_MAX_MAC_ADDRS);
 332                 return -ENOMEM;
 333         }
 334         /* Copy the permanent MAC address */
 335         rte_ether_addr_copy((struct rte_ether_addr *)hw->perm_addr,
 336                         &eth_dev->data->mac_addrs[0]);
 337
 338         PMD_INIT_LOG(DEBUG, "MAC Address : %02x:%02x:%02x:%02x:%02x:%02x",
 339                      hw->perm_addr[0], hw->perm_addr[1], hw->perm_addr[2],
 340                      hw->perm_addr[3], hw->perm_addr[4], hw->perm_addr[5]);
 341
 342         /* Put device in Quiesce Mode */
 343         VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, VMXNET3_CMD_QUIESCE_DEV);
 344
 345         /* allow untagged pkts */
 346         VMXNET3_SET_VFTABLE_ENTRY(hw->shadow_vfta, 0);
 347
 348         hw->txdata_desc_size = VMXNET3_VERSION_GE_3(hw) ?
 349                 eth_vmxnet3_txdata_get(hw) : sizeof(struct Vmxnet3_TxDataDesc);
 350
 351         hw->rxdata_desc_size = VMXNET3_VERSION_GE_3(hw) ?
 352                 VMXNET3_DEF_RXDATA_DESC_SIZE : 0;
 353         RTE_ASSERT((hw->rxdata_desc_size & ~VMXNET3_RXDATA_DESC_SIZE_MASK) ==
 354                    hw->rxdata_desc_size);
 355
 356         /* clear shadow stats */
 357         memset(hw->saved_tx_stats, 0, sizeof(hw->saved_tx_stats));
 358         memset(hw->saved_rx_stats, 0, sizeof(hw->saved_rx_stats));
 359
 360         /* clear snapshot stats */
 361         memset(hw->snapshot_tx_stats, 0, sizeof(hw->snapshot_tx_stats));
 362         memset(hw->snapshot_rx_stats, 0, sizeof(hw->snapshot_rx_stats));
 363
 364         /* set the initial link status */
 365         memset(&link, 0, sizeof(link));
 366         link.link_duplex = ETH_LINK_FULL_DUPLEX;
 367         link.link_speed = ETH_SPEED_NUM_10G;
 368         link.link_autoneg = ETH_LINK_FIXED;
 369         rte_eth_linkstatus_set(eth_dev, &link);
 370
 371         return 0;
 372 }
 373
 374 static int
 375 eth_vmxnet3_dev_uninit(struct rte_eth_dev *eth_dev)
 376 {
 377         struct vmxnet3_hw *hw = eth_dev->data->dev_private;
 378
 379         PMD_INIT_FUNC_TRACE();
 380
 381         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
 382                 return 0;
 383
 384         if (hw->adapter_stopped == 0) {
 385                 PMD_INIT_LOG(DEBUG, "Device has not been closed.");
 386                 return -EBUSY;
 387         }
 388
 389         return 0;
 390 }
 391
 392 static int eth_vmxnet3_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
 393         struct rte_pci_device *pci_dev)
 394 {
 395         return rte_eth_dev_pci_generic_probe(pci_dev,
 396                 sizeof(struct vmxnet3_hw), eth_vmxnet3_dev_init);
 397 }
 398
 399 static int eth_vmxnet3_pci_remove(struct rte_pci_device *pci_dev)
 400 {
 401         return rte_eth_dev_pci_generic_remove(pci_dev, eth_vmxnet3_dev_uninit);
 402 }
 403
 404 static struct rte_pci_driver rte_vmxnet3_pmd = {
 405         .id_table = pci_id_vmxnet3_map,
 406         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
 407         .probe = eth_vmxnet3_pci_probe,
 408         .remove = eth_vmxnet3_pci_remove,
 409 };
 410
 411 static int
 412 vmxnet3_dev_configure(struct rte_eth_dev *dev)
 413 {
 414         const struct rte_memzone *mz;
 415         struct vmxnet3_hw *hw = dev->data->dev_private;
 416         size_t size;
 417
 418         PMD_INIT_FUNC_TRACE();
 419
 420         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG)
 421                 dev->data->dev_conf.rxmode.offloads |= DEV_RX_OFFLOAD_RSS_HASH;
 422
 423         if (dev->data->nb_tx_queues > VMXNET3_MAX_TX_QUEUES ||
 424             dev->data->nb_rx_queues > VMXNET3_MAX_RX_QUEUES) {
 425                 PMD_INIT_LOG(ERR, "ERROR: Number of queues not supported");
 426                 return -EINVAL;
 427         }
 428
 429         if (!rte_is_power_of_2(dev->data->nb_rx_queues)) {
 430                 PMD_INIT_LOG(ERR, "ERROR: Number of rx queues not power of 2");
 431                 return -EINVAL;
 432         }
 433
 434         size = dev->data->nb_rx_queues * sizeof(struct Vmxnet3_TxQueueDesc) +
 435                 dev->data->nb_tx_queues * sizeof(struct Vmxnet3_RxQueueDesc);
 436
 437         if (size > UINT16_MAX)
 438                 return -EINVAL;
 439
 440         hw->num_rx_queues = (uint8_t)dev->data->nb_rx_queues;
 441         hw->num_tx_queues = (uint8_t)dev->data->nb_tx_queues;
 442
 443         /*
 444          * Allocate a memzone for Vmxnet3_DriverShared - Vmxnet3_DSDevRead
 445          * on current socket
 446          */
 447         mz = gpa_zone_reserve(dev, sizeof(struct Vmxnet3_DriverShared),
 448                               "shared", rte_socket_id(), 8, 1);
 449
 450         if (mz == NULL) {
 451                 PMD_INIT_LOG(ERR, "ERROR: Creating shared zone");
 452                 return -ENOMEM;
 453         }
 454         memset(mz->addr, 0, mz->len);
 455
 456         hw->shared = mz->addr;
 457         hw->sharedPA = mz->iova;
 458
 459         /*
 460          * Allocate a memzone for Vmxnet3_RxQueueDesc - Vmxnet3_TxQueueDesc
 461          * on current socket.
 462          *
 463          * We cannot reuse this memzone from previous allocation as its size
 464          * depends on the number of tx and rx queues, which could be different
 465          * from one config to another.
 466          */
 467         mz = gpa_zone_reserve(dev, size, "queuedesc", rte_socket_id(),
 468                               VMXNET3_QUEUE_DESC_ALIGN, 0);
 469         if (mz == NULL) {
 470                 PMD_INIT_LOG(ERR, "ERROR: Creating queue descriptors zone");
 471                 return -ENOMEM;
 472         }
 473         memset(mz->addr, 0, mz->len);
 474
 475         hw->tqd_start = (Vmxnet3_TxQueueDesc *)mz->addr;
 476         hw->rqd_start = (Vmxnet3_RxQueueDesc *)(hw->tqd_start + hw->num_tx_queues);
 477
 478         hw->queueDescPA = mz->iova;
 479         hw->queue_desc_len = (uint16_t)size;
 480
 481         if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_RSS) {
 482                 /* Allocate memory structure for UPT1_RSSConf and configure */
 483                 mz = gpa_zone_reserve(dev, sizeof(struct VMXNET3_RSSConf),
 484                                       "rss_conf", rte_socket_id(),
 485                                       RTE_CACHE_LINE_SIZE, 1);
 486                 if (mz == NULL) {
 487                         PMD_INIT_LOG(ERR,
 488                                      "ERROR: Creating rss_conf structure zone");
 489                         return -ENOMEM;
 490                 }
 491                 memset(mz->addr, 0, mz->len);
 492
 493                 hw->rss_conf = mz->addr;
 494                 hw->rss_confPA = mz->iova;
 495         }
 496
 497         return 0;
 498 }
 499
 500 static void
 501 vmxnet3_write_mac(struct vmxnet3_hw *hw, const uint8_t *addr)
 502 {
 503         uint32_t val;
 504
 505         PMD_INIT_LOG(DEBUG,
 506                      "Writing MAC Address : %02x:%02x:%02x:%02x:%02x:%02x",
 507                      addr[0], addr[1], addr[2],
 508                      addr[3], addr[4], addr[5]);
 509
 510         memcpy(&val, addr, 4);
 511         VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_MACL, val);
 512
 513         memcpy(&val, addr + 4, 2);
 514         VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_MACH, val);
 515 }
 516
 517 static int
 518 vmxnet3_dev_setup_memreg(struct rte_eth_dev *dev)
 519 {
 520         struct vmxnet3_hw *hw = dev->data->dev_private;
 521         Vmxnet3_DriverShared *shared = hw->shared;
 522         Vmxnet3_CmdInfo *cmdInfo;
 523         struct rte_mempool *mp[VMXNET3_MAX_RX_QUEUES];
 524         uint8_t index[VMXNET3_MAX_RX_QUEUES + VMXNET3_MAX_TX_QUEUES];
 525         uint32_t num, i, j, size;
 526
 527         if (hw->memRegsPA == 0) {
 528                 const struct rte_memzone *mz;
 529
 530                 size = sizeof(Vmxnet3_MemRegs) +
 531                         (VMXNET3_MAX_RX_QUEUES + VMXNET3_MAX_TX_QUEUES) *
 532                         sizeof(Vmxnet3_MemoryRegion);
 533
 534                 mz = gpa_zone_reserve(dev, size, "memRegs", rte_socket_id(), 8,
 535                                       1);
 536                 if (mz == NULL) {
 537                         PMD_INIT_LOG(ERR, "ERROR: Creating memRegs zone");
 538                         return -ENOMEM;
 539                 }
 540                 memset(mz->addr, 0, mz->len);
 541                 hw->memRegs = mz->addr;
 542                 hw->memRegsPA = mz->iova;
 543         }
 544
 545         num = hw->num_rx_queues;
 546
 547         for (i = 0; i < num; i++) {
 548                 vmxnet3_rx_queue_t *rxq = dev->data->rx_queues[i];
 549
 550                 mp[i] = rxq->mp;
 551                 index[i] = 1 << i;
 552         }
 553
 554         /*
 555          * The same mempool could be used by multiple queues. In such a case,
 556          * remove duplicate mempool entries. Only one entry is kept with
 557          * bitmask indicating queues that are using this mempool.
 558          */
 559         for (i = 1; i < num; i++) {
 560                 for (j = 0; j < i; j++) {
 561                         if (mp[i] == mp[j]) {
 562                                 mp[i] = NULL;
 563                                 index[j] |= 1 << i;
 564                                 break;
 565                         }
 566                 }
 567         }
 568
 569         j = 0;
 570         for (i = 0; i < num; i++) {
 571                 if (mp[i] == NULL)
 572                         continue;
 573
 574                 Vmxnet3_MemoryRegion *mr = &hw->memRegs->memRegs[j];
 575
 576                 mr->startPA =
 577                         (uintptr_t)STAILQ_FIRST(&mp[i]->mem_list)->iova;
 578                 mr->length = STAILQ_FIRST(&mp[i]->mem_list)->len <= INT32_MAX ?
 579                         STAILQ_FIRST(&mp[i]->mem_list)->len : INT32_MAX;
 580                 mr->txQueueBits = index[i];
 581                 mr->rxQueueBits = index[i];
 582
 583                 PMD_INIT_LOG(INFO,
 584                              "index: %u startPA: %" PRIu64 " length: %u, "
 585                              "rxBits: %x",
 586                              j, mr->startPA, mr->length, mr->rxQueueBits);
 587                 j++;
 588         }
 589         hw->memRegs->numRegs = j;
 590         PMD_INIT_LOG(INFO, "numRegs: %u", j);
 591
 592         size = sizeof(Vmxnet3_MemRegs) +
 593                 (j - 1) * sizeof(Vmxnet3_MemoryRegion);
 594
 595         cmdInfo = &shared->cu.cmdInfo;
 596         cmdInfo->varConf.confVer = 1;
 597         cmdInfo->varConf.confLen = size;
 598         cmdInfo->varConf.confPA = hw->memRegsPA;
 599
 600         return 0;
 601 }
 602
 603 static int
 604 vmxnet3_setup_driver_shared(struct rte_eth_dev *dev)
 605 {
 606         struct rte_eth_conf port_conf = dev->data->dev_conf;
 607         struct vmxnet3_hw *hw = dev->data->dev_private;
 608         uint32_t mtu = dev->data->mtu;
 609         Vmxnet3_DriverShared *shared = hw->shared;
 610         Vmxnet3_DSDevRead *devRead = &shared->devRead;
 611         uint64_t rx_offloads = dev->data->dev_conf.rxmode.offloads;
 612         uint32_t i;
 613         int ret;
 614
 615         hw->mtu = mtu;
 616
 617         shared->magic = VMXNET3_REV1_MAGIC;
 618         devRead->misc.driverInfo.version = VMXNET3_DRIVER_VERSION_NUM;
 619
 620         /* Setting up Guest OS information */
 621         devRead->misc.driverInfo.gos.gosBits   = sizeof(void *) == 4 ?
 622                 VMXNET3_GOS_BITS_32 : VMXNET3_GOS_BITS_64;
 623         devRead->misc.driverInfo.gos.gosType   = VMXNET3_GOS_TYPE_LINUX;
 624         devRead->misc.driverInfo.vmxnet3RevSpt = 1;
 625         devRead->misc.driverInfo.uptVerSpt     = 1;
 626
 627         devRead->misc.mtu = rte_le_to_cpu_32(mtu);
 628         devRead->misc.queueDescPA  = hw->queueDescPA;
 629         devRead->misc.queueDescLen = hw->queue_desc_len;
 630         devRead->misc.numTxQueues  = hw->num_tx_queues;
 631         devRead->misc.numRxQueues  = hw->num_rx_queues;
 632
 633         /*
 634          * Set number of interrupts to 1
 635          * PMD by default disables all the interrupts but this is MUST
 636          * to activate device. It needs at least one interrupt for
 637          * link events to handle
 638          */
 639         hw->num_intrs = devRead->intrConf.numIntrs = 1;
 640         devRead->intrConf.intrCtrl |= VMXNET3_IC_DISABLE_ALL;
 641
 642         for (i = 0; i < hw->num_tx_queues; i++) {
 643                 Vmxnet3_TxQueueDesc *tqd = &hw->tqd_start[i];
 644                 vmxnet3_tx_queue_t *txq  = dev->data->tx_queues[i];
 645
 646                 txq->shared = &hw->tqd_start[i];
 647
 648                 tqd->ctrl.txNumDeferred  = 0;
 649                 tqd->ctrl.txThreshold    = 1;
 650                 tqd->conf.txRingBasePA   = txq->cmd_ring.basePA;
 651                 tqd->conf.compRingBasePA = txq->comp_ring.basePA;
 652                 tqd->conf.dataRingBasePA = txq->data_ring.basePA;
 653
 654                 tqd->conf.txRingSize   = txq->cmd_ring.size;
 655                 tqd->conf.compRingSize = txq->comp_ring.size;
 656                 tqd->conf.dataRingSize = txq->data_ring.size;
 657                 tqd->conf.txDataRingDescSize = txq->txdata_desc_size;
 658                 tqd->conf.intrIdx      = txq->comp_ring.intr_idx;
 659                 tqd->status.stopped    = TRUE;
 660                 tqd->status.error      = 0;
 661                 memset(&tqd->stats, 0, sizeof(tqd->stats));
 662         }
 663
 664         for (i = 0; i < hw->num_rx_queues; i++) {
 665                 Vmxnet3_RxQueueDesc *rqd  = &hw->rqd_start[i];
 666                 vmxnet3_rx_queue_t *rxq   = dev->data->rx_queues[i];
 667
 668                 rxq->shared = &hw->rqd_start[i];
 669
 670                 rqd->conf.rxRingBasePA[0] = rxq->cmd_ring[0].basePA;
 671                 rqd->conf.rxRingBasePA[1] = rxq->cmd_ring[1].basePA;
 672                 rqd->conf.compRingBasePA  = rxq->comp_ring.basePA;
 673
 674                 rqd->conf.rxRingSize[0]   = rxq->cmd_ring[0].size;
 675                 rqd->conf.rxRingSize[1]   = rxq->cmd_ring[1].size;
 676                 rqd->conf.compRingSize    = rxq->comp_ring.size;
 677                 rqd->conf.intrIdx         = rxq->comp_ring.intr_idx;
 678                 if (VMXNET3_VERSION_GE_3(hw)) {
 679                         rqd->conf.rxDataRingBasePA = rxq->data_ring.basePA;
 680                         rqd->conf.rxDataRingDescSize = rxq->data_desc_size;
 681                 }
 682                 rqd->status.stopped       = TRUE;
 683                 rqd->status.error         = 0;
 684                 memset(&rqd->stats, 0, sizeof(rqd->stats));
 685         }
 686
 687         /* RxMode set to 0 of VMXNET3_RXM_xxx */
 688         devRead->rxFilterConf.rxMode = 0;
 689
 690         /* Setting up feature flags */
 691         if (rx_offloads & DEV_RX_OFFLOAD_CHECKSUM)
 692                 devRead->misc.uptFeatures |= VMXNET3_F_RXCSUM;
 693
 694         if (rx_offloads & DEV_RX_OFFLOAD_TCP_LRO) {
 695                 devRead->misc.uptFeatures |= VMXNET3_F_LRO;
 696                 devRead->misc.maxNumRxSG = 0;
 697         }
 698
 699         if (port_conf.rxmode.mq_mode == ETH_MQ_RX_RSS) {
 700                 ret = vmxnet3_rss_configure(dev);
 701                 if (ret != VMXNET3_SUCCESS)
 702                         return ret;
 703
 704                 devRead->misc.uptFeatures |= VMXNET3_F_RSS;
 705                 devRead->rssConfDesc.confVer = 1;
 706                 devRead->rssConfDesc.confLen = sizeof(struct VMXNET3_RSSConf);
 707                 devRead->rssConfDesc.confPA  = hw->rss_confPA;
 708         }
 709
 710         ret = vmxnet3_dev_vlan_offload_set(dev,
 711                         ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK);
 712         if (ret)
 713                 return ret;
 714
 715         vmxnet3_write_mac(hw, dev->data->mac_addrs->addr_bytes);
 716
 717         return VMXNET3_SUCCESS;
 718 }
 719
 720 /*
 721  * Configure device link speed and setup link.
 722  * Must be called after eth_vmxnet3_dev_init. Other wise it might fail
 723  * It returns 0 on success.
 724  */
 725 static int
 726 vmxnet3_dev_start(struct rte_eth_dev *dev)
 727 {
 728         int ret;
 729         struct vmxnet3_hw *hw = dev->data->dev_private;
 730
 731         PMD_INIT_FUNC_TRACE();
 732
 733         /* Save stats before it is reset by CMD_ACTIVATE */
 734         vmxnet3_hw_stats_save(hw);
 735
 736         ret = vmxnet3_setup_driver_shared(dev);
 737         if (ret != VMXNET3_SUCCESS)
 738                 return ret;
 739
 740         /* check if lsc interrupt feature is enabled */
 741         if (dev->data->dev_conf.intr_conf.lsc) {
 742                 struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev->device);
 743
 744                 /* Setup interrupt callback  */
 745                 rte_intr_callback_register(&pci_dev->intr_handle,
 746                                            vmxnet3_interrupt_handler, dev);
 747
 748                 if (rte_intr_enable(&pci_dev->intr_handle) < 0) {
 749                         PMD_INIT_LOG(ERR, "interrupt enable failed");
 750                         return -EIO;
 751                 }
 752         }
 753
 754         /* Exchange shared data with device */
 755         VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_DSAL,
 756                                VMXNET3_GET_ADDR_LO(hw->sharedPA));
 757         VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_DSAH,
 758                                VMXNET3_GET_ADDR_HI(hw->sharedPA));
 759
 760         /* Activate device by register write */
 761         VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, VMXNET3_CMD_ACTIVATE_DEV);
 762         ret = VMXNET3_READ_BAR1_REG(hw, VMXNET3_REG_CMD);
 763
 764         if (ret != 0) {
 765                 PMD_INIT_LOG(ERR, "Device activation: UNSUCCESSFUL");
 766                 return -EINVAL;
 767         }
 768
 769         /* Setup memory region for rx buffers */
 770         ret = vmxnet3_dev_setup_memreg(dev);
 771         if (ret == 0) {
 772                 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD,
 773                                        VMXNET3_CMD_REGISTER_MEMREGS);
 774                 ret = VMXNET3_READ_BAR1_REG(hw, VMXNET3_REG_CMD);
 775                 if (ret != 0)
 776                         PMD_INIT_LOG(DEBUG,
 777                                      "Failed in setup memory region cmd\n");
 778                 ret = 0;
 779         } else {
 780                 PMD_INIT_LOG(DEBUG, "Failed to setup memory region\n");
 781         }
 782
 783         if (VMXNET3_VERSION_GE_4(hw) &&
 784             dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_RSS) {
 785                 /* Check for additional RSS  */
 786                 ret = vmxnet3_v4_rss_configure(dev);
 787                 if (ret != VMXNET3_SUCCESS) {
 788                         PMD_INIT_LOG(ERR, "Failed to configure v4 RSS");
 789                         return ret;
 790                 }
 791         }
 792
 793         /* Disable interrupts */
 794         vmxnet3_disable_intr(hw);
 795
 796         /*
 797          * Load RX queues with blank mbufs and update next2fill index for device
 798          * Update RxMode of the device
 799          */
 800         ret = vmxnet3_dev_rxtx_init(dev);
 801         if (ret != VMXNET3_SUCCESS) {
 802                 PMD_INIT_LOG(ERR, "Device queue init: UNSUCCESSFUL");
 803                 return ret;
 804         }
 805
 806         hw->adapter_stopped = FALSE;
 807
 808         /* Setting proper Rx Mode and issue Rx Mode Update command */
 809         vmxnet3_dev_set_rxmode(hw, VMXNET3_RXM_UCAST | VMXNET3_RXM_BCAST, 1);
 810
 811         if (dev->data->dev_conf.intr_conf.lsc) {
 812                 vmxnet3_enable_intr(hw);
 813
 814                 /*
 815                  * Update link state from device since this won't be
 816                  * done upon starting with lsc in use. This is done
 817                  * only after enabling interrupts to avoid any race
 818                  * where the link state could change without an
 819                  * interrupt being fired.
 820                  */
 821                 __vmxnet3_dev_link_update(dev, 0);
 822         }
 823
 824         return VMXNET3_SUCCESS;
 825 }
 826
 827 /*
 828  * Stop device: disable rx and tx functions to allow for reconfiguring.
 829  */
 830 static int
 831 vmxnet3_dev_stop(struct rte_eth_dev *dev)
 832 {
 833         struct rte_eth_link link;
 834         struct vmxnet3_hw *hw = dev->data->dev_private;
 835
 836         PMD_INIT_FUNC_TRACE();
 837
 838         if (hw->adapter_stopped == 1) {
 839                 PMD_INIT_LOG(DEBUG, "Device already stopped.");
 840                 return 0;
 841         }
 842
 843         /* disable interrupts */
 844         vmxnet3_disable_intr(hw);
 845
 846         if (dev->data->dev_conf.intr_conf.lsc) {
 847                 struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev->device);
 848
 849                 rte_intr_disable(&pci_dev->intr_handle);
 850
 851                 rte_intr_callback_unregister(&pci_dev->intr_handle,
 852                                              vmxnet3_interrupt_handler, dev);
 853         }
 854
 855         /* quiesce the device first */
 856         VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, VMXNET3_CMD_QUIESCE_DEV);
 857         VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_DSAL, 0);
 858         VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_DSAH, 0);
 859
 860         /* reset the device */
 861         VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, VMXNET3_CMD_RESET_DEV);
 862         PMD_INIT_LOG(DEBUG, "Device reset.");
 863
 864         vmxnet3_dev_clear_queues(dev);
 865
 866         /* Clear recorded link status */
 867         memset(&link, 0, sizeof(link));
 868         link.link_duplex = ETH_LINK_FULL_DUPLEX;
 869         link.link_speed = ETH_SPEED_NUM_10G;
 870         link.link_autoneg = ETH_LINK_FIXED;
 871         rte_eth_linkstatus_set(dev, &link);
 872
 873         hw->adapter_stopped = 1;
 874         dev->data->dev_started = 0;
 875
 876         return 0;
 877 }
 878
 879 static void
 880 vmxnet3_free_queues(struct rte_eth_dev *dev)
 881 {
 882         int i;
 883
 884         PMD_INIT_FUNC_TRACE();
 885
 886         for (i = 0; i < dev->data->nb_rx_queues; i++) {
 887                 void *rxq = dev->data->rx_queues[i];
 888
 889                 vmxnet3_dev_rx_queue_release(rxq);
 890         }
 891         dev->data->nb_rx_queues = 0;
 892
 893         for (i = 0; i < dev->data->nb_tx_queues; i++) {
 894                 void *txq = dev->data->tx_queues[i];
 895
 896                 vmxnet3_dev_tx_queue_release(txq);
 897         }
 898         dev->data->nb_tx_queues = 0;
 899 }
 900
 901 /*
 902  * Reset and stop device.
 903  */
 904 static int
 905 vmxnet3_dev_close(struct rte_eth_dev *dev)
 906 {
 907         int ret;
 908         PMD_INIT_FUNC_TRACE();
 909         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
 910                 return 0;
 911
 912         ret = vmxnet3_dev_stop(dev);
 913         vmxnet3_free_queues(dev);
 914
 915         return ret;
 916 }
 917
 918 static int
 919 vmxnet3_dev_reset(struct rte_eth_dev *dev)
 920 {
 921         int ret;
 922
 923         ret = eth_vmxnet3_dev_uninit(dev);
 924         if (ret)
 925                 return ret;
 926         ret = eth_vmxnet3_dev_init(dev);
 927         return ret;
 928 }
 929
 930 static void
 931 vmxnet3_hw_tx_stats_get(struct vmxnet3_hw *hw, unsigned int q,
 932                         struct UPT1_TxStats *res)
 933 {
 934 #define VMXNET3_UPDATE_TX_STAT(h, i, f, r)              \
 935                 ((r)->f = (h)->tqd_start[(i)].stats.f + \
 936                         (h)->saved_tx_stats[(i)].f)
 937
 938         VMXNET3_UPDATE_TX_STAT(hw, q, ucastPktsTxOK, res);
 939         VMXNET3_UPDATE_TX_STAT(hw, q, mcastPktsTxOK, res);
 940         VMXNET3_UPDATE_TX_STAT(hw, q, bcastPktsTxOK, res);
 941         VMXNET3_UPDATE_TX_STAT(hw, q, ucastBytesTxOK, res);
 942         VMXNET3_UPDATE_TX_STAT(hw, q, mcastBytesTxOK, res);
 943         VMXNET3_UPDATE_TX_STAT(hw, q, bcastBytesTxOK, res);
 944         VMXNET3_UPDATE_TX_STAT(hw, q, pktsTxError, res);
 945         VMXNET3_UPDATE_TX_STAT(hw, q, pktsTxDiscard, res);
 946
 947 #undef VMXNET3_UPDATE_TX_STAT
 948 }
 949
 950 static void
 951 vmxnet3_hw_rx_stats_get(struct vmxnet3_hw *hw, unsigned int q,
 952                         struct UPT1_RxStats *res)
 953 {
 954 #define VMXNET3_UPDATE_RX_STAT(h, i, f, r)              \
 955                 ((r)->f = (h)->rqd_start[(i)].stats.f + \
 956                         (h)->saved_rx_stats[(i)].f)
 957
 958         VMXNET3_UPDATE_RX_STAT(hw, q, ucastPktsRxOK, res);
 959         VMXNET3_UPDATE_RX_STAT(hw, q, mcastPktsRxOK, res);
 960         VMXNET3_UPDATE_RX_STAT(hw, q, bcastPktsRxOK, res);
 961         VMXNET3_UPDATE_RX_STAT(hw, q, ucastBytesRxOK, res);
 962         VMXNET3_UPDATE_RX_STAT(hw, q, mcastBytesRxOK, res);
 963         VMXNET3_UPDATE_RX_STAT(hw, q, bcastBytesRxOK, res);
 964         VMXNET3_UPDATE_RX_STAT(hw, q, pktsRxError, res);
 965         VMXNET3_UPDATE_RX_STAT(hw, q, pktsRxOutOfBuf, res);
 966
 967 #undef VMXNET3_UPDATE_RX_STAT
 968 }
 969
 970 static void
 971 vmxnet3_tx_stats_get(struct vmxnet3_hw *hw, unsigned int q,
 972                                         struct UPT1_TxStats *res)
 973 {
 974                 vmxnet3_hw_tx_stats_get(hw, q, res);
 975
 976 #define VMXNET3_REDUCE_SNAPSHOT_TX_STAT(h, i, f, r)     \
 977                 ((r)->f -= (h)->snapshot_tx_stats[(i)].f)
 978
 979         VMXNET3_REDUCE_SNAPSHOT_TX_STAT(hw, q, ucastPktsTxOK, res);
 980         VMXNET3_REDUCE_SNAPSHOT_TX_STAT(hw, q, mcastPktsTxOK, res);
 981         VMXNET3_REDUCE_SNAPSHOT_TX_STAT(hw, q, bcastPktsTxOK, res);
 982         VMXNET3_REDUCE_SNAPSHOT_TX_STAT(hw, q, ucastBytesTxOK, res);
 983         VMXNET3_REDUCE_SNAPSHOT_TX_STAT(hw, q, mcastBytesTxOK, res);
 984         VMXNET3_REDUCE_SNAPSHOT_TX_STAT(hw, q, bcastBytesTxOK, res);
 985         VMXNET3_REDUCE_SNAPSHOT_TX_STAT(hw, q, pktsTxError, res);
 986         VMXNET3_REDUCE_SNAPSHOT_TX_STAT(hw, q, pktsTxDiscard, res);
 987
 988 #undef VMXNET3_REDUCE_SNAPSHOT_TX_STAT
 989 }
 990
 991 static void
 992 vmxnet3_rx_stats_get(struct vmxnet3_hw *hw, unsigned int q,
 993                                         struct UPT1_RxStats *res)
 994 {
 995                 vmxnet3_hw_rx_stats_get(hw, q, res);
 996
 997 #define VMXNET3_REDUCE_SNAPSHOT_RX_STAT(h, i, f, r)     \
 998                 ((r)->f -= (h)->snapshot_rx_stats[(i)].f)
 999
1000         VMXNET3_REDUCE_SNAPSHOT_RX_STAT(hw, q, ucastPktsRxOK, res);
1001         VMXNET3_REDUCE_SNAPSHOT_RX_STAT(hw, q, mcastPktsRxOK, res);
1002         VMXNET3_REDUCE_SNAPSHOT_RX_STAT(hw, q, bcastPktsRxOK, res);
1003         VMXNET3_REDUCE_SNAPSHOT_RX_STAT(hw, q, ucastBytesRxOK, res);
1004         VMXNET3_REDUCE_SNAPSHOT_RX_STAT(hw, q, mcastBytesRxOK, res);
1005         VMXNET3_REDUCE_SNAPSHOT_RX_STAT(hw, q, bcastBytesRxOK, res);
1006         VMXNET3_REDUCE_SNAPSHOT_RX_STAT(hw, q, pktsRxError, res);
1007         VMXNET3_REDUCE_SNAPSHOT_RX_STAT(hw, q, pktsRxOutOfBuf, res);
1008
1009 #undef VMXNET3_REDUCE_SNAPSHOT_RX_STAT
1010 }
1011
1012 static void
1013 vmxnet3_hw_stats_save(struct vmxnet3_hw *hw)
1014 {
1015         unsigned int i;
1016
1017         VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, VMXNET3_CMD_GET_STATS);
1018
1019         RTE_BUILD_BUG_ON(RTE_ETHDEV_QUEUE_STAT_CNTRS < VMXNET3_MAX_TX_QUEUES);
1020
1021         for (i = 0; i < hw->num_tx_queues; i++)
1022                 vmxnet3_hw_tx_stats_get(hw, i, &hw->saved_tx_stats[i]);
1023         for (i = 0; i < hw->num_rx_queues; i++)
1024                 vmxnet3_hw_rx_stats_get(hw, i, &hw->saved_rx_stats[i]);
1025 }
1026
1027 static int
1028 vmxnet3_dev_xstats_get_names(struct rte_eth_dev *dev,
1029                              struct rte_eth_xstat_name *xstats_names,
1030                              unsigned int n)
1031 {
1032         unsigned int i, t, count = 0;
1033         unsigned int nstats =
1034                 dev->data->nb_tx_queues * RTE_DIM(vmxnet3_txq_stat_strings) +
1035                 dev->data->nb_rx_queues * RTE_DIM(vmxnet3_rxq_stat_strings);
1036
1037         if (!xstats_names || n < nstats)
1038                 return nstats;
1039
1040         for (i = 0; i < dev->data->nb_rx_queues; i++) {
1041                 if (!dev->data->rx_queues[i])
1042                         continue;
1043
1044                 for (t = 0; t < RTE_DIM(vmxnet3_rxq_stat_strings); t++) {
1045                         snprintf(xstats_names[count].name,
1046                                  sizeof(xstats_names[count].name),
1047                                  "rx_q%u_%s", i,
1048                                  vmxnet3_rxq_stat_strings[t].name);
1049                         count++;
1050                 }
1051         }
1052
1053         for (i = 0; i < dev->data->nb_tx_queues; i++) {
1054                 if (!dev->data->tx_queues[i])
1055                         continue;
1056
1057                 for (t = 0; t < RTE_DIM(vmxnet3_txq_stat_strings); t++) {
1058                         snprintf(xstats_names[count].name,
1059                                  sizeof(xstats_names[count].name),
1060                                  "tx_q%u_%s", i,
1061                                  vmxnet3_txq_stat_strings[t].name);
1062                         count++;
1063                 }
1064         }
1065
1066         return count;
1067 }
1068
1069 static int
1070 vmxnet3_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
1071                        unsigned int n)
1072 {
1073         unsigned int i, t, count = 0;
1074         unsigned int nstats =
1075                 dev->data->nb_tx_queues * RTE_DIM(vmxnet3_txq_stat_strings) +
1076                 dev->data->nb_rx_queues * RTE_DIM(vmxnet3_rxq_stat_strings);
1077
1078         if (n < nstats)
1079                 return nstats;
1080
1081         for (i = 0; i < dev->data->nb_rx_queues; i++) {
1082                 struct vmxnet3_rx_queue *rxq = dev->data->rx_queues[i];
1083
1084                 if (rxq == NULL)
1085                         continue;
1086
1087                 for (t = 0; t < RTE_DIM(vmxnet3_rxq_stat_strings); t++) {
1088                         xstats[count].value = *(uint64_t *)(((char *)&rxq->stats) +
1089                                 vmxnet3_rxq_stat_strings[t].offset);
1090                         xstats[count].id = count;
1091                         count++;
1092                 }
1093         }
1094
1095         for (i = 0; i < dev->data->nb_tx_queues; i++) {
1096                 struct vmxnet3_tx_queue *txq = dev->data->tx_queues[i];
1097
1098                 if (txq == NULL)
1099                         continue;
1100
1101                 for (t = 0; t < RTE_DIM(vmxnet3_txq_stat_strings); t++) {
1102                         xstats[count].value = *(uint64_t *)(((char *)&txq->stats) +
1103                                 vmxnet3_txq_stat_strings[t].offset);
1104                         xstats[count].id = count;
1105                         count++;
1106                 }
1107         }
1108
1109         return count;
1110 }
1111
1112 static int
1113 vmxnet3_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
1114 {
1115         unsigned int i;
1116         struct vmxnet3_hw *hw = dev->data->dev_private;
1117         struct UPT1_TxStats txStats;
1118         struct UPT1_RxStats rxStats;
1119
1120         VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, VMXNET3_CMD_GET_STATS);
1121
1122         RTE_BUILD_BUG_ON(RTE_ETHDEV_QUEUE_STAT_CNTRS < VMXNET3_MAX_TX_QUEUES);
1123         for (i = 0; i < hw->num_tx_queues; i++) {
1124                 vmxnet3_tx_stats_get(hw, i, &txStats);
1125
1126                 stats->q_opackets[i] = txStats.ucastPktsTxOK +
1127                         txStats.mcastPktsTxOK +
1128                         txStats.bcastPktsTxOK;
1129
1130                 stats->q_obytes[i] = txStats.ucastBytesTxOK +
1131                         txStats.mcastBytesTxOK +
1132                         txStats.bcastBytesTxOK;
1133
1134                 stats->opackets += stats->q_opackets[i];
1135                 stats->obytes += stats->q_obytes[i];
1136                 stats->oerrors += txStats.pktsTxError + txStats.pktsTxDiscard;
1137         }
1138
1139         RTE_BUILD_BUG_ON(RTE_ETHDEV_QUEUE_STAT_CNTRS < VMXNET3_MAX_RX_QUEUES);
1140         for (i = 0; i < hw->num_rx_queues; i++) {
1141                 vmxnet3_rx_stats_get(hw, i, &rxStats);
1142
1143                 stats->q_ipackets[i] = rxStats.ucastPktsRxOK +
1144                         rxStats.mcastPktsRxOK +
1145                         rxStats.bcastPktsRxOK;
1146
1147                 stats->q_ibytes[i] = rxStats.ucastBytesRxOK +
1148                         rxStats.mcastBytesRxOK +
1149                         rxStats.bcastBytesRxOK;
1150
1151                 stats->ipackets += stats->q_ipackets[i];
1152                 stats->ibytes += stats->q_ibytes[i];
1153
1154                 stats->q_errors[i] = rxStats.pktsRxError;
1155                 stats->ierrors += rxStats.pktsRxError;
1156                 stats->imissed += rxStats.pktsRxOutOfBuf;
1157         }
1158
1159         return 0;
1160 }
1161
1162 static int
1163 vmxnet3_dev_stats_reset(struct rte_eth_dev *dev)
1164 {
1165         unsigned int i;
1166         struct vmxnet3_hw *hw = dev->data->dev_private;
1167         struct UPT1_TxStats txStats = {0};
1168         struct UPT1_RxStats rxStats = {0};
1169
1170         VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, VMXNET3_CMD_GET_STATS);
1171
1172         RTE_BUILD_BUG_ON(RTE_ETHDEV_QUEUE_STAT_CNTRS < VMXNET3_MAX_TX_QUEUES);
1173
1174         for (i = 0; i < hw->num_tx_queues; i++) {
1175                 vmxnet3_hw_tx_stats_get(hw, i, &txStats);
1176                 memcpy(&hw->snapshot_tx_stats[i], &txStats,
1177                         sizeof(hw->snapshot_tx_stats[0]));
1178         }
1179         for (i = 0; i < hw->num_rx_queues; i++) {
1180                 vmxnet3_hw_rx_stats_get(hw, i, &rxStats);
1181                 memcpy(&hw->snapshot_rx_stats[i], &rxStats,
1182                         sizeof(hw->snapshot_rx_stats[0]));
1183         }
1184
1185         return 0;
1186 }
1187
1188 static int
1189 vmxnet3_dev_info_get(struct rte_eth_dev *dev,
1190                      struct rte_eth_dev_info *dev_info)
1191 {
1192         struct vmxnet3_hw *hw = dev->data->dev_private;
1193
1194         dev_info->max_rx_queues = VMXNET3_MAX_RX_QUEUES;
1195         dev_info->max_tx_queues = VMXNET3_MAX_TX_QUEUES;
1196         dev_info->min_rx_bufsize = 1518 + RTE_PKTMBUF_HEADROOM;
1197         dev_info->max_rx_pktlen = 16384; /* includes CRC, cf MAXFRS register */
1198         dev_info->min_mtu = VMXNET3_MIN_MTU;
1199         dev_info->max_mtu = VMXNET3_MAX_MTU;
1200         dev_info->speed_capa = ETH_LINK_SPEED_10G;
1201         dev_info->max_mac_addrs = VMXNET3_MAX_MAC_ADDRS;
1202
1203         dev_info->flow_type_rss_offloads = VMXNET3_RSS_OFFLOAD_ALL;
1204
1205         if (VMXNET3_VERSION_GE_4(hw)) {
1206                 dev_info->flow_type_rss_offloads |= VMXNET3_V4_RSS_MASK;
1207         }
1208
1209         dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
1210                 .nb_max = VMXNET3_RX_RING_MAX_SIZE,
1211                 .nb_min = VMXNET3_DEF_RX_RING_SIZE,
1212                 .nb_align = 1,
1213         };
1214
1215         dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
1216                 .nb_max = VMXNET3_TX_RING_MAX_SIZE,
1217                 .nb_min = VMXNET3_DEF_TX_RING_SIZE,
1218                 .nb_align = 1,
1219                 .nb_seg_max = VMXNET3_TX_MAX_SEG,
1220                 .nb_mtu_seg_max = VMXNET3_MAX_TXD_PER_PKT,
1221         };
1222
1223         dev_info->rx_offload_capa = VMXNET3_RX_OFFLOAD_CAP;
1224         dev_info->rx_queue_offload_capa = 0;
1225         dev_info->tx_offload_capa = VMXNET3_TX_OFFLOAD_CAP;
1226         dev_info->tx_queue_offload_capa = 0;
1227
1228         return 0;
1229 }
1230
1231 static const uint32_t *
1232 vmxnet3_dev_supported_ptypes_get(struct rte_eth_dev *dev)
1233 {
1234         static const uint32_t ptypes[] = {
1235                 RTE_PTYPE_L3_IPV4_EXT,
1236                 RTE_PTYPE_L3_IPV4,
1237                 RTE_PTYPE_UNKNOWN
1238         };
1239
1240         if (dev->rx_pkt_burst == vmxnet3_recv_pkts)
1241                 return ptypes;
1242         return NULL;
1243 }
1244
1245 static int
1246 vmxnet3_dev_mtu_set(struct rte_eth_dev *dev, __rte_unused uint16_t mtu)
1247 {
1248         if (dev->data->dev_started) {
1249                 PMD_DRV_LOG(ERR, "Port %d must be stopped to configure MTU",
1250                             dev->data->port_id);
1251                 return -EBUSY;
1252         }
1253
1254         return 0;
1255 }
1256
1257 static int
1258 vmxnet3_mac_addr_set(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr)
1259 {
1260         struct vmxnet3_hw *hw = dev->data->dev_private;
1261
1262         rte_ether_addr_copy(mac_addr, (struct rte_ether_addr *)(hw->perm_addr));
1263         vmxnet3_write_mac(hw, mac_addr->addr_bytes);
1264         return 0;
1265 }
1266
1267 /* return 0 means link status changed, -1 means not changed */
1268 static int
1269 __vmxnet3_dev_link_update(struct rte_eth_dev *dev,
1270                           __rte_unused int wait_to_complete)
1271 {
1272         struct vmxnet3_hw *hw = dev->data->dev_private;
1273         struct rte_eth_link link;
1274         uint32_t ret;
1275
1276         memset(&link, 0, sizeof(link));
1277
1278         VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, VMXNET3_CMD_GET_LINK);
1279         ret = VMXNET3_READ_BAR1_REG(hw, VMXNET3_REG_CMD);
1280
1281         if (ret & 0x1)
1282                 link.link_status = ETH_LINK_UP;
1283         link.link_duplex = ETH_LINK_FULL_DUPLEX;
1284         link.link_speed = ETH_SPEED_NUM_10G;
1285         link.link_autoneg = ETH_LINK_FIXED;
1286
1287         return rte_eth_linkstatus_set(dev, &link);
1288 }
1289
1290 static int
1291 vmxnet3_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
1292 {
1293         /* Link status doesn't change for stopped dev */
1294         if (dev->data->dev_started == 0)
1295                 return -1;
1296
1297         return __vmxnet3_dev_link_update(dev, wait_to_complete);
1298 }
1299
1300 /* Updating rxmode through Vmxnet3_DriverShared structure in adapter */
1301 static void
1302 vmxnet3_dev_set_rxmode(struct vmxnet3_hw *hw, uint32_t feature, int set)
1303 {
1304         struct Vmxnet3_RxFilterConf *rxConf = &hw->shared->devRead.rxFilterConf;
1305
1306         if (set)
1307                 rxConf->rxMode = rxConf->rxMode | feature;
1308         else
1309                 rxConf->rxMode = rxConf->rxMode & (~feature);
1310
1311         VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, VMXNET3_CMD_UPDATE_RX_MODE);
1312 }
1313
1314 /* Promiscuous supported only if Vmxnet3_DriverShared is initialized in adapter */
1315 static int
1316 vmxnet3_dev_promiscuous_enable(struct rte_eth_dev *dev)
1317 {
1318         struct vmxnet3_hw *hw = dev->data->dev_private;
1319         uint32_t *vf_table = hw->shared->devRead.rxFilterConf.vfTable;
1320
1321         memset(vf_table, 0, VMXNET3_VFT_TABLE_SIZE);
1322         vmxnet3_dev_set_rxmode(hw, VMXNET3_RXM_PROMISC, 1);
1323
1324         VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD,
1325                                VMXNET3_CMD_UPDATE_VLAN_FILTERS);
1326
1327         return 0;
1328 }
1329
1330 /* Promiscuous supported only if Vmxnet3_DriverShared is initialized in adapter */
1331 static int
1332 vmxnet3_dev_promiscuous_disable(struct rte_eth_dev *dev)
1333 {
1334         struct vmxnet3_hw *hw = dev->data->dev_private;
1335         uint32_t *vf_table = hw->shared->devRead.rxFilterConf.vfTable;
1336         uint64_t rx_offloads = dev->data->dev_conf.rxmode.offloads;
1337
1338         if (rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
1339                 memcpy(vf_table, hw->shadow_vfta, VMXNET3_VFT_TABLE_SIZE);
1340         else
1341                 memset(vf_table, 0xff, VMXNET3_VFT_TABLE_SIZE);
1342         vmxnet3_dev_set_rxmode(hw, VMXNET3_RXM_PROMISC, 0);
1343         VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD,
1344                                VMXNET3_CMD_UPDATE_VLAN_FILTERS);
1345
1346         return 0;
1347 }
1348
1349 /* Allmulticast supported only if Vmxnet3_DriverShared is initialized in adapter */
1350 static int
1351 vmxnet3_dev_allmulticast_enable(struct rte_eth_dev *dev)
1352 {
1353         struct vmxnet3_hw *hw = dev->data->dev_private;
1354
1355         vmxnet3_dev_set_rxmode(hw, VMXNET3_RXM_ALL_MULTI, 1);
1356
1357         return 0;
1358 }
1359
1360 /* Allmulticast supported only if Vmxnet3_DriverShared is initialized in adapter */
1361 static int
1362 vmxnet3_dev_allmulticast_disable(struct rte_eth_dev *dev)
1363 {
1364         struct vmxnet3_hw *hw = dev->data->dev_private;
1365
1366         vmxnet3_dev_set_rxmode(hw, VMXNET3_RXM_ALL_MULTI, 0);
1367
1368         return 0;
1369 }
1370
1371 /* Enable/disable filter on vlan */
1372 static int
1373 vmxnet3_dev_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vid, int on)
1374 {
1375         struct vmxnet3_hw *hw = dev->data->dev_private;
1376         struct Vmxnet3_RxFilterConf *rxConf = &hw->shared->devRead.rxFilterConf;
1377         uint32_t *vf_table = rxConf->vfTable;
1378
1379         /* save state for restore */
1380         if (on)
1381                 VMXNET3_SET_VFTABLE_ENTRY(hw->shadow_vfta, vid);
1382         else
1383                 VMXNET3_CLEAR_VFTABLE_ENTRY(hw->shadow_vfta, vid);
1384
1385         /* don't change active filter if in promiscuous mode */
1386         if (rxConf->rxMode & VMXNET3_RXM_PROMISC)
1387                 return 0;
1388
1389         /* set in hardware */
1390         if (on)
1391                 VMXNET3_SET_VFTABLE_ENTRY(vf_table, vid);
1392         else
1393                 VMXNET3_CLEAR_VFTABLE_ENTRY(vf_table, vid);
1394
1395         VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD,
1396                                VMXNET3_CMD_UPDATE_VLAN_FILTERS);
1397         return 0;
1398 }
1399
1400 static int
1401 vmxnet3_dev_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1402 {
1403         struct vmxnet3_hw *hw = dev->data->dev_private;
1404         Vmxnet3_DSDevRead *devRead = &hw->shared->devRead;
1405         uint32_t *vf_table = devRead->rxFilterConf.vfTable;
1406         uint64_t rx_offloads = dev->data->dev_conf.rxmode.offloads;
1407
1408         if (mask & ETH_VLAN_STRIP_MASK) {
1409                 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
1410                         devRead->misc.uptFeatures |= UPT1_F_RXVLAN;
1411                 else
1412                         devRead->misc.uptFeatures &= ~UPT1_F_RXVLAN;
1413
1414                 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD,
1415                                        VMXNET3_CMD_UPDATE_FEATURE);
1416         }
1417
1418         if (mask & ETH_VLAN_FILTER_MASK) {
1419                 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
1420                         memcpy(vf_table, hw->shadow_vfta, VMXNET3_VFT_TABLE_SIZE);
1421                 else
1422                         memset(vf_table, 0xff, VMXNET3_VFT_TABLE_SIZE);
1423
1424                 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD,
1425                                        VMXNET3_CMD_UPDATE_VLAN_FILTERS);
1426         }
1427
1428         return 0;
1429 }
1430
1431 static void
1432 vmxnet3_process_events(struct rte_eth_dev *dev)
1433 {
1434         struct vmxnet3_hw *hw = dev->data->dev_private;
1435         uint32_t events = hw->shared->ecr;
1436
1437         if (!events)
1438                 return;
1439
1440         /*
1441          * ECR bits when written with 1b are cleared. Hence write
1442          * events back to ECR so that the bits which were set will be reset.
1443          */
1444         VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_ECR, events);
1445
1446         /* Check if link state has changed */
1447         if (events & VMXNET3_ECR_LINK) {
1448                 PMD_DRV_LOG(DEBUG, "Process events: VMXNET3_ECR_LINK event");
1449                 if (vmxnet3_dev_link_update(dev, 0) == 0)
1450                         rte_eth_dev_callback_process(dev,
1451                                                      RTE_ETH_EVENT_INTR_LSC,
1452                                                      NULL);
1453         }
1454
1455         /* Check if there is an error on xmit/recv queues */
1456         if (events & (VMXNET3_ECR_TQERR | VMXNET3_ECR_RQERR)) {
1457                 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD,
1458                                        VMXNET3_CMD_GET_QUEUE_STATUS);
1459
1460                 if (hw->tqd_start->status.stopped)
1461                         PMD_DRV_LOG(ERR, "tq error 0x%x",
1462                                     hw->tqd_start->status.error);
1463
1464                 if (hw->rqd_start->status.stopped)
1465                         PMD_DRV_LOG(ERR, "rq error 0x%x",
1466                                      hw->rqd_start->status.error);
1467
1468                 /* Reset the device */
1469                 /* Have to reset the device */
1470         }
1471
1472         if (events & VMXNET3_ECR_DIC)
1473                 PMD_DRV_LOG(DEBUG, "Device implementation change event.");
1474
1475         if (events & VMXNET3_ECR_DEBUG)
1476                 PMD_DRV_LOG(DEBUG, "Debug event generated by device.");
1477 }
1478
1479 static void
1480 vmxnet3_interrupt_handler(void *param)
1481 {
1482         struct rte_eth_dev *dev = param;
1483         struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev->device);
1484
1485         vmxnet3_process_events(dev);
1486
1487         if (rte_intr_ack(&pci_dev->intr_handle) < 0)
1488                 PMD_DRV_LOG(ERR, "interrupt enable failed");
1489 }
1490
1491 RTE_PMD_REGISTER_PCI(net_vmxnet3, rte_vmxnet3_pmd);
1492 RTE_PMD_REGISTER_PCI_TABLE(net_vmxnet3, pci_id_vmxnet3_map);
1493 RTE_PMD_REGISTER_KMOD_DEP(net_vmxnet3, "* igb_uio | uio_pci_generic | vfio-pci");
1494 RTE_LOG_REGISTER(vmxnet3_logtype_init, pmd.net.vmxnet3.init, NOTICE);
1495 RTE_LOG_REGISTER(vmxnet3_logtype_driver, pmd.net.vmxnet3.driver, NOTICE);