1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2010-2015 Intel Corporation
14 #include <rte_byteorder.h>
15 #include <rte_common.h>
16 #include <rte_cycles.h>
18 #include <rte_interrupts.h>
20 #include <rte_debug.h>
22 #include <rte_bus_pci.h>
23 #include <rte_branch_prediction.h>
24 #include <rte_memory.h>
25 #include <rte_memzone.h>
27 #include <rte_alarm.h>
28 #include <rte_ether.h>
29 #include <ethdev_driver.h>
30 #include <ethdev_pci.h>
31 #include <rte_string_fns.h>
32 #include <rte_malloc.h>
35 #include "base/vmxnet3_defs.h"
37 #include "vmxnet3_ring.h"
38 #include "vmxnet3_logs.h"
39 #include "vmxnet3_ethdev.h"
41 #define VMXNET3_TX_MAX_SEG UINT8_MAX
43 #define VMXNET3_TX_OFFLOAD_CAP \
44 (RTE_ETH_TX_OFFLOAD_VLAN_INSERT | \
45 RTE_ETH_TX_OFFLOAD_TCP_CKSUM | \
46 RTE_ETH_TX_OFFLOAD_UDP_CKSUM | \
47 RTE_ETH_TX_OFFLOAD_TCP_TSO | \
48 RTE_ETH_TX_OFFLOAD_MULTI_SEGS)
50 #define VMXNET3_RX_OFFLOAD_CAP \
51 (RTE_ETH_RX_OFFLOAD_VLAN_STRIP | \
52 RTE_ETH_RX_OFFLOAD_VLAN_FILTER | \
53 RTE_ETH_RX_OFFLOAD_SCATTER | \
54 RTE_ETH_RX_OFFLOAD_UDP_CKSUM | \
55 RTE_ETH_RX_OFFLOAD_TCP_CKSUM | \
56 RTE_ETH_RX_OFFLOAD_TCP_LRO | \
57 RTE_ETH_RX_OFFLOAD_RSS_HASH)
59 int vmxnet3_segs_dynfield_offset = -1;
61 static int eth_vmxnet3_dev_init(struct rte_eth_dev *eth_dev);
62 static int eth_vmxnet3_dev_uninit(struct rte_eth_dev *eth_dev);
63 static int vmxnet3_dev_configure(struct rte_eth_dev *dev);
64 static int vmxnet3_dev_start(struct rte_eth_dev *dev);
65 static int vmxnet3_dev_stop(struct rte_eth_dev *dev);
66 static int vmxnet3_dev_close(struct rte_eth_dev *dev);
67 static int vmxnet3_dev_reset(struct rte_eth_dev *dev);
68 static void vmxnet3_dev_set_rxmode(struct vmxnet3_hw *hw, uint32_t feature, int set);
69 static int vmxnet3_dev_promiscuous_enable(struct rte_eth_dev *dev);
70 static int vmxnet3_dev_promiscuous_disable(struct rte_eth_dev *dev);
71 static int vmxnet3_dev_allmulticast_enable(struct rte_eth_dev *dev);
72 static int vmxnet3_dev_allmulticast_disable(struct rte_eth_dev *dev);
73 static int __vmxnet3_dev_link_update(struct rte_eth_dev *dev,
74 int wait_to_complete);
75 static int vmxnet3_dev_link_update(struct rte_eth_dev *dev,
76 int wait_to_complete);
77 static void vmxnet3_hw_stats_save(struct vmxnet3_hw *hw);
78 static int vmxnet3_dev_stats_get(struct rte_eth_dev *dev,
79 struct rte_eth_stats *stats);
80 static int vmxnet3_dev_stats_reset(struct rte_eth_dev *dev);
81 static int vmxnet3_dev_xstats_get_names(struct rte_eth_dev *dev,
82 struct rte_eth_xstat_name *xstats,
84 static int vmxnet3_dev_xstats_get(struct rte_eth_dev *dev,
85 struct rte_eth_xstat *xstats, unsigned int n);
86 static int vmxnet3_dev_info_get(struct rte_eth_dev *dev,
87 struct rte_eth_dev_info *dev_info);
88 static const uint32_t *
89 vmxnet3_dev_supported_ptypes_get(struct rte_eth_dev *dev);
90 static int vmxnet3_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
91 static int vmxnet3_dev_vlan_filter_set(struct rte_eth_dev *dev,
92 uint16_t vid, int on);
93 static int vmxnet3_dev_vlan_offload_set(struct rte_eth_dev *dev, int mask);
94 static int vmxnet3_mac_addr_set(struct rte_eth_dev *dev,
95 struct rte_ether_addr *mac_addr);
96 static void vmxnet3_process_events(struct rte_eth_dev *dev);
97 static void vmxnet3_interrupt_handler(void *param);
98 static int vmxnet3_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
100 static int vmxnet3_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
104 * The set of PCI devices this driver supports
106 #define VMWARE_PCI_VENDOR_ID 0x15AD
107 #define VMWARE_DEV_ID_VMXNET3 0x07B0
108 static const struct rte_pci_id pci_id_vmxnet3_map[] = {
109 { RTE_PCI_DEVICE(VMWARE_PCI_VENDOR_ID, VMWARE_DEV_ID_VMXNET3) },
110 { .vendor_id = 0, /* sentinel */ },
113 static const struct eth_dev_ops vmxnet3_eth_dev_ops = {
114 .dev_configure = vmxnet3_dev_configure,
115 .dev_start = vmxnet3_dev_start,
116 .dev_stop = vmxnet3_dev_stop,
117 .dev_close = vmxnet3_dev_close,
118 .dev_reset = vmxnet3_dev_reset,
119 .promiscuous_enable = vmxnet3_dev_promiscuous_enable,
120 .promiscuous_disable = vmxnet3_dev_promiscuous_disable,
121 .allmulticast_enable = vmxnet3_dev_allmulticast_enable,
122 .allmulticast_disable = vmxnet3_dev_allmulticast_disable,
123 .link_update = vmxnet3_dev_link_update,
124 .stats_get = vmxnet3_dev_stats_get,
125 .xstats_get_names = vmxnet3_dev_xstats_get_names,
126 .xstats_get = vmxnet3_dev_xstats_get,
127 .stats_reset = vmxnet3_dev_stats_reset,
128 .mac_addr_set = vmxnet3_mac_addr_set,
129 .dev_infos_get = vmxnet3_dev_info_get,
130 .dev_supported_ptypes_get = vmxnet3_dev_supported_ptypes_get,
131 .mtu_set = vmxnet3_dev_mtu_set,
132 .vlan_filter_set = vmxnet3_dev_vlan_filter_set,
133 .vlan_offload_set = vmxnet3_dev_vlan_offload_set,
134 .rx_queue_setup = vmxnet3_dev_rx_queue_setup,
135 .rx_queue_release = vmxnet3_dev_rx_queue_release,
136 .tx_queue_setup = vmxnet3_dev_tx_queue_setup,
137 .tx_queue_release = vmxnet3_dev_tx_queue_release,
138 .rx_queue_intr_enable = vmxnet3_dev_rx_queue_intr_enable,
139 .rx_queue_intr_disable = vmxnet3_dev_rx_queue_intr_disable,
142 struct vmxnet3_xstats_name_off {
143 char name[RTE_ETH_XSTATS_NAME_SIZE];
147 /* tx_qX_ is prepended to the name string here */
148 static const struct vmxnet3_xstats_name_off vmxnet3_txq_stat_strings[] = {
149 {"drop_total", offsetof(struct vmxnet3_txq_stats, drop_total)},
150 {"drop_too_many_segs", offsetof(struct vmxnet3_txq_stats, drop_too_many_segs)},
151 {"drop_tso", offsetof(struct vmxnet3_txq_stats, drop_tso)},
152 {"tx_ring_full", offsetof(struct vmxnet3_txq_stats, tx_ring_full)},
155 /* rx_qX_ is prepended to the name string here */
156 static const struct vmxnet3_xstats_name_off vmxnet3_rxq_stat_strings[] = {
157 {"drop_total", offsetof(struct vmxnet3_rxq_stats, drop_total)},
158 {"drop_err", offsetof(struct vmxnet3_rxq_stats, drop_err)},
159 {"drop_fcs", offsetof(struct vmxnet3_rxq_stats, drop_fcs)},
160 {"rx_buf_alloc_failure", offsetof(struct vmxnet3_rxq_stats, rx_buf_alloc_failure)},
163 static const struct rte_memzone *
164 gpa_zone_reserve(struct rte_eth_dev *dev, uint32_t size,
165 const char *post_string, int socket_id,
166 uint16_t align, bool reuse)
168 char z_name[RTE_MEMZONE_NAMESIZE];
169 const struct rte_memzone *mz;
171 snprintf(z_name, sizeof(z_name), "eth_p%d_%s",
172 dev->data->port_id, post_string);
174 mz = rte_memzone_lookup(z_name);
177 rte_memzone_free(mz);
178 return rte_memzone_reserve_aligned(z_name, size, socket_id,
179 RTE_MEMZONE_IOVA_CONTIG, align);
185 return rte_memzone_reserve_aligned(z_name, size, socket_id,
186 RTE_MEMZONE_IOVA_CONTIG, align);
190 * Enable the given interrupt
193 vmxnet3_enable_intr(struct vmxnet3_hw *hw, unsigned int intr_idx)
195 PMD_INIT_FUNC_TRACE();
196 VMXNET3_WRITE_BAR0_REG(hw, VMXNET3_REG_IMR + intr_idx * 8, 0);
200 * Disable the given interrupt
203 vmxnet3_disable_intr(struct vmxnet3_hw *hw, unsigned int intr_idx)
205 PMD_INIT_FUNC_TRACE();
206 VMXNET3_WRITE_BAR0_REG(hw, VMXNET3_REG_IMR + intr_idx * 8, 1);
210 * Enable all intrs used by the device
213 vmxnet3_enable_all_intrs(struct vmxnet3_hw *hw)
215 Vmxnet3_DSDevRead *devRead = &hw->shared->devRead;
217 PMD_INIT_FUNC_TRACE();
219 devRead->intrConf.intrCtrl &= rte_cpu_to_le_32(~VMXNET3_IC_DISABLE_ALL);
221 if (hw->intr.lsc_only) {
222 vmxnet3_enable_intr(hw, devRead->intrConf.eventIntrIdx);
226 for (i = 0; i < hw->intr.num_intrs; i++)
227 vmxnet3_enable_intr(hw, i);
232 * Disable all intrs used by the device
235 vmxnet3_disable_all_intrs(struct vmxnet3_hw *hw)
239 PMD_INIT_FUNC_TRACE();
241 hw->shared->devRead.intrConf.intrCtrl |=
242 rte_cpu_to_le_32(VMXNET3_IC_DISABLE_ALL);
243 for (i = 0; i < hw->num_intrs; i++)
244 vmxnet3_disable_intr(hw, i);
248 * Gets tx data ring descriptor size.
251 eth_vmxnet3_txdata_get(struct vmxnet3_hw *hw)
253 uint16 txdata_desc_size;
255 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD,
256 VMXNET3_CMD_GET_TXDATA_DESC_SIZE);
257 txdata_desc_size = VMXNET3_READ_BAR1_REG(hw, VMXNET3_REG_CMD);
259 return (txdata_desc_size < VMXNET3_TXDATA_DESC_MIN_SIZE ||
260 txdata_desc_size > VMXNET3_TXDATA_DESC_MAX_SIZE ||
261 txdata_desc_size & VMXNET3_TXDATA_DESC_SIZE_MASK) ?
262 sizeof(struct Vmxnet3_TxDataDesc) : txdata_desc_size;
266 * It returns 0 on success.
269 eth_vmxnet3_dev_init(struct rte_eth_dev *eth_dev)
271 struct rte_pci_device *pci_dev;
272 struct vmxnet3_hw *hw = eth_dev->data->dev_private;
273 uint32_t mac_hi, mac_lo, ver;
274 struct rte_eth_link link;
275 static const struct rte_mbuf_dynfield vmxnet3_segs_dynfield_desc = {
276 .name = VMXNET3_SEGS_DYNFIELD_NAME,
277 .size = sizeof(vmxnet3_segs_dynfield_t),
278 .align = __alignof__(vmxnet3_segs_dynfield_t),
281 PMD_INIT_FUNC_TRACE();
283 eth_dev->dev_ops = &vmxnet3_eth_dev_ops;
284 eth_dev->rx_pkt_burst = &vmxnet3_recv_pkts;
285 eth_dev->tx_pkt_burst = &vmxnet3_xmit_pkts;
286 eth_dev->tx_pkt_prepare = vmxnet3_prep_pkts;
287 pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
289 /* extra mbuf field is required to guess MSS */
290 vmxnet3_segs_dynfield_offset =
291 rte_mbuf_dynfield_register(&vmxnet3_segs_dynfield_desc);
292 if (vmxnet3_segs_dynfield_offset < 0) {
293 PMD_INIT_LOG(ERR, "Cannot register mbuf field.");
298 * for secondary processes, we don't initialize any further as primary
299 * has already done this work.
301 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
304 rte_eth_copy_pci_info(eth_dev, pci_dev);
305 eth_dev->data->dev_flags |= RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS;
307 /* Vendor and Device ID need to be set before init of shared code */
308 hw->device_id = pci_dev->id.device_id;
309 hw->vendor_id = pci_dev->id.vendor_id;
310 hw->hw_addr0 = (void *)pci_dev->mem_resource[0].addr;
311 hw->hw_addr1 = (void *)pci_dev->mem_resource[1].addr;
313 hw->num_rx_queues = 1;
314 hw->num_tx_queues = 1;
315 hw->bufs_per_pkt = 1;
317 /* Check h/w version compatibility with driver. */
318 ver = VMXNET3_READ_BAR1_REG(hw, VMXNET3_REG_VRRS);
319 PMD_INIT_LOG(DEBUG, "Hardware version : %d", ver);
321 if (ver & (1 << VMXNET3_REV_4)) {
322 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_VRRS,
324 hw->version = VMXNET3_REV_4 + 1;
325 } else if (ver & (1 << VMXNET3_REV_3)) {
326 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_VRRS,
328 hw->version = VMXNET3_REV_3 + 1;
329 } else if (ver & (1 << VMXNET3_REV_2)) {
330 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_VRRS,
332 hw->version = VMXNET3_REV_2 + 1;
333 } else if (ver & (1 << VMXNET3_REV_1)) {
334 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_VRRS,
336 hw->version = VMXNET3_REV_1 + 1;
338 PMD_INIT_LOG(ERR, "Incompatible hardware version: %d", ver);
342 PMD_INIT_LOG(INFO, "Using device v%d", hw->version);
344 /* Check UPT version compatibility with driver. */
345 ver = VMXNET3_READ_BAR1_REG(hw, VMXNET3_REG_UVRS);
346 PMD_INIT_LOG(DEBUG, "UPT hardware version : %d", ver);
348 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_UVRS, 1);
350 PMD_INIT_LOG(ERR, "Incompatible UPT version.");
354 /* Getting MAC Address */
355 mac_lo = VMXNET3_READ_BAR1_REG(hw, VMXNET3_REG_MACL);
356 mac_hi = VMXNET3_READ_BAR1_REG(hw, VMXNET3_REG_MACH);
357 memcpy(hw->perm_addr, &mac_lo, 4);
358 memcpy(hw->perm_addr + 4, &mac_hi, 2);
360 /* Allocate memory for storing MAC addresses */
361 eth_dev->data->mac_addrs = rte_zmalloc("vmxnet3", RTE_ETHER_ADDR_LEN *
362 VMXNET3_MAX_MAC_ADDRS, 0);
363 if (eth_dev->data->mac_addrs == NULL) {
365 "Failed to allocate %d bytes needed to store MAC addresses",
366 RTE_ETHER_ADDR_LEN * VMXNET3_MAX_MAC_ADDRS);
369 /* Copy the permanent MAC address */
370 rte_ether_addr_copy((struct rte_ether_addr *)hw->perm_addr,
371 ð_dev->data->mac_addrs[0]);
373 PMD_INIT_LOG(DEBUG, "MAC Address : " RTE_ETHER_ADDR_PRT_FMT,
374 hw->perm_addr[0], hw->perm_addr[1], hw->perm_addr[2],
375 hw->perm_addr[3], hw->perm_addr[4], hw->perm_addr[5]);
377 /* Put device in Quiesce Mode */
378 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, VMXNET3_CMD_QUIESCE_DEV);
380 /* allow untagged pkts */
381 VMXNET3_SET_VFTABLE_ENTRY(hw->shadow_vfta, 0);
383 hw->txdata_desc_size = VMXNET3_VERSION_GE_3(hw) ?
384 eth_vmxnet3_txdata_get(hw) : sizeof(struct Vmxnet3_TxDataDesc);
386 hw->rxdata_desc_size = VMXNET3_VERSION_GE_3(hw) ?
387 VMXNET3_DEF_RXDATA_DESC_SIZE : 0;
388 RTE_ASSERT((hw->rxdata_desc_size & ~VMXNET3_RXDATA_DESC_SIZE_MASK) ==
389 hw->rxdata_desc_size);
391 /* clear shadow stats */
392 memset(hw->saved_tx_stats, 0, sizeof(hw->saved_tx_stats));
393 memset(hw->saved_rx_stats, 0, sizeof(hw->saved_rx_stats));
395 /* clear snapshot stats */
396 memset(hw->snapshot_tx_stats, 0, sizeof(hw->snapshot_tx_stats));
397 memset(hw->snapshot_rx_stats, 0, sizeof(hw->snapshot_rx_stats));
399 /* set the initial link status */
400 memset(&link, 0, sizeof(link));
401 link.link_duplex = RTE_ETH_LINK_FULL_DUPLEX;
402 link.link_speed = RTE_ETH_SPEED_NUM_10G;
403 link.link_autoneg = RTE_ETH_LINK_FIXED;
404 rte_eth_linkstatus_set(eth_dev, &link);
410 eth_vmxnet3_dev_uninit(struct rte_eth_dev *eth_dev)
412 struct vmxnet3_hw *hw = eth_dev->data->dev_private;
414 PMD_INIT_FUNC_TRACE();
416 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
419 if (hw->adapter_stopped == 0) {
420 PMD_INIT_LOG(DEBUG, "Device has not been closed.");
427 static int eth_vmxnet3_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
428 struct rte_pci_device *pci_dev)
430 return rte_eth_dev_pci_generic_probe(pci_dev,
431 sizeof(struct vmxnet3_hw), eth_vmxnet3_dev_init);
434 static int eth_vmxnet3_pci_remove(struct rte_pci_device *pci_dev)
436 return rte_eth_dev_pci_generic_remove(pci_dev, eth_vmxnet3_dev_uninit);
439 static struct rte_pci_driver rte_vmxnet3_pmd = {
440 .id_table = pci_id_vmxnet3_map,
441 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
442 .probe = eth_vmxnet3_pci_probe,
443 .remove = eth_vmxnet3_pci_remove,
447 vmxnet3_alloc_intr_resources(struct rte_eth_dev *dev)
449 struct vmxnet3_hw *hw = dev->data->dev_private;
451 int nvec = 1; /* for link event */
454 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD,
455 VMXNET3_CMD_GET_CONF_INTR);
456 cfg = VMXNET3_READ_BAR1_REG(hw, VMXNET3_REG_CMD);
457 hw->intr.type = cfg & 0x3;
458 hw->intr.mask_mode = (cfg >> 2) & 0x3;
460 if (hw->intr.type == VMXNET3_IT_AUTO)
461 hw->intr.type = VMXNET3_IT_MSIX;
463 if (hw->intr.type == VMXNET3_IT_MSIX) {
464 /* only support shared tx/rx intr */
465 if (hw->num_tx_queues != hw->num_rx_queues)
468 nvec += hw->num_rx_queues;
469 hw->intr.num_intrs = nvec;
474 /* the tx/rx queue interrupt will be disabled */
475 hw->intr.num_intrs = 2;
476 hw->intr.lsc_only = TRUE;
477 PMD_INIT_LOG(INFO, "Enabled MSI-X with %d vectors", hw->intr.num_intrs);
481 vmxnet3_dev_configure(struct rte_eth_dev *dev)
483 const struct rte_memzone *mz;
484 struct vmxnet3_hw *hw = dev->data->dev_private;
487 PMD_INIT_FUNC_TRACE();
489 if (dev->data->dev_conf.rxmode.mq_mode & RTE_ETH_MQ_RX_RSS_FLAG)
490 dev->data->dev_conf.rxmode.offloads |= RTE_ETH_RX_OFFLOAD_RSS_HASH;
492 if (dev->data->nb_tx_queues > VMXNET3_MAX_TX_QUEUES ||
493 dev->data->nb_rx_queues > VMXNET3_MAX_RX_QUEUES) {
494 PMD_INIT_LOG(ERR, "ERROR: Number of queues not supported");
498 if (!rte_is_power_of_2(dev->data->nb_rx_queues)) {
499 PMD_INIT_LOG(ERR, "ERROR: Number of rx queues not power of 2");
503 size = dev->data->nb_rx_queues * sizeof(struct Vmxnet3_TxQueueDesc) +
504 dev->data->nb_tx_queues * sizeof(struct Vmxnet3_RxQueueDesc);
506 if (size > UINT16_MAX)
509 hw->num_rx_queues = (uint8_t)dev->data->nb_rx_queues;
510 hw->num_tx_queues = (uint8_t)dev->data->nb_tx_queues;
513 * Allocate a memzone for Vmxnet3_DriverShared - Vmxnet3_DSDevRead
516 mz = gpa_zone_reserve(dev, sizeof(struct Vmxnet3_DriverShared),
517 "shared", rte_socket_id(), 8, 1);
520 PMD_INIT_LOG(ERR, "ERROR: Creating shared zone");
523 memset(mz->addr, 0, mz->len);
525 hw->shared = mz->addr;
526 hw->sharedPA = mz->iova;
529 * Allocate a memzone for Vmxnet3_RxQueueDesc - Vmxnet3_TxQueueDesc
532 * We cannot reuse this memzone from previous allocation as its size
533 * depends on the number of tx and rx queues, which could be different
534 * from one config to another.
536 mz = gpa_zone_reserve(dev, size, "queuedesc", rte_socket_id(),
537 VMXNET3_QUEUE_DESC_ALIGN, 0);
539 PMD_INIT_LOG(ERR, "ERROR: Creating queue descriptors zone");
542 memset(mz->addr, 0, mz->len);
544 hw->tqd_start = (Vmxnet3_TxQueueDesc *)mz->addr;
545 hw->rqd_start = (Vmxnet3_RxQueueDesc *)(hw->tqd_start + hw->num_tx_queues);
547 hw->queueDescPA = mz->iova;
548 hw->queue_desc_len = (uint16_t)size;
550 if (dev->data->dev_conf.rxmode.mq_mode == RTE_ETH_MQ_RX_RSS) {
551 /* Allocate memory structure for UPT1_RSSConf and configure */
552 mz = gpa_zone_reserve(dev, sizeof(struct VMXNET3_RSSConf),
553 "rss_conf", rte_socket_id(),
554 RTE_CACHE_LINE_SIZE, 1);
557 "ERROR: Creating rss_conf structure zone");
560 memset(mz->addr, 0, mz->len);
562 hw->rss_conf = mz->addr;
563 hw->rss_confPA = mz->iova;
566 vmxnet3_alloc_intr_resources(dev);
572 vmxnet3_write_mac(struct vmxnet3_hw *hw, const uint8_t *addr)
577 "Writing MAC Address : " RTE_ETHER_ADDR_PRT_FMT,
578 addr[0], addr[1], addr[2],
579 addr[3], addr[4], addr[5]);
581 memcpy(&val, addr, 4);
582 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_MACL, val);
584 memcpy(&val, addr + 4, 2);
585 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_MACH, val);
589 * Configure the hardware to generate MSI-X interrupts.
590 * If setting up MSIx fails, try setting up MSI (only 1 interrupt vector
591 * which will be disabled to allow lsc to work).
593 * Returns 0 on success and -1 otherwise.
596 vmxnet3_configure_msix(struct rte_eth_dev *dev)
598 struct vmxnet3_hw *hw = dev->data->dev_private;
599 struct rte_intr_handle *intr_handle = dev->intr_handle;
600 uint16_t intr_vector;
603 hw->intr.event_intr_idx = 0;
605 /* only vfio-pci driver can support interrupt mode. */
606 if (!rte_intr_cap_multiple(intr_handle) ||
607 dev->data->dev_conf.intr_conf.rxq == 0)
610 intr_vector = dev->data->nb_rx_queues;
611 if (intr_vector > VMXNET3_MAX_RX_QUEUES) {
612 PMD_INIT_LOG(ERR, "At most %d intr queues supported",
613 VMXNET3_MAX_RX_QUEUES);
617 if (rte_intr_efd_enable(intr_handle, intr_vector)) {
618 PMD_INIT_LOG(ERR, "Failed to enable fastpath event fd");
622 if (rte_intr_dp_is_en(intr_handle)) {
623 if (rte_intr_vec_list_alloc(intr_handle, "intr_vec",
624 dev->data->nb_rx_queues)) {
625 PMD_INIT_LOG(ERR, "Failed to allocate %d Rx queues intr_vec",
626 dev->data->nb_rx_queues);
627 rte_intr_efd_disable(intr_handle);
632 if (!rte_intr_allow_others(intr_handle) &&
633 dev->data->dev_conf.intr_conf.lsc != 0) {
634 PMD_INIT_LOG(ERR, "not enough intr vector to support both Rx interrupt and LSC");
635 rte_intr_vec_list_free(intr_handle);
636 rte_intr_efd_disable(intr_handle);
640 /* if we cannot allocate one MSI-X vector per queue, don't enable
643 if (hw->intr.num_intrs !=
644 (rte_intr_nb_efd_get(intr_handle) + 1)) {
645 PMD_INIT_LOG(ERR, "Device configured with %d Rx intr vectors, expecting %d",
647 rte_intr_nb_efd_get(intr_handle) + 1);
648 rte_intr_vec_list_free(intr_handle);
649 rte_intr_efd_disable(intr_handle);
653 for (i = 0; i < dev->data->nb_rx_queues; i++)
654 if (rte_intr_vec_list_index_set(intr_handle, i, i + 1))
657 for (i = 0; i < hw->intr.num_intrs; i++)
658 hw->intr.mod_levels[i] = UPT1_IML_ADAPTIVE;
660 PMD_INIT_LOG(INFO, "intr type %u, mode %u, %u vectors allocated",
661 hw->intr.type, hw->intr.mask_mode, hw->intr.num_intrs);
667 vmxnet3_dev_setup_memreg(struct rte_eth_dev *dev)
669 struct vmxnet3_hw *hw = dev->data->dev_private;
670 Vmxnet3_DriverShared *shared = hw->shared;
671 Vmxnet3_CmdInfo *cmdInfo;
672 struct rte_mempool *mp[VMXNET3_MAX_RX_QUEUES];
673 uint8_t index[VMXNET3_MAX_RX_QUEUES + VMXNET3_MAX_TX_QUEUES];
674 uint32_t num, i, j, size;
676 if (hw->memRegsPA == 0) {
677 const struct rte_memzone *mz;
679 size = sizeof(Vmxnet3_MemRegs) +
680 (VMXNET3_MAX_RX_QUEUES + VMXNET3_MAX_TX_QUEUES) *
681 sizeof(Vmxnet3_MemoryRegion);
683 mz = gpa_zone_reserve(dev, size, "memRegs", rte_socket_id(), 8,
686 PMD_INIT_LOG(ERR, "ERROR: Creating memRegs zone");
689 memset(mz->addr, 0, mz->len);
690 hw->memRegs = mz->addr;
691 hw->memRegsPA = mz->iova;
694 num = hw->num_rx_queues;
696 for (i = 0; i < num; i++) {
697 vmxnet3_rx_queue_t *rxq = dev->data->rx_queues[i];
704 * The same mempool could be used by multiple queues. In such a case,
705 * remove duplicate mempool entries. Only one entry is kept with
706 * bitmask indicating queues that are using this mempool.
708 for (i = 1; i < num; i++) {
709 for (j = 0; j < i; j++) {
710 if (mp[i] == mp[j]) {
719 for (i = 0; i < num; i++) {
723 Vmxnet3_MemoryRegion *mr = &hw->memRegs->memRegs[j];
726 (uintptr_t)STAILQ_FIRST(&mp[i]->mem_list)->iova;
727 mr->length = STAILQ_FIRST(&mp[i]->mem_list)->len <= INT32_MAX ?
728 STAILQ_FIRST(&mp[i]->mem_list)->len : INT32_MAX;
729 mr->txQueueBits = index[i];
730 mr->rxQueueBits = index[i];
733 "index: %u startPA: %" PRIu64 " length: %u, "
735 j, mr->startPA, mr->length, mr->rxQueueBits);
738 hw->memRegs->numRegs = j;
739 PMD_INIT_LOG(INFO, "numRegs: %u", j);
741 size = sizeof(Vmxnet3_MemRegs) +
742 (j - 1) * sizeof(Vmxnet3_MemoryRegion);
744 cmdInfo = &shared->cu.cmdInfo;
745 cmdInfo->varConf.confVer = 1;
746 cmdInfo->varConf.confLen = size;
747 cmdInfo->varConf.confPA = hw->memRegsPA;
753 vmxnet3_setup_driver_shared(struct rte_eth_dev *dev)
755 struct rte_eth_conf port_conf = dev->data->dev_conf;
756 struct vmxnet3_hw *hw = dev->data->dev_private;
757 struct rte_intr_handle *intr_handle = dev->intr_handle;
758 uint32_t mtu = dev->data->mtu;
759 Vmxnet3_DriverShared *shared = hw->shared;
760 Vmxnet3_DSDevRead *devRead = &shared->devRead;
761 uint64_t rx_offloads = dev->data->dev_conf.rxmode.offloads;
767 shared->magic = VMXNET3_REV1_MAGIC;
768 devRead->misc.driverInfo.version = VMXNET3_DRIVER_VERSION_NUM;
770 /* Setting up Guest OS information */
771 devRead->misc.driverInfo.gos.gosBits = sizeof(void *) == 4 ?
772 VMXNET3_GOS_BITS_32 : VMXNET3_GOS_BITS_64;
773 devRead->misc.driverInfo.gos.gosType = VMXNET3_GOS_TYPE_LINUX;
774 devRead->misc.driverInfo.vmxnet3RevSpt = 1;
775 devRead->misc.driverInfo.uptVerSpt = 1;
777 devRead->misc.mtu = rte_le_to_cpu_32(mtu);
778 devRead->misc.queueDescPA = hw->queueDescPA;
779 devRead->misc.queueDescLen = hw->queue_desc_len;
780 devRead->misc.numTxQueues = hw->num_tx_queues;
781 devRead->misc.numRxQueues = hw->num_rx_queues;
783 for (i = 0; i < hw->num_tx_queues; i++) {
784 Vmxnet3_TxQueueDesc *tqd = &hw->tqd_start[i];
785 vmxnet3_tx_queue_t *txq = dev->data->tx_queues[i];
787 txq->shared = &hw->tqd_start[i];
789 tqd->ctrl.txNumDeferred = 0;
790 tqd->ctrl.txThreshold = 1;
791 tqd->conf.txRingBasePA = txq->cmd_ring.basePA;
792 tqd->conf.compRingBasePA = txq->comp_ring.basePA;
793 tqd->conf.dataRingBasePA = txq->data_ring.basePA;
795 tqd->conf.txRingSize = txq->cmd_ring.size;
796 tqd->conf.compRingSize = txq->comp_ring.size;
797 tqd->conf.dataRingSize = txq->data_ring.size;
798 tqd->conf.txDataRingDescSize = txq->txdata_desc_size;
800 if (hw->intr.lsc_only)
801 tqd->conf.intrIdx = 1;
804 rte_intr_vec_list_index_get(intr_handle,
806 tqd->status.stopped = TRUE;
807 tqd->status.error = 0;
808 memset(&tqd->stats, 0, sizeof(tqd->stats));
811 for (i = 0; i < hw->num_rx_queues; i++) {
812 Vmxnet3_RxQueueDesc *rqd = &hw->rqd_start[i];
813 vmxnet3_rx_queue_t *rxq = dev->data->rx_queues[i];
815 rxq->shared = &hw->rqd_start[i];
817 rqd->conf.rxRingBasePA[0] = rxq->cmd_ring[0].basePA;
818 rqd->conf.rxRingBasePA[1] = rxq->cmd_ring[1].basePA;
819 rqd->conf.compRingBasePA = rxq->comp_ring.basePA;
821 rqd->conf.rxRingSize[0] = rxq->cmd_ring[0].size;
822 rqd->conf.rxRingSize[1] = rxq->cmd_ring[1].size;
823 rqd->conf.compRingSize = rxq->comp_ring.size;
825 if (hw->intr.lsc_only)
826 rqd->conf.intrIdx = 1;
829 rte_intr_vec_list_index_get(intr_handle,
831 rqd->status.stopped = TRUE;
832 rqd->status.error = 0;
833 memset(&rqd->stats, 0, sizeof(rqd->stats));
837 devRead->intrConf.autoMask = hw->intr.mask_mode == VMXNET3_IMM_AUTO;
838 devRead->intrConf.numIntrs = hw->intr.num_intrs;
839 for (i = 0; i < hw->intr.num_intrs; i++)
840 devRead->intrConf.modLevels[i] = hw->intr.mod_levels[i];
842 devRead->intrConf.eventIntrIdx = hw->intr.event_intr_idx;
843 devRead->intrConf.intrCtrl |= rte_cpu_to_le_32(VMXNET3_IC_DISABLE_ALL);
845 /* RxMode set to 0 of VMXNET3_RXM_xxx */
846 devRead->rxFilterConf.rxMode = 0;
848 /* Setting up feature flags */
849 if (rx_offloads & RTE_ETH_RX_OFFLOAD_CHECKSUM)
850 devRead->misc.uptFeatures |= VMXNET3_F_RXCSUM;
852 if (rx_offloads & RTE_ETH_RX_OFFLOAD_TCP_LRO) {
853 devRead->misc.uptFeatures |= VMXNET3_F_LRO;
854 devRead->misc.maxNumRxSG = 0;
857 if (port_conf.rxmode.mq_mode == RTE_ETH_MQ_RX_RSS) {
858 ret = vmxnet3_rss_configure(dev);
859 if (ret != VMXNET3_SUCCESS)
862 devRead->misc.uptFeatures |= VMXNET3_F_RSS;
863 devRead->rssConfDesc.confVer = 1;
864 devRead->rssConfDesc.confLen = sizeof(struct VMXNET3_RSSConf);
865 devRead->rssConfDesc.confPA = hw->rss_confPA;
868 ret = vmxnet3_dev_vlan_offload_set(dev,
869 RTE_ETH_VLAN_STRIP_MASK | RTE_ETH_VLAN_FILTER_MASK);
873 vmxnet3_write_mac(hw, dev->data->mac_addrs->addr_bytes);
875 return VMXNET3_SUCCESS;
879 * Configure device link speed and setup link.
880 * Must be called after eth_vmxnet3_dev_init. Other wise it might fail
881 * It returns 0 on success.
884 vmxnet3_dev_start(struct rte_eth_dev *dev)
887 struct vmxnet3_hw *hw = dev->data->dev_private;
889 PMD_INIT_FUNC_TRACE();
891 /* Save stats before it is reset by CMD_ACTIVATE */
892 vmxnet3_hw_stats_save(hw);
894 /* configure MSI-X */
895 ret = vmxnet3_configure_msix(dev);
897 /* revert to lsc only */
898 hw->intr.num_intrs = 2;
899 hw->intr.lsc_only = TRUE;
902 ret = vmxnet3_setup_driver_shared(dev);
903 if (ret != VMXNET3_SUCCESS)
906 /* Exchange shared data with device */
907 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_DSAL,
908 VMXNET3_GET_ADDR_LO(hw->sharedPA));
909 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_DSAH,
910 VMXNET3_GET_ADDR_HI(hw->sharedPA));
912 /* Activate device by register write */
913 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, VMXNET3_CMD_ACTIVATE_DEV);
914 ret = VMXNET3_READ_BAR1_REG(hw, VMXNET3_REG_CMD);
917 PMD_INIT_LOG(ERR, "Device activation: UNSUCCESSFUL");
921 /* Setup memory region for rx buffers */
922 ret = vmxnet3_dev_setup_memreg(dev);
924 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD,
925 VMXNET3_CMD_REGISTER_MEMREGS);
926 ret = VMXNET3_READ_BAR1_REG(hw, VMXNET3_REG_CMD);
929 "Failed in setup memory region cmd\n");
932 PMD_INIT_LOG(DEBUG, "Failed to setup memory region\n");
935 if (VMXNET3_VERSION_GE_4(hw) &&
936 dev->data->dev_conf.rxmode.mq_mode == RTE_ETH_MQ_RX_RSS) {
937 /* Check for additional RSS */
938 ret = vmxnet3_v4_rss_configure(dev);
939 if (ret != VMXNET3_SUCCESS) {
940 PMD_INIT_LOG(ERR, "Failed to configure v4 RSS");
946 * Load RX queues with blank mbufs and update next2fill index for device
947 * Update RxMode of the device
949 ret = vmxnet3_dev_rxtx_init(dev);
950 if (ret != VMXNET3_SUCCESS) {
951 PMD_INIT_LOG(ERR, "Device queue init: UNSUCCESSFUL");
955 hw->adapter_stopped = FALSE;
957 /* Setting proper Rx Mode and issue Rx Mode Update command */
958 vmxnet3_dev_set_rxmode(hw, VMXNET3_RXM_UCAST | VMXNET3_RXM_BCAST, 1);
960 /* Setup interrupt callback */
961 rte_intr_callback_register(dev->intr_handle,
962 vmxnet3_interrupt_handler, dev);
964 if (rte_intr_enable(dev->intr_handle) < 0) {
965 PMD_INIT_LOG(ERR, "interrupt enable failed");
969 /* enable all intrs */
970 vmxnet3_enable_all_intrs(hw);
972 vmxnet3_process_events(dev);
975 * Update link state from device since this won't be
976 * done upon starting with lsc in use. This is done
977 * only after enabling interrupts to avoid any race
978 * where the link state could change without an
979 * interrupt being fired.
981 __vmxnet3_dev_link_update(dev, 0);
983 return VMXNET3_SUCCESS;
987 * Stop device: disable rx and tx functions to allow for reconfiguring.
990 vmxnet3_dev_stop(struct rte_eth_dev *dev)
992 struct rte_eth_link link;
993 struct vmxnet3_hw *hw = dev->data->dev_private;
994 struct rte_intr_handle *intr_handle = dev->intr_handle;
997 PMD_INIT_FUNC_TRACE();
999 if (hw->adapter_stopped == 1) {
1000 PMD_INIT_LOG(DEBUG, "Device already stopped.");
1005 /* Unregister has lock to make sure there is no running cb.
1006 * This has to happen first since vmxnet3_interrupt_handler
1007 * reenables interrupts by calling vmxnet3_enable_intr
1009 ret = rte_intr_callback_unregister(intr_handle,
1010 vmxnet3_interrupt_handler,
1012 } while (ret == -EAGAIN);
1015 PMD_DRV_LOG(ERR, "Error attempting to unregister intr cb: %d",
1018 PMD_INIT_LOG(DEBUG, "Disabled %d intr callbacks", ret);
1020 /* disable interrupts */
1021 vmxnet3_disable_all_intrs(hw);
1023 rte_intr_disable(intr_handle);
1025 /* Clean datapath event and queue/vector mapping */
1026 rte_intr_efd_disable(intr_handle);
1027 rte_intr_vec_list_free(intr_handle);
1029 /* quiesce the device first */
1030 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, VMXNET3_CMD_QUIESCE_DEV);
1031 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_DSAL, 0);
1032 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_DSAH, 0);
1034 /* reset the device */
1035 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, VMXNET3_CMD_RESET_DEV);
1036 PMD_INIT_LOG(DEBUG, "Device reset.");
1038 vmxnet3_dev_clear_queues(dev);
1040 /* Clear recorded link status */
1041 memset(&link, 0, sizeof(link));
1042 link.link_duplex = RTE_ETH_LINK_FULL_DUPLEX;
1043 link.link_speed = RTE_ETH_SPEED_NUM_10G;
1044 link.link_autoneg = RTE_ETH_LINK_FIXED;
1045 rte_eth_linkstatus_set(dev, &link);
1047 hw->adapter_stopped = 1;
1048 dev->data->dev_started = 0;
1054 vmxnet3_free_queues(struct rte_eth_dev *dev)
1058 PMD_INIT_FUNC_TRACE();
1060 for (i = 0; i < dev->data->nb_rx_queues; i++)
1061 vmxnet3_dev_rx_queue_release(dev, i);
1062 dev->data->nb_rx_queues = 0;
1064 for (i = 0; i < dev->data->nb_tx_queues; i++)
1065 vmxnet3_dev_tx_queue_release(dev, i);
1066 dev->data->nb_tx_queues = 0;
1070 * Reset and stop device.
1073 vmxnet3_dev_close(struct rte_eth_dev *dev)
1076 PMD_INIT_FUNC_TRACE();
1077 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1080 ret = vmxnet3_dev_stop(dev);
1081 vmxnet3_free_queues(dev);
1087 vmxnet3_dev_reset(struct rte_eth_dev *dev)
1091 ret = eth_vmxnet3_dev_uninit(dev);
1094 ret = eth_vmxnet3_dev_init(dev);
1099 vmxnet3_hw_tx_stats_get(struct vmxnet3_hw *hw, unsigned int q,
1100 struct UPT1_TxStats *res)
1102 #define VMXNET3_UPDATE_TX_STAT(h, i, f, r) \
1103 ((r)->f = (h)->tqd_start[(i)].stats.f + \
1104 (h)->saved_tx_stats[(i)].f)
1106 VMXNET3_UPDATE_TX_STAT(hw, q, ucastPktsTxOK, res);
1107 VMXNET3_UPDATE_TX_STAT(hw, q, mcastPktsTxOK, res);
1108 VMXNET3_UPDATE_TX_STAT(hw, q, bcastPktsTxOK, res);
1109 VMXNET3_UPDATE_TX_STAT(hw, q, ucastBytesTxOK, res);
1110 VMXNET3_UPDATE_TX_STAT(hw, q, mcastBytesTxOK, res);
1111 VMXNET3_UPDATE_TX_STAT(hw, q, bcastBytesTxOK, res);
1112 VMXNET3_UPDATE_TX_STAT(hw, q, pktsTxError, res);
1113 VMXNET3_UPDATE_TX_STAT(hw, q, pktsTxDiscard, res);
1115 #undef VMXNET3_UPDATE_TX_STAT
1119 vmxnet3_hw_rx_stats_get(struct vmxnet3_hw *hw, unsigned int q,
1120 struct UPT1_RxStats *res)
1122 #define VMXNET3_UPDATE_RX_STAT(h, i, f, r) \
1123 ((r)->f = (h)->rqd_start[(i)].stats.f + \
1124 (h)->saved_rx_stats[(i)].f)
1126 VMXNET3_UPDATE_RX_STAT(hw, q, ucastPktsRxOK, res);
1127 VMXNET3_UPDATE_RX_STAT(hw, q, mcastPktsRxOK, res);
1128 VMXNET3_UPDATE_RX_STAT(hw, q, bcastPktsRxOK, res);
1129 VMXNET3_UPDATE_RX_STAT(hw, q, ucastBytesRxOK, res);
1130 VMXNET3_UPDATE_RX_STAT(hw, q, mcastBytesRxOK, res);
1131 VMXNET3_UPDATE_RX_STAT(hw, q, bcastBytesRxOK, res);
1132 VMXNET3_UPDATE_RX_STAT(hw, q, pktsRxError, res);
1133 VMXNET3_UPDATE_RX_STAT(hw, q, pktsRxOutOfBuf, res);
1135 #undef VMXNET3_UPDATE_RX_STAT
1139 vmxnet3_tx_stats_get(struct vmxnet3_hw *hw, unsigned int q,
1140 struct UPT1_TxStats *res)
1142 vmxnet3_hw_tx_stats_get(hw, q, res);
1144 #define VMXNET3_REDUCE_SNAPSHOT_TX_STAT(h, i, f, r) \
1145 ((r)->f -= (h)->snapshot_tx_stats[(i)].f)
1147 VMXNET3_REDUCE_SNAPSHOT_TX_STAT(hw, q, ucastPktsTxOK, res);
1148 VMXNET3_REDUCE_SNAPSHOT_TX_STAT(hw, q, mcastPktsTxOK, res);
1149 VMXNET3_REDUCE_SNAPSHOT_TX_STAT(hw, q, bcastPktsTxOK, res);
1150 VMXNET3_REDUCE_SNAPSHOT_TX_STAT(hw, q, ucastBytesTxOK, res);
1151 VMXNET3_REDUCE_SNAPSHOT_TX_STAT(hw, q, mcastBytesTxOK, res);
1152 VMXNET3_REDUCE_SNAPSHOT_TX_STAT(hw, q, bcastBytesTxOK, res);
1153 VMXNET3_REDUCE_SNAPSHOT_TX_STAT(hw, q, pktsTxError, res);
1154 VMXNET3_REDUCE_SNAPSHOT_TX_STAT(hw, q, pktsTxDiscard, res);
1156 #undef VMXNET3_REDUCE_SNAPSHOT_TX_STAT
1160 vmxnet3_rx_stats_get(struct vmxnet3_hw *hw, unsigned int q,
1161 struct UPT1_RxStats *res)
1163 vmxnet3_hw_rx_stats_get(hw, q, res);
1165 #define VMXNET3_REDUCE_SNAPSHOT_RX_STAT(h, i, f, r) \
1166 ((r)->f -= (h)->snapshot_rx_stats[(i)].f)
1168 VMXNET3_REDUCE_SNAPSHOT_RX_STAT(hw, q, ucastPktsRxOK, res);
1169 VMXNET3_REDUCE_SNAPSHOT_RX_STAT(hw, q, mcastPktsRxOK, res);
1170 VMXNET3_REDUCE_SNAPSHOT_RX_STAT(hw, q, bcastPktsRxOK, res);
1171 VMXNET3_REDUCE_SNAPSHOT_RX_STAT(hw, q, ucastBytesRxOK, res);
1172 VMXNET3_REDUCE_SNAPSHOT_RX_STAT(hw, q, mcastBytesRxOK, res);
1173 VMXNET3_REDUCE_SNAPSHOT_RX_STAT(hw, q, bcastBytesRxOK, res);
1174 VMXNET3_REDUCE_SNAPSHOT_RX_STAT(hw, q, pktsRxError, res);
1175 VMXNET3_REDUCE_SNAPSHOT_RX_STAT(hw, q, pktsRxOutOfBuf, res);
1177 #undef VMXNET3_REDUCE_SNAPSHOT_RX_STAT
1181 vmxnet3_hw_stats_save(struct vmxnet3_hw *hw)
1185 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, VMXNET3_CMD_GET_STATS);
1187 RTE_BUILD_BUG_ON(RTE_ETHDEV_QUEUE_STAT_CNTRS < VMXNET3_MAX_TX_QUEUES);
1189 for (i = 0; i < hw->num_tx_queues; i++)
1190 vmxnet3_hw_tx_stats_get(hw, i, &hw->saved_tx_stats[i]);
1191 for (i = 0; i < hw->num_rx_queues; i++)
1192 vmxnet3_hw_rx_stats_get(hw, i, &hw->saved_rx_stats[i]);
1196 vmxnet3_dev_xstats_get_names(struct rte_eth_dev *dev,
1197 struct rte_eth_xstat_name *xstats_names,
1200 unsigned int i, t, count = 0;
1201 unsigned int nstats =
1202 dev->data->nb_tx_queues * RTE_DIM(vmxnet3_txq_stat_strings) +
1203 dev->data->nb_rx_queues * RTE_DIM(vmxnet3_rxq_stat_strings);
1205 if (!xstats_names || n < nstats)
1208 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1209 if (!dev->data->rx_queues[i])
1212 for (t = 0; t < RTE_DIM(vmxnet3_rxq_stat_strings); t++) {
1213 snprintf(xstats_names[count].name,
1214 sizeof(xstats_names[count].name),
1216 vmxnet3_rxq_stat_strings[t].name);
1221 for (i = 0; i < dev->data->nb_tx_queues; i++) {
1222 if (!dev->data->tx_queues[i])
1225 for (t = 0; t < RTE_DIM(vmxnet3_txq_stat_strings); t++) {
1226 snprintf(xstats_names[count].name,
1227 sizeof(xstats_names[count].name),
1229 vmxnet3_txq_stat_strings[t].name);
1238 vmxnet3_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
1241 unsigned int i, t, count = 0;
1242 unsigned int nstats =
1243 dev->data->nb_tx_queues * RTE_DIM(vmxnet3_txq_stat_strings) +
1244 dev->data->nb_rx_queues * RTE_DIM(vmxnet3_rxq_stat_strings);
1249 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1250 struct vmxnet3_rx_queue *rxq = dev->data->rx_queues[i];
1255 for (t = 0; t < RTE_DIM(vmxnet3_rxq_stat_strings); t++) {
1256 xstats[count].value = *(uint64_t *)(((char *)&rxq->stats) +
1257 vmxnet3_rxq_stat_strings[t].offset);
1258 xstats[count].id = count;
1263 for (i = 0; i < dev->data->nb_tx_queues; i++) {
1264 struct vmxnet3_tx_queue *txq = dev->data->tx_queues[i];
1269 for (t = 0; t < RTE_DIM(vmxnet3_txq_stat_strings); t++) {
1270 xstats[count].value = *(uint64_t *)(((char *)&txq->stats) +
1271 vmxnet3_txq_stat_strings[t].offset);
1272 xstats[count].id = count;
1281 vmxnet3_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
1284 struct vmxnet3_hw *hw = dev->data->dev_private;
1285 struct UPT1_TxStats txStats;
1286 struct UPT1_RxStats rxStats;
1288 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, VMXNET3_CMD_GET_STATS);
1290 RTE_BUILD_BUG_ON(RTE_ETHDEV_QUEUE_STAT_CNTRS < VMXNET3_MAX_TX_QUEUES);
1291 for (i = 0; i < hw->num_tx_queues; i++) {
1292 vmxnet3_tx_stats_get(hw, i, &txStats);
1294 stats->q_opackets[i] = txStats.ucastPktsTxOK +
1295 txStats.mcastPktsTxOK +
1296 txStats.bcastPktsTxOK;
1298 stats->q_obytes[i] = txStats.ucastBytesTxOK +
1299 txStats.mcastBytesTxOK +
1300 txStats.bcastBytesTxOK;
1302 stats->opackets += stats->q_opackets[i];
1303 stats->obytes += stats->q_obytes[i];
1304 stats->oerrors += txStats.pktsTxError + txStats.pktsTxDiscard;
1307 RTE_BUILD_BUG_ON(RTE_ETHDEV_QUEUE_STAT_CNTRS < VMXNET3_MAX_RX_QUEUES);
1308 for (i = 0; i < hw->num_rx_queues; i++) {
1309 vmxnet3_rx_stats_get(hw, i, &rxStats);
1311 stats->q_ipackets[i] = rxStats.ucastPktsRxOK +
1312 rxStats.mcastPktsRxOK +
1313 rxStats.bcastPktsRxOK;
1315 stats->q_ibytes[i] = rxStats.ucastBytesRxOK +
1316 rxStats.mcastBytesRxOK +
1317 rxStats.bcastBytesRxOK;
1319 stats->ipackets += stats->q_ipackets[i];
1320 stats->ibytes += stats->q_ibytes[i];
1322 stats->q_errors[i] = rxStats.pktsRxError;
1323 stats->ierrors += rxStats.pktsRxError;
1324 stats->imissed += rxStats.pktsRxOutOfBuf;
1331 vmxnet3_dev_stats_reset(struct rte_eth_dev *dev)
1334 struct vmxnet3_hw *hw = dev->data->dev_private;
1335 struct UPT1_TxStats txStats = {0};
1336 struct UPT1_RxStats rxStats = {0};
1338 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, VMXNET3_CMD_GET_STATS);
1340 RTE_BUILD_BUG_ON(RTE_ETHDEV_QUEUE_STAT_CNTRS < VMXNET3_MAX_TX_QUEUES);
1342 for (i = 0; i < hw->num_tx_queues; i++) {
1343 vmxnet3_hw_tx_stats_get(hw, i, &txStats);
1344 memcpy(&hw->snapshot_tx_stats[i], &txStats,
1345 sizeof(hw->snapshot_tx_stats[0]));
1347 for (i = 0; i < hw->num_rx_queues; i++) {
1348 vmxnet3_hw_rx_stats_get(hw, i, &rxStats);
1349 memcpy(&hw->snapshot_rx_stats[i], &rxStats,
1350 sizeof(hw->snapshot_rx_stats[0]));
1357 vmxnet3_dev_info_get(struct rte_eth_dev *dev,
1358 struct rte_eth_dev_info *dev_info)
1360 struct vmxnet3_hw *hw = dev->data->dev_private;
1362 dev_info->max_rx_queues = VMXNET3_MAX_RX_QUEUES;
1363 dev_info->max_tx_queues = VMXNET3_MAX_TX_QUEUES;
1364 dev_info->min_rx_bufsize = 1518 + RTE_PKTMBUF_HEADROOM;
1365 dev_info->max_rx_pktlen = 16384; /* includes CRC, cf MAXFRS register */
1366 dev_info->min_mtu = VMXNET3_MIN_MTU;
1367 dev_info->max_mtu = VMXNET3_MAX_MTU;
1368 dev_info->speed_capa = RTE_ETH_LINK_SPEED_10G;
1369 dev_info->max_mac_addrs = VMXNET3_MAX_MAC_ADDRS;
1371 dev_info->flow_type_rss_offloads = VMXNET3_RSS_OFFLOAD_ALL;
1373 if (VMXNET3_VERSION_GE_4(hw)) {
1374 dev_info->flow_type_rss_offloads |= VMXNET3_V4_RSS_MASK;
1377 dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
1378 .nb_max = VMXNET3_RX_RING_MAX_SIZE,
1379 .nb_min = VMXNET3_DEF_RX_RING_SIZE,
1383 dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
1384 .nb_max = VMXNET3_TX_RING_MAX_SIZE,
1385 .nb_min = VMXNET3_DEF_TX_RING_SIZE,
1387 .nb_seg_max = VMXNET3_TX_MAX_SEG,
1388 .nb_mtu_seg_max = VMXNET3_MAX_TXD_PER_PKT,
1391 dev_info->rx_offload_capa = VMXNET3_RX_OFFLOAD_CAP;
1392 dev_info->rx_queue_offload_capa = 0;
1393 dev_info->tx_offload_capa = VMXNET3_TX_OFFLOAD_CAP;
1394 dev_info->tx_queue_offload_capa = 0;
1399 static const uint32_t *
1400 vmxnet3_dev_supported_ptypes_get(struct rte_eth_dev *dev)
1402 static const uint32_t ptypes[] = {
1403 RTE_PTYPE_L3_IPV4_EXT,
1408 if (dev->rx_pkt_burst == vmxnet3_recv_pkts)
1414 vmxnet3_dev_mtu_set(struct rte_eth_dev *dev, __rte_unused uint16_t mtu)
1416 if (dev->data->dev_started) {
1417 PMD_DRV_LOG(ERR, "Port %d must be stopped to configure MTU",
1418 dev->data->port_id);
1426 vmxnet3_mac_addr_set(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr)
1428 struct vmxnet3_hw *hw = dev->data->dev_private;
1430 rte_ether_addr_copy(mac_addr, (struct rte_ether_addr *)(hw->perm_addr));
1431 vmxnet3_write_mac(hw, mac_addr->addr_bytes);
1435 /* return 0 means link status changed, -1 means not changed */
1437 __vmxnet3_dev_link_update(struct rte_eth_dev *dev,
1438 __rte_unused int wait_to_complete)
1440 struct vmxnet3_hw *hw = dev->data->dev_private;
1441 struct rte_eth_link link;
1444 memset(&link, 0, sizeof(link));
1446 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, VMXNET3_CMD_GET_LINK);
1447 ret = VMXNET3_READ_BAR1_REG(hw, VMXNET3_REG_CMD);
1450 link.link_status = RTE_ETH_LINK_UP;
1451 link.link_duplex = RTE_ETH_LINK_FULL_DUPLEX;
1452 link.link_speed = RTE_ETH_SPEED_NUM_10G;
1453 link.link_autoneg = RTE_ETH_LINK_FIXED;
1455 return rte_eth_linkstatus_set(dev, &link);
1459 vmxnet3_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
1461 /* Link status doesn't change for stopped dev */
1462 if (dev->data->dev_started == 0)
1465 return __vmxnet3_dev_link_update(dev, wait_to_complete);
1468 /* Updating rxmode through Vmxnet3_DriverShared structure in adapter */
1470 vmxnet3_dev_set_rxmode(struct vmxnet3_hw *hw, uint32_t feature, int set)
1472 struct Vmxnet3_RxFilterConf *rxConf = &hw->shared->devRead.rxFilterConf;
1475 rxConf->rxMode = rxConf->rxMode | feature;
1477 rxConf->rxMode = rxConf->rxMode & (~feature);
1479 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, VMXNET3_CMD_UPDATE_RX_MODE);
1482 /* Promiscuous supported only if Vmxnet3_DriverShared is initialized in adapter */
1484 vmxnet3_dev_promiscuous_enable(struct rte_eth_dev *dev)
1486 struct vmxnet3_hw *hw = dev->data->dev_private;
1487 uint32_t *vf_table = hw->shared->devRead.rxFilterConf.vfTable;
1489 memset(vf_table, 0, VMXNET3_VFT_TABLE_SIZE);
1490 vmxnet3_dev_set_rxmode(hw, VMXNET3_RXM_PROMISC, 1);
1492 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD,
1493 VMXNET3_CMD_UPDATE_VLAN_FILTERS);
1498 /* Promiscuous supported only if Vmxnet3_DriverShared is initialized in adapter */
1500 vmxnet3_dev_promiscuous_disable(struct rte_eth_dev *dev)
1502 struct vmxnet3_hw *hw = dev->data->dev_private;
1503 uint32_t *vf_table = hw->shared->devRead.rxFilterConf.vfTable;
1504 uint64_t rx_offloads = dev->data->dev_conf.rxmode.offloads;
1506 if (rx_offloads & RTE_ETH_RX_OFFLOAD_VLAN_FILTER)
1507 memcpy(vf_table, hw->shadow_vfta, VMXNET3_VFT_TABLE_SIZE);
1509 memset(vf_table, 0xff, VMXNET3_VFT_TABLE_SIZE);
1510 vmxnet3_dev_set_rxmode(hw, VMXNET3_RXM_PROMISC, 0);
1511 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD,
1512 VMXNET3_CMD_UPDATE_VLAN_FILTERS);
1517 /* Allmulticast supported only if Vmxnet3_DriverShared is initialized in adapter */
1519 vmxnet3_dev_allmulticast_enable(struct rte_eth_dev *dev)
1521 struct vmxnet3_hw *hw = dev->data->dev_private;
1523 vmxnet3_dev_set_rxmode(hw, VMXNET3_RXM_ALL_MULTI, 1);
1528 /* Allmulticast supported only if Vmxnet3_DriverShared is initialized in adapter */
1530 vmxnet3_dev_allmulticast_disable(struct rte_eth_dev *dev)
1532 struct vmxnet3_hw *hw = dev->data->dev_private;
1534 vmxnet3_dev_set_rxmode(hw, VMXNET3_RXM_ALL_MULTI, 0);
1539 /* Enable/disable filter on vlan */
1541 vmxnet3_dev_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vid, int on)
1543 struct vmxnet3_hw *hw = dev->data->dev_private;
1544 struct Vmxnet3_RxFilterConf *rxConf = &hw->shared->devRead.rxFilterConf;
1545 uint32_t *vf_table = rxConf->vfTable;
1547 /* save state for restore */
1549 VMXNET3_SET_VFTABLE_ENTRY(hw->shadow_vfta, vid);
1551 VMXNET3_CLEAR_VFTABLE_ENTRY(hw->shadow_vfta, vid);
1553 /* don't change active filter if in promiscuous mode */
1554 if (rxConf->rxMode & VMXNET3_RXM_PROMISC)
1557 /* set in hardware */
1559 VMXNET3_SET_VFTABLE_ENTRY(vf_table, vid);
1561 VMXNET3_CLEAR_VFTABLE_ENTRY(vf_table, vid);
1563 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD,
1564 VMXNET3_CMD_UPDATE_VLAN_FILTERS);
1569 vmxnet3_dev_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1571 struct vmxnet3_hw *hw = dev->data->dev_private;
1572 Vmxnet3_DSDevRead *devRead = &hw->shared->devRead;
1573 uint32_t *vf_table = devRead->rxFilterConf.vfTable;
1574 uint64_t rx_offloads = dev->data->dev_conf.rxmode.offloads;
1576 if (mask & RTE_ETH_VLAN_STRIP_MASK) {
1577 if (rx_offloads & RTE_ETH_RX_OFFLOAD_VLAN_STRIP)
1578 devRead->misc.uptFeatures |= UPT1_F_RXVLAN;
1580 devRead->misc.uptFeatures &= ~UPT1_F_RXVLAN;
1582 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD,
1583 VMXNET3_CMD_UPDATE_FEATURE);
1586 if (mask & RTE_ETH_VLAN_FILTER_MASK) {
1587 if (rx_offloads & RTE_ETH_RX_OFFLOAD_VLAN_FILTER)
1588 memcpy(vf_table, hw->shadow_vfta, VMXNET3_VFT_TABLE_SIZE);
1590 memset(vf_table, 0xff, VMXNET3_VFT_TABLE_SIZE);
1592 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD,
1593 VMXNET3_CMD_UPDATE_VLAN_FILTERS);
1600 vmxnet3_process_events(struct rte_eth_dev *dev)
1602 struct vmxnet3_hw *hw = dev->data->dev_private;
1603 uint32_t events = hw->shared->ecr;
1609 * ECR bits when written with 1b are cleared. Hence write
1610 * events back to ECR so that the bits which were set will be reset.
1612 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_ECR, events);
1614 /* Check if link state has changed */
1615 if (events & VMXNET3_ECR_LINK) {
1616 PMD_DRV_LOG(DEBUG, "Process events: VMXNET3_ECR_LINK event");
1617 if (vmxnet3_dev_link_update(dev, 0) == 0)
1618 rte_eth_dev_callback_process(dev,
1619 RTE_ETH_EVENT_INTR_LSC,
1623 /* Check if there is an error on xmit/recv queues */
1624 if (events & (VMXNET3_ECR_TQERR | VMXNET3_ECR_RQERR)) {
1625 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD,
1626 VMXNET3_CMD_GET_QUEUE_STATUS);
1628 if (hw->tqd_start->status.stopped)
1629 PMD_DRV_LOG(ERR, "tq error 0x%x",
1630 hw->tqd_start->status.error);
1632 if (hw->rqd_start->status.stopped)
1633 PMD_DRV_LOG(ERR, "rq error 0x%x",
1634 hw->rqd_start->status.error);
1636 /* Reset the device */
1637 /* Have to reset the device */
1640 if (events & VMXNET3_ECR_DIC)
1641 PMD_DRV_LOG(DEBUG, "Device implementation change event.");
1643 if (events & VMXNET3_ECR_DEBUG)
1644 PMD_DRV_LOG(DEBUG, "Debug event generated by device.");
1648 vmxnet3_interrupt_handler(void *param)
1650 struct rte_eth_dev *dev = param;
1651 struct vmxnet3_hw *hw = dev->data->dev_private;
1652 Vmxnet3_DSDevRead *devRead = &hw->shared->devRead;
1655 PMD_INIT_FUNC_TRACE();
1656 vmxnet3_disable_intr(hw, devRead->intrConf.eventIntrIdx);
1658 events = VMXNET3_READ_BAR1_REG(hw, VMXNET3_REG_ECR);
1662 RTE_LOG(DEBUG, PMD, "Reading events: 0x%X", events);
1663 vmxnet3_process_events(dev);
1665 vmxnet3_enable_intr(hw, devRead->intrConf.eventIntrIdx);
1669 vmxnet3_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
1671 struct vmxnet3_hw *hw = dev->data->dev_private;
1673 vmxnet3_enable_intr(hw,
1674 rte_intr_vec_list_index_get(dev->intr_handle,
1681 vmxnet3_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
1683 struct vmxnet3_hw *hw = dev->data->dev_private;
1685 vmxnet3_disable_intr(hw,
1686 rte_intr_vec_list_index_get(dev->intr_handle, queue_id));
1691 RTE_PMD_REGISTER_PCI(net_vmxnet3, rte_vmxnet3_pmd);
1692 RTE_PMD_REGISTER_PCI_TABLE(net_vmxnet3, pci_id_vmxnet3_map);
1693 RTE_PMD_REGISTER_KMOD_DEP(net_vmxnet3, "* igb_uio | uio_pci_generic | vfio-pci");
1694 RTE_LOG_REGISTER_SUFFIX(vmxnet3_logtype_init, init, NOTICE);
1695 RTE_LOG_REGISTER_SUFFIX(vmxnet3_logtype_driver, driver, NOTICE);