1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2010-2015 Intel Corporation
14 #include <rte_byteorder.h>
15 #include <rte_common.h>
16 #include <rte_cycles.h>
18 #include <rte_interrupts.h>
20 #include <rte_debug.h>
22 #include <rte_bus_pci.h>
23 #include <rte_branch_prediction.h>
24 #include <rte_memory.h>
25 #include <rte_memzone.h>
27 #include <rte_alarm.h>
28 #include <rte_ether.h>
29 #include <rte_ethdev_driver.h>
30 #include <rte_ethdev_pci.h>
31 #include <rte_string_fns.h>
32 #include <rte_malloc.h>
35 #include "base/vmxnet3_defs.h"
37 #include "vmxnet3_ring.h"
38 #include "vmxnet3_logs.h"
39 #include "vmxnet3_ethdev.h"
41 #define PROCESS_SYS_EVENTS 0
43 #define VMXNET3_TX_MAX_SEG UINT8_MAX
45 #define VMXNET3_TX_OFFLOAD_CAP \
46 (DEV_TX_OFFLOAD_VLAN_INSERT | \
47 DEV_TX_OFFLOAD_TCP_CKSUM | \
48 DEV_TX_OFFLOAD_UDP_CKSUM | \
49 DEV_TX_OFFLOAD_TCP_TSO | \
50 DEV_TX_OFFLOAD_MULTI_SEGS)
52 #define VMXNET3_RX_OFFLOAD_CAP \
53 (DEV_RX_OFFLOAD_VLAN_STRIP | \
54 DEV_RX_OFFLOAD_VLAN_FILTER | \
55 DEV_RX_OFFLOAD_SCATTER | \
56 DEV_RX_OFFLOAD_UDP_CKSUM | \
57 DEV_RX_OFFLOAD_TCP_CKSUM | \
58 DEV_RX_OFFLOAD_TCP_LRO | \
59 DEV_RX_OFFLOAD_JUMBO_FRAME | \
60 DEV_RX_OFFLOAD_RSS_HASH)
62 static int eth_vmxnet3_dev_init(struct rte_eth_dev *eth_dev);
63 static int eth_vmxnet3_dev_uninit(struct rte_eth_dev *eth_dev);
64 static int vmxnet3_dev_configure(struct rte_eth_dev *dev);
65 static int vmxnet3_dev_start(struct rte_eth_dev *dev);
66 static void vmxnet3_dev_stop(struct rte_eth_dev *dev);
67 static int vmxnet3_dev_close(struct rte_eth_dev *dev);
68 static void vmxnet3_dev_set_rxmode(struct vmxnet3_hw *hw, uint32_t feature, int set);
69 static int vmxnet3_dev_promiscuous_enable(struct rte_eth_dev *dev);
70 static int vmxnet3_dev_promiscuous_disable(struct rte_eth_dev *dev);
71 static int vmxnet3_dev_allmulticast_enable(struct rte_eth_dev *dev);
72 static int vmxnet3_dev_allmulticast_disable(struct rte_eth_dev *dev);
73 static int __vmxnet3_dev_link_update(struct rte_eth_dev *dev,
74 int wait_to_complete);
75 static int vmxnet3_dev_link_update(struct rte_eth_dev *dev,
76 int wait_to_complete);
77 static void vmxnet3_hw_stats_save(struct vmxnet3_hw *hw);
78 static int vmxnet3_dev_stats_get(struct rte_eth_dev *dev,
79 struct rte_eth_stats *stats);
80 static int vmxnet3_dev_stats_reset(struct rte_eth_dev *dev);
81 static int vmxnet3_dev_xstats_get_names(struct rte_eth_dev *dev,
82 struct rte_eth_xstat_name *xstats,
84 static int vmxnet3_dev_xstats_get(struct rte_eth_dev *dev,
85 struct rte_eth_xstat *xstats, unsigned int n);
86 static int vmxnet3_dev_info_get(struct rte_eth_dev *dev,
87 struct rte_eth_dev_info *dev_info);
88 static const uint32_t *
89 vmxnet3_dev_supported_ptypes_get(struct rte_eth_dev *dev);
90 static int vmxnet3_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
91 static int vmxnet3_dev_vlan_filter_set(struct rte_eth_dev *dev,
92 uint16_t vid, int on);
93 static int vmxnet3_dev_vlan_offload_set(struct rte_eth_dev *dev, int mask);
94 static int vmxnet3_mac_addr_set(struct rte_eth_dev *dev,
95 struct rte_ether_addr *mac_addr);
96 static void vmxnet3_interrupt_handler(void *param);
99 * The set of PCI devices this driver supports
101 #define VMWARE_PCI_VENDOR_ID 0x15AD
102 #define VMWARE_DEV_ID_VMXNET3 0x07B0
103 static const struct rte_pci_id pci_id_vmxnet3_map[] = {
104 { RTE_PCI_DEVICE(VMWARE_PCI_VENDOR_ID, VMWARE_DEV_ID_VMXNET3) },
105 { .vendor_id = 0, /* sentinel */ },
108 static const struct eth_dev_ops vmxnet3_eth_dev_ops = {
109 .dev_configure = vmxnet3_dev_configure,
110 .dev_start = vmxnet3_dev_start,
111 .dev_stop = vmxnet3_dev_stop,
112 .dev_close = vmxnet3_dev_close,
113 .promiscuous_enable = vmxnet3_dev_promiscuous_enable,
114 .promiscuous_disable = vmxnet3_dev_promiscuous_disable,
115 .allmulticast_enable = vmxnet3_dev_allmulticast_enable,
116 .allmulticast_disable = vmxnet3_dev_allmulticast_disable,
117 .link_update = vmxnet3_dev_link_update,
118 .stats_get = vmxnet3_dev_stats_get,
119 .xstats_get_names = vmxnet3_dev_xstats_get_names,
120 .xstats_get = vmxnet3_dev_xstats_get,
121 .stats_reset = vmxnet3_dev_stats_reset,
122 .mac_addr_set = vmxnet3_mac_addr_set,
123 .dev_infos_get = vmxnet3_dev_info_get,
124 .dev_supported_ptypes_get = vmxnet3_dev_supported_ptypes_get,
125 .mtu_set = vmxnet3_dev_mtu_set,
126 .vlan_filter_set = vmxnet3_dev_vlan_filter_set,
127 .vlan_offload_set = vmxnet3_dev_vlan_offload_set,
128 .rx_queue_setup = vmxnet3_dev_rx_queue_setup,
129 .rx_queue_release = vmxnet3_dev_rx_queue_release,
130 .tx_queue_setup = vmxnet3_dev_tx_queue_setup,
131 .tx_queue_release = vmxnet3_dev_tx_queue_release,
134 struct vmxnet3_xstats_name_off {
135 char name[RTE_ETH_XSTATS_NAME_SIZE];
139 /* tx_qX_ is prepended to the name string here */
140 static const struct vmxnet3_xstats_name_off vmxnet3_txq_stat_strings[] = {
141 {"drop_total", offsetof(struct vmxnet3_txq_stats, drop_total)},
142 {"drop_too_many_segs", offsetof(struct vmxnet3_txq_stats, drop_too_many_segs)},
143 {"drop_tso", offsetof(struct vmxnet3_txq_stats, drop_tso)},
144 {"tx_ring_full", offsetof(struct vmxnet3_txq_stats, tx_ring_full)},
147 /* rx_qX_ is prepended to the name string here */
148 static const struct vmxnet3_xstats_name_off vmxnet3_rxq_stat_strings[] = {
149 {"drop_total", offsetof(struct vmxnet3_rxq_stats, drop_total)},
150 {"drop_err", offsetof(struct vmxnet3_rxq_stats, drop_err)},
151 {"drop_fcs", offsetof(struct vmxnet3_rxq_stats, drop_fcs)},
152 {"rx_buf_alloc_failure", offsetof(struct vmxnet3_rxq_stats, rx_buf_alloc_failure)},
155 static const struct rte_memzone *
156 gpa_zone_reserve(struct rte_eth_dev *dev, uint32_t size,
157 const char *post_string, int socket_id,
158 uint16_t align, bool reuse)
160 char z_name[RTE_MEMZONE_NAMESIZE];
161 const struct rte_memzone *mz;
163 snprintf(z_name, sizeof(z_name), "eth_p%d_%s",
164 dev->data->port_id, post_string);
166 mz = rte_memzone_lookup(z_name);
169 rte_memzone_free(mz);
170 return rte_memzone_reserve_aligned(z_name, size, socket_id,
171 RTE_MEMZONE_IOVA_CONTIG, align);
177 return rte_memzone_reserve_aligned(z_name, size, socket_id,
178 RTE_MEMZONE_IOVA_CONTIG, align);
182 * This function is based on vmxnet3_disable_intr()
185 vmxnet3_disable_intr(struct vmxnet3_hw *hw)
189 PMD_INIT_FUNC_TRACE();
191 hw->shared->devRead.intrConf.intrCtrl |= VMXNET3_IC_DISABLE_ALL;
192 for (i = 0; i < hw->num_intrs; i++)
193 VMXNET3_WRITE_BAR0_REG(hw, VMXNET3_REG_IMR + i * 8, 1);
197 vmxnet3_enable_intr(struct vmxnet3_hw *hw)
201 PMD_INIT_FUNC_TRACE();
203 hw->shared->devRead.intrConf.intrCtrl &= ~VMXNET3_IC_DISABLE_ALL;
204 for (i = 0; i < hw->num_intrs; i++)
205 VMXNET3_WRITE_BAR0_REG(hw, VMXNET3_REG_IMR + i * 8, 0);
209 * Gets tx data ring descriptor size.
212 eth_vmxnet3_txdata_get(struct vmxnet3_hw *hw)
214 uint16 txdata_desc_size;
216 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD,
217 VMXNET3_CMD_GET_TXDATA_DESC_SIZE);
218 txdata_desc_size = VMXNET3_READ_BAR1_REG(hw, VMXNET3_REG_CMD);
220 return (txdata_desc_size < VMXNET3_TXDATA_DESC_MIN_SIZE ||
221 txdata_desc_size > VMXNET3_TXDATA_DESC_MAX_SIZE ||
222 txdata_desc_size & VMXNET3_TXDATA_DESC_SIZE_MASK) ?
223 sizeof(struct Vmxnet3_TxDataDesc) : txdata_desc_size;
227 * It returns 0 on success.
230 eth_vmxnet3_dev_init(struct rte_eth_dev *eth_dev)
232 struct rte_pci_device *pci_dev;
233 struct vmxnet3_hw *hw = eth_dev->data->dev_private;
234 uint32_t mac_hi, mac_lo, ver;
235 struct rte_eth_link link;
237 PMD_INIT_FUNC_TRACE();
239 eth_dev->dev_ops = &vmxnet3_eth_dev_ops;
240 eth_dev->rx_pkt_burst = &vmxnet3_recv_pkts;
241 eth_dev->tx_pkt_burst = &vmxnet3_xmit_pkts;
242 eth_dev->tx_pkt_prepare = vmxnet3_prep_pkts;
243 pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
246 * for secondary processes, we don't initialize any further as primary
247 * has already done this work.
249 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
252 rte_eth_copy_pci_info(eth_dev, pci_dev);
254 /* Vendor and Device ID need to be set before init of shared code */
255 hw->device_id = pci_dev->id.device_id;
256 hw->vendor_id = pci_dev->id.vendor_id;
257 hw->hw_addr0 = (void *)pci_dev->mem_resource[0].addr;
258 hw->hw_addr1 = (void *)pci_dev->mem_resource[1].addr;
260 hw->num_rx_queues = 1;
261 hw->num_tx_queues = 1;
262 hw->bufs_per_pkt = 1;
264 /* Check h/w version compatibility with driver. */
265 ver = VMXNET3_READ_BAR1_REG(hw, VMXNET3_REG_VRRS);
266 PMD_INIT_LOG(DEBUG, "Hardware version : %d", ver);
268 if (ver & (1 << VMXNET3_REV_4)) {
269 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_VRRS,
271 hw->version = VMXNET3_REV_4 + 1;
272 } else if (ver & (1 << VMXNET3_REV_3)) {
273 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_VRRS,
275 hw->version = VMXNET3_REV_3 + 1;
276 } else if (ver & (1 << VMXNET3_REV_2)) {
277 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_VRRS,
279 hw->version = VMXNET3_REV_2 + 1;
280 } else if (ver & (1 << VMXNET3_REV_1)) {
281 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_VRRS,
283 hw->version = VMXNET3_REV_1 + 1;
285 PMD_INIT_LOG(ERR, "Incompatible hardware version: %d", ver);
289 PMD_INIT_LOG(DEBUG, "Using device version %d\n", hw->version);
291 /* Check UPT version compatibility with driver. */
292 ver = VMXNET3_READ_BAR1_REG(hw, VMXNET3_REG_UVRS);
293 PMD_INIT_LOG(DEBUG, "UPT hardware version : %d", ver);
295 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_UVRS, 1);
297 PMD_INIT_LOG(ERR, "Incompatible UPT version.");
301 /* Getting MAC Address */
302 mac_lo = VMXNET3_READ_BAR1_REG(hw, VMXNET3_REG_MACL);
303 mac_hi = VMXNET3_READ_BAR1_REG(hw, VMXNET3_REG_MACH);
304 memcpy(hw->perm_addr, &mac_lo, 4);
305 memcpy(hw->perm_addr + 4, &mac_hi, 2);
307 /* Allocate memory for storing MAC addresses */
308 eth_dev->data->mac_addrs = rte_zmalloc("vmxnet3", RTE_ETHER_ADDR_LEN *
309 VMXNET3_MAX_MAC_ADDRS, 0);
310 if (eth_dev->data->mac_addrs == NULL) {
312 "Failed to allocate %d bytes needed to store MAC addresses",
313 RTE_ETHER_ADDR_LEN * VMXNET3_MAX_MAC_ADDRS);
316 /* Copy the permanent MAC address */
317 rte_ether_addr_copy((struct rte_ether_addr *)hw->perm_addr,
318 ð_dev->data->mac_addrs[0]);
320 PMD_INIT_LOG(DEBUG, "MAC Address : %02x:%02x:%02x:%02x:%02x:%02x",
321 hw->perm_addr[0], hw->perm_addr[1], hw->perm_addr[2],
322 hw->perm_addr[3], hw->perm_addr[4], hw->perm_addr[5]);
324 /* Put device in Quiesce Mode */
325 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, VMXNET3_CMD_QUIESCE_DEV);
327 /* allow untagged pkts */
328 VMXNET3_SET_VFTABLE_ENTRY(hw->shadow_vfta, 0);
330 hw->txdata_desc_size = VMXNET3_VERSION_GE_3(hw) ?
331 eth_vmxnet3_txdata_get(hw) : sizeof(struct Vmxnet3_TxDataDesc);
333 hw->rxdata_desc_size = VMXNET3_VERSION_GE_3(hw) ?
334 VMXNET3_DEF_RXDATA_DESC_SIZE : 0;
335 RTE_ASSERT((hw->rxdata_desc_size & ~VMXNET3_RXDATA_DESC_SIZE_MASK) ==
336 hw->rxdata_desc_size);
338 /* clear shadow stats */
339 memset(hw->saved_tx_stats, 0, sizeof(hw->saved_tx_stats));
340 memset(hw->saved_rx_stats, 0, sizeof(hw->saved_rx_stats));
342 /* clear snapshot stats */
343 memset(hw->snapshot_tx_stats, 0, sizeof(hw->snapshot_tx_stats));
344 memset(hw->snapshot_rx_stats, 0, sizeof(hw->snapshot_rx_stats));
346 /* set the initial link status */
347 memset(&link, 0, sizeof(link));
348 link.link_duplex = ETH_LINK_FULL_DUPLEX;
349 link.link_speed = ETH_SPEED_NUM_10G;
350 link.link_autoneg = ETH_LINK_FIXED;
351 rte_eth_linkstatus_set(eth_dev, &link);
357 eth_vmxnet3_dev_uninit(struct rte_eth_dev *eth_dev)
359 struct vmxnet3_hw *hw = eth_dev->data->dev_private;
361 PMD_INIT_FUNC_TRACE();
363 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
366 if (hw->adapter_stopped == 0) {
367 PMD_INIT_LOG(DEBUG, "Device has not been closed.");
371 eth_dev->dev_ops = NULL;
372 eth_dev->rx_pkt_burst = NULL;
373 eth_dev->tx_pkt_burst = NULL;
374 eth_dev->tx_pkt_prepare = NULL;
379 static int eth_vmxnet3_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
380 struct rte_pci_device *pci_dev)
382 return rte_eth_dev_pci_generic_probe(pci_dev,
383 sizeof(struct vmxnet3_hw), eth_vmxnet3_dev_init);
386 static int eth_vmxnet3_pci_remove(struct rte_pci_device *pci_dev)
388 return rte_eth_dev_pci_generic_remove(pci_dev, eth_vmxnet3_dev_uninit);
391 static struct rte_pci_driver rte_vmxnet3_pmd = {
392 .id_table = pci_id_vmxnet3_map,
393 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
394 .probe = eth_vmxnet3_pci_probe,
395 .remove = eth_vmxnet3_pci_remove,
399 vmxnet3_dev_configure(struct rte_eth_dev *dev)
401 const struct rte_memzone *mz;
402 struct vmxnet3_hw *hw = dev->data->dev_private;
405 PMD_INIT_FUNC_TRACE();
407 if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG)
408 dev->data->dev_conf.rxmode.offloads |= DEV_RX_OFFLOAD_RSS_HASH;
410 if (dev->data->nb_tx_queues > VMXNET3_MAX_TX_QUEUES ||
411 dev->data->nb_rx_queues > VMXNET3_MAX_RX_QUEUES) {
412 PMD_INIT_LOG(ERR, "ERROR: Number of queues not supported");
416 if (!rte_is_power_of_2(dev->data->nb_rx_queues)) {
417 PMD_INIT_LOG(ERR, "ERROR: Number of rx queues not power of 2");
421 size = dev->data->nb_rx_queues * sizeof(struct Vmxnet3_TxQueueDesc) +
422 dev->data->nb_tx_queues * sizeof(struct Vmxnet3_RxQueueDesc);
424 if (size > UINT16_MAX)
427 hw->num_rx_queues = (uint8_t)dev->data->nb_rx_queues;
428 hw->num_tx_queues = (uint8_t)dev->data->nb_tx_queues;
431 * Allocate a memzone for Vmxnet3_DriverShared - Vmxnet3_DSDevRead
434 mz = gpa_zone_reserve(dev, sizeof(struct Vmxnet3_DriverShared),
435 "shared", rte_socket_id(), 8, 1);
438 PMD_INIT_LOG(ERR, "ERROR: Creating shared zone");
441 memset(mz->addr, 0, mz->len);
443 hw->shared = mz->addr;
444 hw->sharedPA = mz->iova;
447 * Allocate a memzone for Vmxnet3_RxQueueDesc - Vmxnet3_TxQueueDesc
450 * We cannot reuse this memzone from previous allocation as its size
451 * depends on the number of tx and rx queues, which could be different
452 * from one config to another.
454 mz = gpa_zone_reserve(dev, size, "queuedesc", rte_socket_id(),
455 VMXNET3_QUEUE_DESC_ALIGN, 0);
457 PMD_INIT_LOG(ERR, "ERROR: Creating queue descriptors zone");
460 memset(mz->addr, 0, mz->len);
462 hw->tqd_start = (Vmxnet3_TxQueueDesc *)mz->addr;
463 hw->rqd_start = (Vmxnet3_RxQueueDesc *)(hw->tqd_start + hw->num_tx_queues);
465 hw->queueDescPA = mz->iova;
466 hw->queue_desc_len = (uint16_t)size;
468 if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_RSS) {
469 /* Allocate memory structure for UPT1_RSSConf and configure */
470 mz = gpa_zone_reserve(dev, sizeof(struct VMXNET3_RSSConf),
471 "rss_conf", rte_socket_id(),
472 RTE_CACHE_LINE_SIZE, 1);
475 "ERROR: Creating rss_conf structure zone");
478 memset(mz->addr, 0, mz->len);
480 hw->rss_conf = mz->addr;
481 hw->rss_confPA = mz->iova;
488 vmxnet3_write_mac(struct vmxnet3_hw *hw, const uint8_t *addr)
493 "Writing MAC Address : %02x:%02x:%02x:%02x:%02x:%02x",
494 addr[0], addr[1], addr[2],
495 addr[3], addr[4], addr[5]);
497 memcpy(&val, addr, 4);
498 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_MACL, val);
500 memcpy(&val, addr + 4, 2);
501 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_MACH, val);
505 vmxnet3_dev_setup_memreg(struct rte_eth_dev *dev)
507 struct vmxnet3_hw *hw = dev->data->dev_private;
508 Vmxnet3_DriverShared *shared = hw->shared;
509 Vmxnet3_CmdInfo *cmdInfo;
510 struct rte_mempool *mp[VMXNET3_MAX_RX_QUEUES];
511 uint8_t index[VMXNET3_MAX_RX_QUEUES + VMXNET3_MAX_TX_QUEUES];
512 uint32_t num, i, j, size;
514 if (hw->memRegsPA == 0) {
515 const struct rte_memzone *mz;
517 size = sizeof(Vmxnet3_MemRegs) +
518 (VMXNET3_MAX_RX_QUEUES + VMXNET3_MAX_TX_QUEUES) *
519 sizeof(Vmxnet3_MemoryRegion);
521 mz = gpa_zone_reserve(dev, size, "memRegs", rte_socket_id(), 8,
524 PMD_INIT_LOG(ERR, "ERROR: Creating memRegs zone");
527 memset(mz->addr, 0, mz->len);
528 hw->memRegs = mz->addr;
529 hw->memRegsPA = mz->iova;
532 num = hw->num_rx_queues;
534 for (i = 0; i < num; i++) {
535 vmxnet3_rx_queue_t *rxq = dev->data->rx_queues[i];
542 * The same mempool could be used by multiple queues. In such a case,
543 * remove duplicate mempool entries. Only one entry is kept with
544 * bitmask indicating queues that are using this mempool.
546 for (i = 1; i < num; i++) {
547 for (j = 0; j < i; j++) {
548 if (mp[i] == mp[j]) {
557 for (i = 0; i < num; i++) {
561 Vmxnet3_MemoryRegion *mr = &hw->memRegs->memRegs[j];
564 (uintptr_t)STAILQ_FIRST(&mp[i]->mem_list)->iova;
565 mr->length = STAILQ_FIRST(&mp[i]->mem_list)->len <= INT32_MAX ?
566 STAILQ_FIRST(&mp[i]->mem_list)->len : INT32_MAX;
567 mr->txQueueBits = index[i];
568 mr->rxQueueBits = index[i];
571 "index: %u startPA: %" PRIu64 " length: %u, "
573 j, mr->startPA, mr->length, mr->rxQueueBits);
576 hw->memRegs->numRegs = j;
577 PMD_INIT_LOG(INFO, "numRegs: %u", j);
579 size = sizeof(Vmxnet3_MemRegs) +
580 (j - 1) * sizeof(Vmxnet3_MemoryRegion);
582 cmdInfo = &shared->cu.cmdInfo;
583 cmdInfo->varConf.confVer = 1;
584 cmdInfo->varConf.confLen = size;
585 cmdInfo->varConf.confPA = hw->memRegsPA;
591 vmxnet3_setup_driver_shared(struct rte_eth_dev *dev)
593 struct rte_eth_conf port_conf = dev->data->dev_conf;
594 struct vmxnet3_hw *hw = dev->data->dev_private;
595 uint32_t mtu = dev->data->mtu;
596 Vmxnet3_DriverShared *shared = hw->shared;
597 Vmxnet3_DSDevRead *devRead = &shared->devRead;
598 uint64_t rx_offloads = dev->data->dev_conf.rxmode.offloads;
604 shared->magic = VMXNET3_REV1_MAGIC;
605 devRead->misc.driverInfo.version = VMXNET3_DRIVER_VERSION_NUM;
607 /* Setting up Guest OS information */
608 devRead->misc.driverInfo.gos.gosBits = sizeof(void *) == 4 ?
609 VMXNET3_GOS_BITS_32 : VMXNET3_GOS_BITS_64;
610 devRead->misc.driverInfo.gos.gosType = VMXNET3_GOS_TYPE_LINUX;
611 devRead->misc.driverInfo.vmxnet3RevSpt = 1;
612 devRead->misc.driverInfo.uptVerSpt = 1;
614 devRead->misc.mtu = rte_le_to_cpu_32(mtu);
615 devRead->misc.queueDescPA = hw->queueDescPA;
616 devRead->misc.queueDescLen = hw->queue_desc_len;
617 devRead->misc.numTxQueues = hw->num_tx_queues;
618 devRead->misc.numRxQueues = hw->num_rx_queues;
621 * Set number of interrupts to 1
622 * PMD by default disables all the interrupts but this is MUST
623 * to activate device. It needs at least one interrupt for
624 * link events to handle
626 hw->num_intrs = devRead->intrConf.numIntrs = 1;
627 devRead->intrConf.intrCtrl |= VMXNET3_IC_DISABLE_ALL;
629 for (i = 0; i < hw->num_tx_queues; i++) {
630 Vmxnet3_TxQueueDesc *tqd = &hw->tqd_start[i];
631 vmxnet3_tx_queue_t *txq = dev->data->tx_queues[i];
633 txq->shared = &hw->tqd_start[i];
635 tqd->ctrl.txNumDeferred = 0;
636 tqd->ctrl.txThreshold = 1;
637 tqd->conf.txRingBasePA = txq->cmd_ring.basePA;
638 tqd->conf.compRingBasePA = txq->comp_ring.basePA;
639 tqd->conf.dataRingBasePA = txq->data_ring.basePA;
641 tqd->conf.txRingSize = txq->cmd_ring.size;
642 tqd->conf.compRingSize = txq->comp_ring.size;
643 tqd->conf.dataRingSize = txq->data_ring.size;
644 tqd->conf.txDataRingDescSize = txq->txdata_desc_size;
645 tqd->conf.intrIdx = txq->comp_ring.intr_idx;
646 tqd->status.stopped = TRUE;
647 tqd->status.error = 0;
648 memset(&tqd->stats, 0, sizeof(tqd->stats));
651 for (i = 0; i < hw->num_rx_queues; i++) {
652 Vmxnet3_RxQueueDesc *rqd = &hw->rqd_start[i];
653 vmxnet3_rx_queue_t *rxq = dev->data->rx_queues[i];
655 rxq->shared = &hw->rqd_start[i];
657 rqd->conf.rxRingBasePA[0] = rxq->cmd_ring[0].basePA;
658 rqd->conf.rxRingBasePA[1] = rxq->cmd_ring[1].basePA;
659 rqd->conf.compRingBasePA = rxq->comp_ring.basePA;
661 rqd->conf.rxRingSize[0] = rxq->cmd_ring[0].size;
662 rqd->conf.rxRingSize[1] = rxq->cmd_ring[1].size;
663 rqd->conf.compRingSize = rxq->comp_ring.size;
664 rqd->conf.intrIdx = rxq->comp_ring.intr_idx;
665 if (VMXNET3_VERSION_GE_3(hw)) {
666 rqd->conf.rxDataRingBasePA = rxq->data_ring.basePA;
667 rqd->conf.rxDataRingDescSize = rxq->data_desc_size;
669 rqd->status.stopped = TRUE;
670 rqd->status.error = 0;
671 memset(&rqd->stats, 0, sizeof(rqd->stats));
674 /* RxMode set to 0 of VMXNET3_RXM_xxx */
675 devRead->rxFilterConf.rxMode = 0;
677 /* Setting up feature flags */
678 if (rx_offloads & DEV_RX_OFFLOAD_CHECKSUM)
679 devRead->misc.uptFeatures |= VMXNET3_F_RXCSUM;
681 if (rx_offloads & DEV_RX_OFFLOAD_TCP_LRO) {
682 devRead->misc.uptFeatures |= VMXNET3_F_LRO;
683 devRead->misc.maxNumRxSG = 0;
686 if (port_conf.rxmode.mq_mode == ETH_MQ_RX_RSS) {
687 ret = vmxnet3_rss_configure(dev);
688 if (ret != VMXNET3_SUCCESS)
691 devRead->misc.uptFeatures |= VMXNET3_F_RSS;
692 devRead->rssConfDesc.confVer = 1;
693 devRead->rssConfDesc.confLen = sizeof(struct VMXNET3_RSSConf);
694 devRead->rssConfDesc.confPA = hw->rss_confPA;
697 ret = vmxnet3_dev_vlan_offload_set(dev,
698 ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK);
702 vmxnet3_write_mac(hw, dev->data->mac_addrs->addr_bytes);
704 return VMXNET3_SUCCESS;
708 * Configure device link speed and setup link.
709 * Must be called after eth_vmxnet3_dev_init. Other wise it might fail
710 * It returns 0 on success.
713 vmxnet3_dev_start(struct rte_eth_dev *dev)
716 struct vmxnet3_hw *hw = dev->data->dev_private;
718 PMD_INIT_FUNC_TRACE();
720 /* Save stats before it is reset by CMD_ACTIVATE */
721 vmxnet3_hw_stats_save(hw);
723 ret = vmxnet3_setup_driver_shared(dev);
724 if (ret != VMXNET3_SUCCESS)
727 /* check if lsc interrupt feature is enabled */
728 if (dev->data->dev_conf.intr_conf.lsc) {
729 struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev->device);
731 /* Setup interrupt callback */
732 rte_intr_callback_register(&pci_dev->intr_handle,
733 vmxnet3_interrupt_handler, dev);
735 if (rte_intr_enable(&pci_dev->intr_handle) < 0) {
736 PMD_INIT_LOG(ERR, "interrupt enable failed");
741 /* Exchange shared data with device */
742 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_DSAL,
743 VMXNET3_GET_ADDR_LO(hw->sharedPA));
744 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_DSAH,
745 VMXNET3_GET_ADDR_HI(hw->sharedPA));
747 /* Activate device by register write */
748 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, VMXNET3_CMD_ACTIVATE_DEV);
749 ret = VMXNET3_READ_BAR1_REG(hw, VMXNET3_REG_CMD);
752 PMD_INIT_LOG(ERR, "Device activation: UNSUCCESSFUL");
756 /* Setup memory region for rx buffers */
757 ret = vmxnet3_dev_setup_memreg(dev);
759 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD,
760 VMXNET3_CMD_REGISTER_MEMREGS);
761 ret = VMXNET3_READ_BAR1_REG(hw, VMXNET3_REG_CMD);
764 "Failed in setup memory region cmd\n");
767 PMD_INIT_LOG(DEBUG, "Failed to setup memory region\n");
770 if (VMXNET3_VERSION_GE_4(hw) &&
771 dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_RSS) {
772 /* Check for additional RSS */
773 ret = vmxnet3_v4_rss_configure(dev);
774 if (ret != VMXNET3_SUCCESS) {
775 PMD_INIT_LOG(ERR, "Failed to configure v4 RSS");
780 /* Disable interrupts */
781 vmxnet3_disable_intr(hw);
784 * Load RX queues with blank mbufs and update next2fill index for device
785 * Update RxMode of the device
787 ret = vmxnet3_dev_rxtx_init(dev);
788 if (ret != VMXNET3_SUCCESS) {
789 PMD_INIT_LOG(ERR, "Device queue init: UNSUCCESSFUL");
793 hw->adapter_stopped = FALSE;
795 /* Setting proper Rx Mode and issue Rx Mode Update command */
796 vmxnet3_dev_set_rxmode(hw, VMXNET3_RXM_UCAST | VMXNET3_RXM_BCAST, 1);
798 if (dev->data->dev_conf.intr_conf.lsc) {
799 vmxnet3_enable_intr(hw);
802 * Update link state from device since this won't be
803 * done upon starting with lsc in use. This is done
804 * only after enabling interrupts to avoid any race
805 * where the link state could change without an
806 * interrupt being fired.
808 __vmxnet3_dev_link_update(dev, 0);
811 return VMXNET3_SUCCESS;
815 * Stop device: disable rx and tx functions to allow for reconfiguring.
818 vmxnet3_dev_stop(struct rte_eth_dev *dev)
820 struct rte_eth_link link;
821 struct vmxnet3_hw *hw = dev->data->dev_private;
823 PMD_INIT_FUNC_TRACE();
825 if (hw->adapter_stopped == 1) {
826 PMD_INIT_LOG(DEBUG, "Device already stopped.");
830 /* disable interrupts */
831 vmxnet3_disable_intr(hw);
833 if (dev->data->dev_conf.intr_conf.lsc) {
834 struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev->device);
836 rte_intr_disable(&pci_dev->intr_handle);
838 rte_intr_callback_unregister(&pci_dev->intr_handle,
839 vmxnet3_interrupt_handler, dev);
842 /* quiesce the device first */
843 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, VMXNET3_CMD_QUIESCE_DEV);
844 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_DSAL, 0);
845 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_DSAH, 0);
847 /* reset the device */
848 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, VMXNET3_CMD_RESET_DEV);
849 PMD_INIT_LOG(DEBUG, "Device reset.");
851 vmxnet3_dev_clear_queues(dev);
853 /* Clear recorded link status */
854 memset(&link, 0, sizeof(link));
855 link.link_duplex = ETH_LINK_FULL_DUPLEX;
856 link.link_speed = ETH_SPEED_NUM_10G;
857 link.link_autoneg = ETH_LINK_FIXED;
858 rte_eth_linkstatus_set(dev, &link);
860 hw->adapter_stopped = 1;
864 vmxnet3_free_queues(struct rte_eth_dev *dev)
868 PMD_INIT_FUNC_TRACE();
870 for (i = 0; i < dev->data->nb_rx_queues; i++) {
871 void *rxq = dev->data->rx_queues[i];
873 vmxnet3_dev_rx_queue_release(rxq);
875 dev->data->nb_rx_queues = 0;
877 for (i = 0; i < dev->data->nb_tx_queues; i++) {
878 void *txq = dev->data->tx_queues[i];
880 vmxnet3_dev_tx_queue_release(txq);
882 dev->data->nb_tx_queues = 0;
886 * Reset and stop device.
889 vmxnet3_dev_close(struct rte_eth_dev *dev)
891 PMD_INIT_FUNC_TRACE();
892 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
895 vmxnet3_dev_stop(dev);
896 vmxnet3_free_queues(dev);
902 vmxnet3_hw_tx_stats_get(struct vmxnet3_hw *hw, unsigned int q,
903 struct UPT1_TxStats *res)
905 #define VMXNET3_UPDATE_TX_STAT(h, i, f, r) \
906 ((r)->f = (h)->tqd_start[(i)].stats.f + \
907 (h)->saved_tx_stats[(i)].f)
909 VMXNET3_UPDATE_TX_STAT(hw, q, ucastPktsTxOK, res);
910 VMXNET3_UPDATE_TX_STAT(hw, q, mcastPktsTxOK, res);
911 VMXNET3_UPDATE_TX_STAT(hw, q, bcastPktsTxOK, res);
912 VMXNET3_UPDATE_TX_STAT(hw, q, ucastBytesTxOK, res);
913 VMXNET3_UPDATE_TX_STAT(hw, q, mcastBytesTxOK, res);
914 VMXNET3_UPDATE_TX_STAT(hw, q, bcastBytesTxOK, res);
915 VMXNET3_UPDATE_TX_STAT(hw, q, pktsTxError, res);
916 VMXNET3_UPDATE_TX_STAT(hw, q, pktsTxDiscard, res);
918 #undef VMXNET3_UPDATE_TX_STAT
922 vmxnet3_hw_rx_stats_get(struct vmxnet3_hw *hw, unsigned int q,
923 struct UPT1_RxStats *res)
925 #define VMXNET3_UPDATE_RX_STAT(h, i, f, r) \
926 ((r)->f = (h)->rqd_start[(i)].stats.f + \
927 (h)->saved_rx_stats[(i)].f)
929 VMXNET3_UPDATE_RX_STAT(hw, q, ucastPktsRxOK, res);
930 VMXNET3_UPDATE_RX_STAT(hw, q, mcastPktsRxOK, res);
931 VMXNET3_UPDATE_RX_STAT(hw, q, bcastPktsRxOK, res);
932 VMXNET3_UPDATE_RX_STAT(hw, q, ucastBytesRxOK, res);
933 VMXNET3_UPDATE_RX_STAT(hw, q, mcastBytesRxOK, res);
934 VMXNET3_UPDATE_RX_STAT(hw, q, bcastBytesRxOK, res);
935 VMXNET3_UPDATE_RX_STAT(hw, q, pktsRxError, res);
936 VMXNET3_UPDATE_RX_STAT(hw, q, pktsRxOutOfBuf, res);
938 #undef VMXNET3_UPDATE_RX_STAT
942 vmxnet3_tx_stats_get(struct vmxnet3_hw *hw, unsigned int q,
943 struct UPT1_TxStats *res)
945 vmxnet3_hw_tx_stats_get(hw, q, res);
947 #define VMXNET3_REDUCE_SNAPSHOT_TX_STAT(h, i, f, r) \
948 ((r)->f -= (h)->snapshot_tx_stats[(i)].f)
950 VMXNET3_REDUCE_SNAPSHOT_TX_STAT(hw, q, ucastPktsTxOK, res);
951 VMXNET3_REDUCE_SNAPSHOT_TX_STAT(hw, q, mcastPktsTxOK, res);
952 VMXNET3_REDUCE_SNAPSHOT_TX_STAT(hw, q, bcastPktsTxOK, res);
953 VMXNET3_REDUCE_SNAPSHOT_TX_STAT(hw, q, ucastBytesTxOK, res);
954 VMXNET3_REDUCE_SNAPSHOT_TX_STAT(hw, q, mcastBytesTxOK, res);
955 VMXNET3_REDUCE_SNAPSHOT_TX_STAT(hw, q, bcastBytesTxOK, res);
956 VMXNET3_REDUCE_SNAPSHOT_TX_STAT(hw, q, pktsTxError, res);
957 VMXNET3_REDUCE_SNAPSHOT_TX_STAT(hw, q, pktsTxDiscard, res);
959 #undef VMXNET3_REDUCE_SNAPSHOT_TX_STAT
963 vmxnet3_rx_stats_get(struct vmxnet3_hw *hw, unsigned int q,
964 struct UPT1_RxStats *res)
966 vmxnet3_hw_rx_stats_get(hw, q, res);
968 #define VMXNET3_REDUCE_SNAPSHOT_RX_STAT(h, i, f, r) \
969 ((r)->f -= (h)->snapshot_rx_stats[(i)].f)
971 VMXNET3_REDUCE_SNAPSHOT_RX_STAT(hw, q, ucastPktsRxOK, res);
972 VMXNET3_REDUCE_SNAPSHOT_RX_STAT(hw, q, mcastPktsRxOK, res);
973 VMXNET3_REDUCE_SNAPSHOT_RX_STAT(hw, q, bcastPktsRxOK, res);
974 VMXNET3_REDUCE_SNAPSHOT_RX_STAT(hw, q, ucastBytesRxOK, res);
975 VMXNET3_REDUCE_SNAPSHOT_RX_STAT(hw, q, mcastBytesRxOK, res);
976 VMXNET3_REDUCE_SNAPSHOT_RX_STAT(hw, q, bcastBytesRxOK, res);
977 VMXNET3_REDUCE_SNAPSHOT_RX_STAT(hw, q, pktsRxError, res);
978 VMXNET3_REDUCE_SNAPSHOT_RX_STAT(hw, q, pktsRxOutOfBuf, res);
980 #undef VMXNET3_REDUCE_SNAPSHOT_RX_STAT
984 vmxnet3_hw_stats_save(struct vmxnet3_hw *hw)
988 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, VMXNET3_CMD_GET_STATS);
990 RTE_BUILD_BUG_ON(RTE_ETHDEV_QUEUE_STAT_CNTRS < VMXNET3_MAX_TX_QUEUES);
992 for (i = 0; i < hw->num_tx_queues; i++)
993 vmxnet3_hw_tx_stats_get(hw, i, &hw->saved_tx_stats[i]);
994 for (i = 0; i < hw->num_rx_queues; i++)
995 vmxnet3_hw_rx_stats_get(hw, i, &hw->saved_rx_stats[i]);
999 vmxnet3_dev_xstats_get_names(struct rte_eth_dev *dev,
1000 struct rte_eth_xstat_name *xstats_names,
1003 unsigned int i, t, count = 0;
1004 unsigned int nstats =
1005 dev->data->nb_tx_queues * RTE_DIM(vmxnet3_txq_stat_strings) +
1006 dev->data->nb_rx_queues * RTE_DIM(vmxnet3_rxq_stat_strings);
1008 if (!xstats_names || n < nstats)
1011 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1012 if (!dev->data->rx_queues[i])
1015 for (t = 0; t < RTE_DIM(vmxnet3_rxq_stat_strings); t++) {
1016 snprintf(xstats_names[count].name,
1017 sizeof(xstats_names[count].name),
1019 vmxnet3_rxq_stat_strings[t].name);
1024 for (i = 0; i < dev->data->nb_tx_queues; i++) {
1025 if (!dev->data->tx_queues[i])
1028 for (t = 0; t < RTE_DIM(vmxnet3_txq_stat_strings); t++) {
1029 snprintf(xstats_names[count].name,
1030 sizeof(xstats_names[count].name),
1032 vmxnet3_txq_stat_strings[t].name);
1041 vmxnet3_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
1044 unsigned int i, t, count = 0;
1045 unsigned int nstats =
1046 dev->data->nb_tx_queues * RTE_DIM(vmxnet3_txq_stat_strings) +
1047 dev->data->nb_rx_queues * RTE_DIM(vmxnet3_rxq_stat_strings);
1052 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1053 struct vmxnet3_rx_queue *rxq = dev->data->rx_queues[i];
1058 for (t = 0; t < RTE_DIM(vmxnet3_rxq_stat_strings); t++) {
1059 xstats[count].value = *(uint64_t *)(((char *)&rxq->stats) +
1060 vmxnet3_rxq_stat_strings[t].offset);
1061 xstats[count].id = count;
1066 for (i = 0; i < dev->data->nb_tx_queues; i++) {
1067 struct vmxnet3_tx_queue *txq = dev->data->tx_queues[i];
1072 for (t = 0; t < RTE_DIM(vmxnet3_txq_stat_strings); t++) {
1073 xstats[count].value = *(uint64_t *)(((char *)&txq->stats) +
1074 vmxnet3_txq_stat_strings[t].offset);
1075 xstats[count].id = count;
1084 vmxnet3_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
1087 struct vmxnet3_hw *hw = dev->data->dev_private;
1088 struct UPT1_TxStats txStats;
1089 struct UPT1_RxStats rxStats;
1091 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, VMXNET3_CMD_GET_STATS);
1093 RTE_BUILD_BUG_ON(RTE_ETHDEV_QUEUE_STAT_CNTRS < VMXNET3_MAX_TX_QUEUES);
1094 for (i = 0; i < hw->num_tx_queues; i++) {
1095 vmxnet3_tx_stats_get(hw, i, &txStats);
1097 stats->q_opackets[i] = txStats.ucastPktsTxOK +
1098 txStats.mcastPktsTxOK +
1099 txStats.bcastPktsTxOK;
1101 stats->q_obytes[i] = txStats.ucastBytesTxOK +
1102 txStats.mcastBytesTxOK +
1103 txStats.bcastBytesTxOK;
1105 stats->opackets += stats->q_opackets[i];
1106 stats->obytes += stats->q_obytes[i];
1107 stats->oerrors += txStats.pktsTxError + txStats.pktsTxDiscard;
1110 RTE_BUILD_BUG_ON(RTE_ETHDEV_QUEUE_STAT_CNTRS < VMXNET3_MAX_RX_QUEUES);
1111 for (i = 0; i < hw->num_rx_queues; i++) {
1112 vmxnet3_rx_stats_get(hw, i, &rxStats);
1114 stats->q_ipackets[i] = rxStats.ucastPktsRxOK +
1115 rxStats.mcastPktsRxOK +
1116 rxStats.bcastPktsRxOK;
1118 stats->q_ibytes[i] = rxStats.ucastBytesRxOK +
1119 rxStats.mcastBytesRxOK +
1120 rxStats.bcastBytesRxOK;
1122 stats->ipackets += stats->q_ipackets[i];
1123 stats->ibytes += stats->q_ibytes[i];
1125 stats->q_errors[i] = rxStats.pktsRxError;
1126 stats->ierrors += rxStats.pktsRxError;
1127 stats->imissed += rxStats.pktsRxOutOfBuf;
1134 vmxnet3_dev_stats_reset(struct rte_eth_dev *dev)
1137 struct vmxnet3_hw *hw = dev->data->dev_private;
1138 struct UPT1_TxStats txStats = {0};
1139 struct UPT1_RxStats rxStats = {0};
1141 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, VMXNET3_CMD_GET_STATS);
1143 RTE_BUILD_BUG_ON(RTE_ETHDEV_QUEUE_STAT_CNTRS < VMXNET3_MAX_TX_QUEUES);
1145 for (i = 0; i < hw->num_tx_queues; i++) {
1146 vmxnet3_hw_tx_stats_get(hw, i, &txStats);
1147 memcpy(&hw->snapshot_tx_stats[i], &txStats,
1148 sizeof(hw->snapshot_tx_stats[0]));
1150 for (i = 0; i < hw->num_rx_queues; i++) {
1151 vmxnet3_hw_rx_stats_get(hw, i, &rxStats);
1152 memcpy(&hw->snapshot_rx_stats[i], &rxStats,
1153 sizeof(hw->snapshot_rx_stats[0]));
1160 vmxnet3_dev_info_get(struct rte_eth_dev *dev,
1161 struct rte_eth_dev_info *dev_info)
1163 struct vmxnet3_hw *hw = dev->data->dev_private;
1165 dev_info->max_rx_queues = VMXNET3_MAX_RX_QUEUES;
1166 dev_info->max_tx_queues = VMXNET3_MAX_TX_QUEUES;
1167 dev_info->min_rx_bufsize = 1518 + RTE_PKTMBUF_HEADROOM;
1168 dev_info->max_rx_pktlen = 16384; /* includes CRC, cf MAXFRS register */
1169 dev_info->min_mtu = VMXNET3_MIN_MTU;
1170 dev_info->max_mtu = VMXNET3_MAX_MTU;
1171 dev_info->speed_capa = ETH_LINK_SPEED_10G;
1172 dev_info->max_mac_addrs = VMXNET3_MAX_MAC_ADDRS;
1174 dev_info->flow_type_rss_offloads = VMXNET3_RSS_OFFLOAD_ALL;
1176 if (VMXNET3_VERSION_GE_4(hw)) {
1177 dev_info->flow_type_rss_offloads |= VMXNET3_V4_RSS_MASK;
1180 dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
1181 .nb_max = VMXNET3_RX_RING_MAX_SIZE,
1182 .nb_min = VMXNET3_DEF_RX_RING_SIZE,
1186 dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
1187 .nb_max = VMXNET3_TX_RING_MAX_SIZE,
1188 .nb_min = VMXNET3_DEF_TX_RING_SIZE,
1190 .nb_seg_max = VMXNET3_TX_MAX_SEG,
1191 .nb_mtu_seg_max = VMXNET3_MAX_TXD_PER_PKT,
1194 dev_info->rx_offload_capa = VMXNET3_RX_OFFLOAD_CAP;
1195 dev_info->rx_queue_offload_capa = 0;
1196 dev_info->tx_offload_capa = VMXNET3_TX_OFFLOAD_CAP;
1197 dev_info->tx_queue_offload_capa = 0;
1202 static const uint32_t *
1203 vmxnet3_dev_supported_ptypes_get(struct rte_eth_dev *dev)
1205 static const uint32_t ptypes[] = {
1206 RTE_PTYPE_L3_IPV4_EXT,
1211 if (dev->rx_pkt_burst == vmxnet3_recv_pkts)
1217 vmxnet3_dev_mtu_set(struct rte_eth_dev *dev, __rte_unused uint16_t mtu)
1219 if (dev->data->dev_started) {
1220 PMD_DRV_LOG(ERR, "Port %d must be stopped to configure MTU",
1221 dev->data->port_id);
1229 vmxnet3_mac_addr_set(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr)
1231 struct vmxnet3_hw *hw = dev->data->dev_private;
1233 rte_ether_addr_copy(mac_addr, (struct rte_ether_addr *)(hw->perm_addr));
1234 vmxnet3_write_mac(hw, mac_addr->addr_bytes);
1238 /* return 0 means link status changed, -1 means not changed */
1240 __vmxnet3_dev_link_update(struct rte_eth_dev *dev,
1241 __rte_unused int wait_to_complete)
1243 struct vmxnet3_hw *hw = dev->data->dev_private;
1244 struct rte_eth_link link;
1247 memset(&link, 0, sizeof(link));
1249 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, VMXNET3_CMD_GET_LINK);
1250 ret = VMXNET3_READ_BAR1_REG(hw, VMXNET3_REG_CMD);
1253 link.link_status = ETH_LINK_UP;
1254 link.link_duplex = ETH_LINK_FULL_DUPLEX;
1255 link.link_speed = ETH_SPEED_NUM_10G;
1256 link.link_autoneg = ETH_LINK_FIXED;
1258 return rte_eth_linkstatus_set(dev, &link);
1262 vmxnet3_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
1264 /* Link status doesn't change for stopped dev */
1265 if (dev->data->dev_started == 0)
1268 return __vmxnet3_dev_link_update(dev, wait_to_complete);
1271 /* Updating rxmode through Vmxnet3_DriverShared structure in adapter */
1273 vmxnet3_dev_set_rxmode(struct vmxnet3_hw *hw, uint32_t feature, int set)
1275 struct Vmxnet3_RxFilterConf *rxConf = &hw->shared->devRead.rxFilterConf;
1278 rxConf->rxMode = rxConf->rxMode | feature;
1280 rxConf->rxMode = rxConf->rxMode & (~feature);
1282 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, VMXNET3_CMD_UPDATE_RX_MODE);
1285 /* Promiscuous supported only if Vmxnet3_DriverShared is initialized in adapter */
1287 vmxnet3_dev_promiscuous_enable(struct rte_eth_dev *dev)
1289 struct vmxnet3_hw *hw = dev->data->dev_private;
1290 uint32_t *vf_table = hw->shared->devRead.rxFilterConf.vfTable;
1292 memset(vf_table, 0, VMXNET3_VFT_TABLE_SIZE);
1293 vmxnet3_dev_set_rxmode(hw, VMXNET3_RXM_PROMISC, 1);
1295 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD,
1296 VMXNET3_CMD_UPDATE_VLAN_FILTERS);
1301 /* Promiscuous supported only if Vmxnet3_DriverShared is initialized in adapter */
1303 vmxnet3_dev_promiscuous_disable(struct rte_eth_dev *dev)
1305 struct vmxnet3_hw *hw = dev->data->dev_private;
1306 uint32_t *vf_table = hw->shared->devRead.rxFilterConf.vfTable;
1307 uint64_t rx_offloads = dev->data->dev_conf.rxmode.offloads;
1309 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
1310 memcpy(vf_table, hw->shadow_vfta, VMXNET3_VFT_TABLE_SIZE);
1312 memset(vf_table, 0xff, VMXNET3_VFT_TABLE_SIZE);
1313 vmxnet3_dev_set_rxmode(hw, VMXNET3_RXM_PROMISC, 0);
1314 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD,
1315 VMXNET3_CMD_UPDATE_VLAN_FILTERS);
1320 /* Allmulticast supported only if Vmxnet3_DriverShared is initialized in adapter */
1322 vmxnet3_dev_allmulticast_enable(struct rte_eth_dev *dev)
1324 struct vmxnet3_hw *hw = dev->data->dev_private;
1326 vmxnet3_dev_set_rxmode(hw, VMXNET3_RXM_ALL_MULTI, 1);
1331 /* Allmulticast supported only if Vmxnet3_DriverShared is initialized in adapter */
1333 vmxnet3_dev_allmulticast_disable(struct rte_eth_dev *dev)
1335 struct vmxnet3_hw *hw = dev->data->dev_private;
1337 vmxnet3_dev_set_rxmode(hw, VMXNET3_RXM_ALL_MULTI, 0);
1342 /* Enable/disable filter on vlan */
1344 vmxnet3_dev_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vid, int on)
1346 struct vmxnet3_hw *hw = dev->data->dev_private;
1347 struct Vmxnet3_RxFilterConf *rxConf = &hw->shared->devRead.rxFilterConf;
1348 uint32_t *vf_table = rxConf->vfTable;
1350 /* save state for restore */
1352 VMXNET3_SET_VFTABLE_ENTRY(hw->shadow_vfta, vid);
1354 VMXNET3_CLEAR_VFTABLE_ENTRY(hw->shadow_vfta, vid);
1356 /* don't change active filter if in promiscuous mode */
1357 if (rxConf->rxMode & VMXNET3_RXM_PROMISC)
1360 /* set in hardware */
1362 VMXNET3_SET_VFTABLE_ENTRY(vf_table, vid);
1364 VMXNET3_CLEAR_VFTABLE_ENTRY(vf_table, vid);
1366 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD,
1367 VMXNET3_CMD_UPDATE_VLAN_FILTERS);
1372 vmxnet3_dev_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1374 struct vmxnet3_hw *hw = dev->data->dev_private;
1375 Vmxnet3_DSDevRead *devRead = &hw->shared->devRead;
1376 uint32_t *vf_table = devRead->rxFilterConf.vfTable;
1377 uint64_t rx_offloads = dev->data->dev_conf.rxmode.offloads;
1379 if (mask & ETH_VLAN_STRIP_MASK) {
1380 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
1381 devRead->misc.uptFeatures |= UPT1_F_RXVLAN;
1383 devRead->misc.uptFeatures &= ~UPT1_F_RXVLAN;
1385 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD,
1386 VMXNET3_CMD_UPDATE_FEATURE);
1389 if (mask & ETH_VLAN_FILTER_MASK) {
1390 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
1391 memcpy(vf_table, hw->shadow_vfta, VMXNET3_VFT_TABLE_SIZE);
1393 memset(vf_table, 0xff, VMXNET3_VFT_TABLE_SIZE);
1395 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD,
1396 VMXNET3_CMD_UPDATE_VLAN_FILTERS);
1403 vmxnet3_process_events(struct rte_eth_dev *dev)
1405 struct vmxnet3_hw *hw = dev->data->dev_private;
1406 uint32_t events = hw->shared->ecr;
1412 * ECR bits when written with 1b are cleared. Hence write
1413 * events back to ECR so that the bits which were set will be reset.
1415 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_ECR, events);
1417 /* Check if link state has changed */
1418 if (events & VMXNET3_ECR_LINK) {
1419 PMD_DRV_LOG(DEBUG, "Process events: VMXNET3_ECR_LINK event");
1420 if (vmxnet3_dev_link_update(dev, 0) == 0)
1421 rte_eth_dev_callback_process(dev,
1422 RTE_ETH_EVENT_INTR_LSC,
1426 /* Check if there is an error on xmit/recv queues */
1427 if (events & (VMXNET3_ECR_TQERR | VMXNET3_ECR_RQERR)) {
1428 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD,
1429 VMXNET3_CMD_GET_QUEUE_STATUS);
1431 if (hw->tqd_start->status.stopped)
1432 PMD_DRV_LOG(ERR, "tq error 0x%x",
1433 hw->tqd_start->status.error);
1435 if (hw->rqd_start->status.stopped)
1436 PMD_DRV_LOG(ERR, "rq error 0x%x",
1437 hw->rqd_start->status.error);
1439 /* Reset the device */
1440 /* Have to reset the device */
1443 if (events & VMXNET3_ECR_DIC)
1444 PMD_DRV_LOG(DEBUG, "Device implementation change event.");
1446 if (events & VMXNET3_ECR_DEBUG)
1447 PMD_DRV_LOG(DEBUG, "Debug event generated by device.");
1451 vmxnet3_interrupt_handler(void *param)
1453 struct rte_eth_dev *dev = param;
1454 struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev->device);
1456 vmxnet3_process_events(dev);
1458 if (rte_intr_ack(&pci_dev->intr_handle) < 0)
1459 PMD_DRV_LOG(ERR, "interrupt enable failed");
1462 RTE_PMD_REGISTER_PCI(net_vmxnet3, rte_vmxnet3_pmd);
1463 RTE_PMD_REGISTER_PCI_TABLE(net_vmxnet3, pci_id_vmxnet3_map);
1464 RTE_PMD_REGISTER_KMOD_DEP(net_vmxnet3, "* igb_uio | uio_pci_generic | vfio-pci");
1465 RTE_LOG_REGISTER(vmxnet3_logtype_init, pmd.net.vmxnet3.init, NOTICE);
1466 RTE_LOG_REGISTER(vmxnet3_logtype_driver, pmd.net.vmxnet3.driver, NOTICE);