drivers/net/vmxnet3/vmxnet3_ethdev.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2015 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <sys/queue.h>
  35 #include <stdio.h>
  36 #include <errno.h>
  37 #include <stdint.h>
  38 #include <string.h>
  39 #include <unistd.h>
  40 #include <stdarg.h>
  41 #include <fcntl.h>
  42 #include <inttypes.h>
  43 #include <rte_byteorder.h>
  44 #include <rte_common.h>
  45 #include <rte_cycles.h>
  46
  47 #include <rte_interrupts.h>
  48 #include <rte_log.h>
  49 #include <rte_debug.h>
  50 #include <rte_pci.h>
  51 #include <rte_atomic.h>
  52 #include <rte_branch_prediction.h>
  53 #include <rte_memory.h>
  54 #include <rte_memzone.h>
  55 #include <rte_eal.h>
  56 #include <rte_alarm.h>
  57 #include <rte_ether.h>
  58 #include <rte_ethdev.h>
  59 #include <rte_ethdev_pci.h>
  60 #include <rte_atomic.h>
  61 #include <rte_string_fns.h>
  62 #include <rte_malloc.h>
  63 #include <rte_dev.h>
  64
  65 #include "base/vmxnet3_defs.h"
  66
  67 #include "vmxnet3_ring.h"
  68 #include "vmxnet3_logs.h"
  69 #include "vmxnet3_ethdev.h"
  70
  71 #define PROCESS_SYS_EVENTS 0
  72
  73 #define VMXNET3_TX_MAX_SEG      UINT8_MAX
  74
  75 static int eth_vmxnet3_dev_init(struct rte_eth_dev *eth_dev);
  76 static int eth_vmxnet3_dev_uninit(struct rte_eth_dev *eth_dev);
  77 static int vmxnet3_dev_configure(struct rte_eth_dev *dev);
  78 static int vmxnet3_dev_start(struct rte_eth_dev *dev);
  79 static void vmxnet3_dev_stop(struct rte_eth_dev *dev);
  80 static void vmxnet3_dev_close(struct rte_eth_dev *dev);
  81 static void vmxnet3_dev_set_rxmode(struct vmxnet3_hw *hw, uint32_t feature, int set);
  82 static void vmxnet3_dev_promiscuous_enable(struct rte_eth_dev *dev);
  83 static void vmxnet3_dev_promiscuous_disable(struct rte_eth_dev *dev);
  84 static void vmxnet3_dev_allmulticast_enable(struct rte_eth_dev *dev);
  85 static void vmxnet3_dev_allmulticast_disable(struct rte_eth_dev *dev);
  86 static int vmxnet3_dev_link_update(struct rte_eth_dev *dev,
  87                                    int wait_to_complete);
  88 static void vmxnet3_hw_stats_save(struct vmxnet3_hw *hw);
  89 static void vmxnet3_dev_stats_get(struct rte_eth_dev *dev,
  90                                   struct rte_eth_stats *stats);
  91 static void vmxnet3_dev_info_get(struct rte_eth_dev *dev,
  92                                  struct rte_eth_dev_info *dev_info);
  93 static const uint32_t *
  94 vmxnet3_dev_supported_ptypes_get(struct rte_eth_dev *dev);
  95 static int vmxnet3_dev_vlan_filter_set(struct rte_eth_dev *dev,
  96                                        uint16_t vid, int on);
  97 static void vmxnet3_dev_vlan_offload_set(struct rte_eth_dev *dev, int mask);
  98 static void vmxnet3_mac_addr_set(struct rte_eth_dev *dev,
  99                                  struct ether_addr *mac_addr);
 100
 101 #if PROCESS_SYS_EVENTS == 1
 102 static void vmxnet3_process_events(struct vmxnet3_hw *);
 103 #endif
 104 /*
 105  * The set of PCI devices this driver supports
 106  */
 107 #define VMWARE_PCI_VENDOR_ID 0x15AD
 108 #define VMWARE_DEV_ID_VMXNET3 0x07B0
 109 static const struct rte_pci_id pci_id_vmxnet3_map[] = {
 110         { RTE_PCI_DEVICE(VMWARE_PCI_VENDOR_ID, VMWARE_DEV_ID_VMXNET3) },
 111         { .vendor_id = 0, /* sentinel */ },
 112 };
 113
 114 static const struct eth_dev_ops vmxnet3_eth_dev_ops = {
 115         .dev_configure        = vmxnet3_dev_configure,
 116         .dev_start            = vmxnet3_dev_start,
 117         .dev_stop             = vmxnet3_dev_stop,
 118         .dev_close            = vmxnet3_dev_close,
 119         .promiscuous_enable   = vmxnet3_dev_promiscuous_enable,
 120         .promiscuous_disable  = vmxnet3_dev_promiscuous_disable,
 121         .allmulticast_enable  = vmxnet3_dev_allmulticast_enable,
 122         .allmulticast_disable = vmxnet3_dev_allmulticast_disable,
 123         .link_update          = vmxnet3_dev_link_update,
 124         .stats_get            = vmxnet3_dev_stats_get,
 125         .mac_addr_set         = vmxnet3_mac_addr_set,
 126         .dev_infos_get        = vmxnet3_dev_info_get,
 127         .dev_supported_ptypes_get = vmxnet3_dev_supported_ptypes_get,
 128         .vlan_filter_set      = vmxnet3_dev_vlan_filter_set,
 129         .vlan_offload_set     = vmxnet3_dev_vlan_offload_set,
 130         .rx_queue_setup       = vmxnet3_dev_rx_queue_setup,
 131         .rx_queue_release     = vmxnet3_dev_rx_queue_release,
 132         .tx_queue_setup       = vmxnet3_dev_tx_queue_setup,
 133         .tx_queue_release     = vmxnet3_dev_tx_queue_release,
 134 };
 135
 136 static const struct rte_memzone *
 137 gpa_zone_reserve(struct rte_eth_dev *dev, uint32_t size,
 138                  const char *post_string, int socket_id,
 139                  uint16_t align, bool reuse)
 140 {
 141         char z_name[RTE_MEMZONE_NAMESIZE];
 142         const struct rte_memzone *mz;
 143
 144         snprintf(z_name, sizeof(z_name), "%s_%d_%s",
 145                  dev->device->driver->name, dev->data->port_id, post_string);
 146
 147         mz = rte_memzone_lookup(z_name);
 148         if (!reuse) {
 149                 if (mz)
 150                         rte_memzone_free(mz);
 151                 return rte_memzone_reserve_aligned(z_name, size, socket_id,
 152                                                    0, align);
 153         }
 154
 155         if (mz)
 156                 return mz;
 157
 158         return rte_memzone_reserve_aligned(z_name, size, socket_id, 0, align);
 159 }
 160
 161 /**
 162  * Atomically reads the link status information from global
 163  * structure rte_eth_dev.
 164  *
 165  * @param dev
 166  *   - Pointer to the structure rte_eth_dev to read from.
 167  *   - Pointer to the buffer to be saved with the link status.
 168  *
 169  * @return
 170  *   - On success, zero.
 171  *   - On failure, negative value.
 172  */
 173
 174 static int
 175 vmxnet3_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 176                                     struct rte_eth_link *link)
 177 {
 178         struct rte_eth_link *dst = link;
 179         struct rte_eth_link *src = &(dev->data->dev_link);
 180
 181         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 182                                 *(uint64_t *)src) == 0)
 183                 return -1;
 184
 185         return 0;
 186 }
 187
 188 /**
 189  * Atomically writes the link status information into global
 190  * structure rte_eth_dev.
 191  *
 192  * @param dev
 193  *   - Pointer to the structure rte_eth_dev to write to.
 194  *   - Pointer to the buffer to be saved with the link status.
 195  *
 196  * @return
 197  *   - On success, zero.
 198  *   - On failure, negative value.
 199  */
 200 static int
 201 vmxnet3_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 202                                      struct rte_eth_link *link)
 203 {
 204         struct rte_eth_link *dst = &(dev->data->dev_link);
 205         struct rte_eth_link *src = link;
 206
 207         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 208                                 *(uint64_t *)src) == 0)
 209                 return -1;
 210
 211         return 0;
 212 }
 213
 214 /*
 215  * This function is based on vmxnet3_disable_intr()
 216  */
 217 static void
 218 vmxnet3_disable_intr(struct vmxnet3_hw *hw)
 219 {
 220         int i;
 221
 222         PMD_INIT_FUNC_TRACE();
 223
 224         hw->shared->devRead.intrConf.intrCtrl |= VMXNET3_IC_DISABLE_ALL;
 225         for (i = 0; i < VMXNET3_MAX_INTRS; i++)
 226                 VMXNET3_WRITE_BAR0_REG(hw, VMXNET3_REG_IMR + i * 8, 1);
 227 }
 228
 229 /*
 230  * Gets tx data ring descriptor size.
 231  */
 232 static uint16_t
 233 eth_vmxnet3_txdata_get(struct vmxnet3_hw *hw)
 234 {
 235         uint16 txdata_desc_size;
 236
 237         VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD,
 238                                VMXNET3_CMD_GET_TXDATA_DESC_SIZE);
 239         txdata_desc_size = VMXNET3_READ_BAR1_REG(hw, VMXNET3_REG_CMD);
 240
 241         return (txdata_desc_size < VMXNET3_TXDATA_DESC_MIN_SIZE ||
 242                 txdata_desc_size > VMXNET3_TXDATA_DESC_MAX_SIZE ||
 243                 txdata_desc_size & VMXNET3_TXDATA_DESC_SIZE_MASK) ?
 244                 sizeof(struct Vmxnet3_TxDataDesc) : txdata_desc_size;
 245 }
 246
 247 /*
 248  * It returns 0 on success.
 249  */
 250 static int
 251 eth_vmxnet3_dev_init(struct rte_eth_dev *eth_dev)
 252 {
 253         struct rte_pci_device *pci_dev;
 254         struct vmxnet3_hw *hw = eth_dev->data->dev_private;
 255         uint32_t mac_hi, mac_lo, ver;
 256
 257         PMD_INIT_FUNC_TRACE();
 258
 259         eth_dev->dev_ops = &vmxnet3_eth_dev_ops;
 260         eth_dev->rx_pkt_burst = &vmxnet3_recv_pkts;
 261         eth_dev->tx_pkt_burst = &vmxnet3_xmit_pkts;
 262         eth_dev->tx_pkt_prepare = vmxnet3_prep_pkts;
 263         pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
 264
 265         /*
 266          * for secondary processes, we don't initialize any further as primary
 267          * has already done this work.
 268          */
 269         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
 270                 return 0;
 271
 272         rte_eth_copy_pci_info(eth_dev, pci_dev);
 273         eth_dev->data->dev_flags |= RTE_ETH_DEV_DETACHABLE;
 274
 275         /* Vendor and Device ID need to be set before init of shared code */
 276         hw->device_id = pci_dev->id.device_id;
 277         hw->vendor_id = pci_dev->id.vendor_id;
 278         hw->hw_addr0 = (void *)pci_dev->mem_resource[0].addr;
 279         hw->hw_addr1 = (void *)pci_dev->mem_resource[1].addr;
 280
 281         hw->num_rx_queues = 1;
 282         hw->num_tx_queues = 1;
 283         hw->bufs_per_pkt = 1;
 284
 285         /* Check h/w version compatibility with driver. */
 286         ver = VMXNET3_READ_BAR1_REG(hw, VMXNET3_REG_VRRS);
 287         PMD_INIT_LOG(DEBUG, "Hardware version : %d", ver);
 288
 289         if (ver & (1 << VMXNET3_REV_3)) {
 290                 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_VRRS,
 291                                        1 << VMXNET3_REV_3);
 292                 hw->version = VMXNET3_REV_3 + 1;
 293         } else if (ver & (1 << VMXNET3_REV_2)) {
 294                 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_VRRS,
 295                                        1 << VMXNET3_REV_2);
 296                 hw->version = VMXNET3_REV_2 + 1;
 297         } else if (ver & (1 << VMXNET3_REV_1)) {
 298                 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_VRRS,
 299                                        1 << VMXNET3_REV_1);
 300                 hw->version = VMXNET3_REV_1 + 1;
 301         } else {
 302                 PMD_INIT_LOG(ERR, "Incompatible hardware version: %d", ver);
 303                 return -EIO;
 304         }
 305
 306         PMD_INIT_LOG(DEBUG, "Using device version %d\n", hw->version);
 307
 308         /* Check UPT version compatibility with driver. */
 309         ver = VMXNET3_READ_BAR1_REG(hw, VMXNET3_REG_UVRS);
 310         PMD_INIT_LOG(DEBUG, "UPT hardware version : %d", ver);
 311         if (ver & 0x1)
 312                 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_UVRS, 1);
 313         else {
 314                 PMD_INIT_LOG(ERR, "Incompatible UPT version.");
 315                 return -EIO;
 316         }
 317
 318         /* Getting MAC Address */
 319         mac_lo = VMXNET3_READ_BAR1_REG(hw, VMXNET3_REG_MACL);
 320         mac_hi = VMXNET3_READ_BAR1_REG(hw, VMXNET3_REG_MACH);
 321         memcpy(hw->perm_addr, &mac_lo, 4);
 322         memcpy(hw->perm_addr + 4, &mac_hi, 2);
 323
 324         /* Allocate memory for storing MAC addresses */
 325         eth_dev->data->mac_addrs = rte_zmalloc("vmxnet3", ETHER_ADDR_LEN *
 326                                                VMXNET3_MAX_MAC_ADDRS, 0);
 327         if (eth_dev->data->mac_addrs == NULL) {
 328                 PMD_INIT_LOG(ERR,
 329                              "Failed to allocate %d bytes needed to store MAC addresses",
 330                              ETHER_ADDR_LEN * VMXNET3_MAX_MAC_ADDRS);
 331                 return -ENOMEM;
 332         }
 333         /* Copy the permanent MAC address */
 334         ether_addr_copy((struct ether_addr *) hw->perm_addr,
 335                         &eth_dev->data->mac_addrs[0]);
 336
 337         PMD_INIT_LOG(DEBUG, "MAC Address : %02x:%02x:%02x:%02x:%02x:%02x",
 338                      hw->perm_addr[0], hw->perm_addr[1], hw->perm_addr[2],
 339                      hw->perm_addr[3], hw->perm_addr[4], hw->perm_addr[5]);
 340
 341         /* Put device in Quiesce Mode */
 342         VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, VMXNET3_CMD_QUIESCE_DEV);
 343
 344         /* allow untagged pkts */
 345         VMXNET3_SET_VFTABLE_ENTRY(hw->shadow_vfta, 0);
 346
 347         hw->txdata_desc_size = VMXNET3_VERSION_GE_3(hw) ?
 348                 eth_vmxnet3_txdata_get(hw) : sizeof(struct Vmxnet3_TxDataDesc);
 349
 350         hw->rxdata_desc_size = VMXNET3_VERSION_GE_3(hw) ?
 351                 VMXNET3_DEF_RXDATA_DESC_SIZE : 0;
 352         RTE_ASSERT((hw->rxdata_desc_size & ~VMXNET3_RXDATA_DESC_SIZE_MASK) ==
 353                    hw->rxdata_desc_size);
 354
 355         /* clear shadow stats */
 356         memset(hw->saved_tx_stats, 0, sizeof(hw->saved_tx_stats));
 357         memset(hw->saved_rx_stats, 0, sizeof(hw->saved_rx_stats));
 358
 359         return 0;
 360 }
 361
 362 static int
 363 eth_vmxnet3_dev_uninit(struct rte_eth_dev *eth_dev)
 364 {
 365         struct vmxnet3_hw *hw = eth_dev->data->dev_private;
 366
 367         PMD_INIT_FUNC_TRACE();
 368
 369         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
 370                 return 0;
 371
 372         if (hw->adapter_stopped == 0)
 373                 vmxnet3_dev_close(eth_dev);
 374
 375         eth_dev->dev_ops = NULL;
 376         eth_dev->rx_pkt_burst = NULL;
 377         eth_dev->tx_pkt_burst = NULL;
 378         eth_dev->tx_pkt_prepare = NULL;
 379
 380         rte_free(eth_dev->data->mac_addrs);
 381         eth_dev->data->mac_addrs = NULL;
 382
 383         return 0;
 384 }
 385
 386 static int eth_vmxnet3_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
 387         struct rte_pci_device *pci_dev)
 388 {
 389         return rte_eth_dev_pci_generic_probe(pci_dev,
 390                 sizeof(struct vmxnet3_hw), eth_vmxnet3_dev_init);
 391 }
 392
 393 static int eth_vmxnet3_pci_remove(struct rte_pci_device *pci_dev)
 394 {
 395         return rte_eth_dev_pci_generic_remove(pci_dev, eth_vmxnet3_dev_uninit);
 396 }
 397
 398 static struct rte_pci_driver rte_vmxnet3_pmd = {
 399         .id_table = pci_id_vmxnet3_map,
 400         .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
 401         .probe = eth_vmxnet3_pci_probe,
 402         .remove = eth_vmxnet3_pci_remove,
 403 };
 404
 405 static int
 406 vmxnet3_dev_configure(struct rte_eth_dev *dev)
 407 {
 408         const struct rte_memzone *mz;
 409         struct vmxnet3_hw *hw = dev->data->dev_private;
 410         size_t size;
 411
 412         PMD_INIT_FUNC_TRACE();
 413
 414         if (dev->data->nb_tx_queues > VMXNET3_MAX_TX_QUEUES ||
 415             dev->data->nb_rx_queues > VMXNET3_MAX_RX_QUEUES) {
 416                 PMD_INIT_LOG(ERR, "ERROR: Number of queues not supported");
 417                 return -EINVAL;
 418         }
 419
 420         if (!rte_is_power_of_2(dev->data->nb_rx_queues)) {
 421                 PMD_INIT_LOG(ERR, "ERROR: Number of rx queues not power of 2");
 422                 return -EINVAL;
 423         }
 424
 425         size = dev->data->nb_rx_queues * sizeof(struct Vmxnet3_TxQueueDesc) +
 426                 dev->data->nb_tx_queues * sizeof(struct Vmxnet3_RxQueueDesc);
 427
 428         if (size > UINT16_MAX)
 429                 return -EINVAL;
 430
 431         hw->num_rx_queues = (uint8_t)dev->data->nb_rx_queues;
 432         hw->num_tx_queues = (uint8_t)dev->data->nb_tx_queues;
 433
 434         /*
 435          * Allocate a memzone for Vmxnet3_DriverShared - Vmxnet3_DSDevRead
 436          * on current socket
 437          */
 438         mz = gpa_zone_reserve(dev, sizeof(struct Vmxnet3_DriverShared),
 439                               "shared", rte_socket_id(), 8, 1);
 440
 441         if (mz == NULL) {
 442                 PMD_INIT_LOG(ERR, "ERROR: Creating shared zone");
 443                 return -ENOMEM;
 444         }
 445         memset(mz->addr, 0, mz->len);
 446
 447         hw->shared = mz->addr;
 448         hw->sharedPA = mz->phys_addr;
 449
 450         /*
 451          * Allocate a memzone for Vmxnet3_RxQueueDesc - Vmxnet3_TxQueueDesc
 452          * on current socket.
 453          *
 454          * We cannot reuse this memzone from previous allocation as its size
 455          * depends on the number of tx and rx queues, which could be different
 456          * from one config to another.
 457          */
 458         mz = gpa_zone_reserve(dev, size, "queuedesc", rte_socket_id(),
 459                               VMXNET3_QUEUE_DESC_ALIGN, 0);
 460         if (mz == NULL) {
 461                 PMD_INIT_LOG(ERR, "ERROR: Creating queue descriptors zone");
 462                 return -ENOMEM;
 463         }
 464         memset(mz->addr, 0, mz->len);
 465
 466         hw->tqd_start = (Vmxnet3_TxQueueDesc *)mz->addr;
 467         hw->rqd_start = (Vmxnet3_RxQueueDesc *)(hw->tqd_start + hw->num_tx_queues);
 468
 469         hw->queueDescPA = mz->phys_addr;
 470         hw->queue_desc_len = (uint16_t)size;
 471
 472         if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_RSS) {
 473                 /* Allocate memory structure for UPT1_RSSConf and configure */
 474                 mz = gpa_zone_reserve(dev, sizeof(struct VMXNET3_RSSConf),
 475                                       "rss_conf", rte_socket_id(),
 476                                       RTE_CACHE_LINE_SIZE, 1);
 477                 if (mz == NULL) {
 478                         PMD_INIT_LOG(ERR,
 479                                      "ERROR: Creating rss_conf structure zone");
 480                         return -ENOMEM;
 481                 }
 482                 memset(mz->addr, 0, mz->len);
 483
 484                 hw->rss_conf = mz->addr;
 485                 hw->rss_confPA = mz->phys_addr;
 486         }
 487
 488         return 0;
 489 }
 490
 491 static void
 492 vmxnet3_write_mac(struct vmxnet3_hw *hw, const uint8_t *addr)
 493 {
 494         uint32_t val;
 495
 496         PMD_INIT_LOG(DEBUG,
 497                      "Writing MAC Address : %02x:%02x:%02x:%02x:%02x:%02x",
 498                      addr[0], addr[1], addr[2],
 499                      addr[3], addr[4], addr[5]);
 500
 501         val = *(const uint32_t *)addr;
 502         VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_MACL, val);
 503
 504         val = (addr[5] << 8) | addr[4];
 505         VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_MACH, val);
 506 }
 507
 508 static int
 509 vmxnet3_dev_setup_memreg(struct rte_eth_dev *dev)
 510 {
 511         struct vmxnet3_hw *hw = dev->data->dev_private;
 512         Vmxnet3_DriverShared *shared = hw->shared;
 513         Vmxnet3_CmdInfo *cmdInfo;
 514         struct rte_mempool *mp[VMXNET3_MAX_RX_QUEUES];
 515         uint8_t index[VMXNET3_MAX_RX_QUEUES + VMXNET3_MAX_TX_QUEUES];
 516         uint32_t num, i, j, size;
 517
 518         if (hw->memRegsPA == 0) {
 519                 const struct rte_memzone *mz;
 520
 521                 size = sizeof(Vmxnet3_MemRegs) +
 522                         (VMXNET3_MAX_RX_QUEUES + VMXNET3_MAX_TX_QUEUES) *
 523                         sizeof(Vmxnet3_MemoryRegion);
 524
 525                 mz = gpa_zone_reserve(dev, size, "memRegs", rte_socket_id(), 8,
 526                                       1);
 527                 if (mz == NULL) {
 528                         PMD_INIT_LOG(ERR, "ERROR: Creating memRegs zone");
 529                         return -ENOMEM;
 530                 }
 531                 memset(mz->addr, 0, mz->len);
 532                 hw->memRegs = mz->addr;
 533                 hw->memRegsPA = mz->phys_addr;
 534         }
 535
 536         num = hw->num_rx_queues;
 537
 538         for (i = 0; i < num; i++) {
 539                 vmxnet3_rx_queue_t *rxq = dev->data->rx_queues[i];
 540
 541                 mp[i] = rxq->mp;
 542                 index[i] = 1 << i;
 543         }
 544
 545         /*
 546          * The same mempool could be used by multiple queues. In such a case,
 547          * remove duplicate mempool entries. Only one entry is kept with
 548          * bitmask indicating queues that are using this mempool.
 549          */
 550         for (i = 1; i < num; i++) {
 551                 for (j = 0; j < i; j++) {
 552                         if (mp[i] == mp[j]) {
 553                                 mp[i] = NULL;
 554                                 index[j] |= 1 << i;
 555                                 break;
 556                         }
 557                 }
 558         }
 559
 560         j = 0;
 561         for (i = 0; i < num; i++) {
 562                 if (mp[i] == NULL)
 563                         continue;
 564
 565                 Vmxnet3_MemoryRegion *mr = &hw->memRegs->memRegs[j];
 566
 567                 mr->startPA =
 568                         (uintptr_t)STAILQ_FIRST(&mp[i]->mem_list)->phys_addr;
 569                 mr->length = STAILQ_FIRST(&mp[i]->mem_list)->len <= INT32_MAX ?
 570                         STAILQ_FIRST(&mp[i]->mem_list)->len : INT32_MAX;
 571                 mr->txQueueBits = index[i];
 572                 mr->rxQueueBits = index[i];
 573
 574                 PMD_INIT_LOG(INFO,
 575                              "index: %u startPA: %" PRIu64 " length: %u, "
 576                              "rxBits: %x",
 577                              j, mr->startPA, mr->length, mr->rxQueueBits);
 578                 j++;
 579         }
 580         hw->memRegs->numRegs = j;
 581         PMD_INIT_LOG(INFO, "numRegs: %u", j);
 582
 583         size = sizeof(Vmxnet3_MemRegs) +
 584                 (j - 1) * sizeof(Vmxnet3_MemoryRegion);
 585
 586         cmdInfo = &shared->cu.cmdInfo;
 587         cmdInfo->varConf.confVer = 1;
 588         cmdInfo->varConf.confLen = size;
 589         cmdInfo->varConf.confPA = hw->memRegsPA;
 590
 591         return 0;
 592 }
 593
 594 static int
 595 vmxnet3_setup_driver_shared(struct rte_eth_dev *dev)
 596 {
 597         struct rte_eth_conf port_conf = dev->data->dev_conf;
 598         struct vmxnet3_hw *hw = dev->data->dev_private;
 599         uint32_t mtu = dev->data->mtu;
 600         Vmxnet3_DriverShared *shared = hw->shared;
 601         Vmxnet3_DSDevRead *devRead = &shared->devRead;
 602         uint32_t i;
 603         int ret;
 604
 605         shared->magic = VMXNET3_REV1_MAGIC;
 606         devRead->misc.driverInfo.version = VMXNET3_DRIVER_VERSION_NUM;
 607
 608         /* Setting up Guest OS information */
 609         devRead->misc.driverInfo.gos.gosBits   = sizeof(void *) == 4 ?
 610                 VMXNET3_GOS_BITS_32 : VMXNET3_GOS_BITS_64;
 611         devRead->misc.driverInfo.gos.gosType   = VMXNET3_GOS_TYPE_LINUX;
 612         devRead->misc.driverInfo.vmxnet3RevSpt = 1;
 613         devRead->misc.driverInfo.uptVerSpt     = 1;
 614
 615         devRead->misc.mtu = rte_le_to_cpu_32(mtu);
 616         devRead->misc.queueDescPA  = hw->queueDescPA;
 617         devRead->misc.queueDescLen = hw->queue_desc_len;
 618         devRead->misc.numTxQueues  = hw->num_tx_queues;
 619         devRead->misc.numRxQueues  = hw->num_rx_queues;
 620
 621         /*
 622          * Set number of interrupts to 1
 623          * PMD disables all the interrupts but this is MUST to activate device
 624          * It needs at least one interrupt for link events to handle
 625          * So we'll disable it later after device activation if needed
 626          */
 627         devRead->intrConf.numIntrs = 1;
 628         devRead->intrConf.intrCtrl |= VMXNET3_IC_DISABLE_ALL;
 629
 630         for (i = 0; i < hw->num_tx_queues; i++) {
 631                 Vmxnet3_TxQueueDesc *tqd = &hw->tqd_start[i];
 632                 vmxnet3_tx_queue_t *txq  = dev->data->tx_queues[i];
 633
 634                 tqd->ctrl.txNumDeferred  = 0;
 635                 tqd->ctrl.txThreshold    = 1;
 636                 tqd->conf.txRingBasePA   = txq->cmd_ring.basePA;
 637                 tqd->conf.compRingBasePA = txq->comp_ring.basePA;
 638                 tqd->conf.dataRingBasePA = txq->data_ring.basePA;
 639
 640                 tqd->conf.txRingSize   = txq->cmd_ring.size;
 641                 tqd->conf.compRingSize = txq->comp_ring.size;
 642                 tqd->conf.dataRingSize = txq->data_ring.size;
 643                 tqd->conf.txDataRingDescSize = txq->txdata_desc_size;
 644                 tqd->conf.intrIdx      = txq->comp_ring.intr_idx;
 645                 tqd->status.stopped    = TRUE;
 646                 tqd->status.error      = 0;
 647                 memset(&tqd->stats, 0, sizeof(tqd->stats));
 648         }
 649
 650         for (i = 0; i < hw->num_rx_queues; i++) {
 651                 Vmxnet3_RxQueueDesc *rqd  = &hw->rqd_start[i];
 652                 vmxnet3_rx_queue_t *rxq   = dev->data->rx_queues[i];
 653
 654                 rqd->conf.rxRingBasePA[0] = rxq->cmd_ring[0].basePA;
 655                 rqd->conf.rxRingBasePA[1] = rxq->cmd_ring[1].basePA;
 656                 rqd->conf.compRingBasePA  = rxq->comp_ring.basePA;
 657
 658                 rqd->conf.rxRingSize[0]   = rxq->cmd_ring[0].size;
 659                 rqd->conf.rxRingSize[1]   = rxq->cmd_ring[1].size;
 660                 rqd->conf.compRingSize    = rxq->comp_ring.size;
 661                 rqd->conf.intrIdx         = rxq->comp_ring.intr_idx;
 662                 if (VMXNET3_VERSION_GE_3(hw)) {
 663                         rqd->conf.rxDataRingBasePA = rxq->data_ring.basePA;
 664                         rqd->conf.rxDataRingDescSize = rxq->data_desc_size;
 665                 }
 666                 rqd->status.stopped       = TRUE;
 667                 rqd->status.error         = 0;
 668                 memset(&rqd->stats, 0, sizeof(rqd->stats));
 669         }
 670
 671         /* RxMode set to 0 of VMXNET3_RXM_xxx */
 672         devRead->rxFilterConf.rxMode = 0;
 673
 674         /* Setting up feature flags */
 675         if (dev->data->dev_conf.rxmode.hw_ip_checksum)
 676                 devRead->misc.uptFeatures |= VMXNET3_F_RXCSUM;
 677
 678         if (dev->data->dev_conf.rxmode.enable_lro) {
 679                 devRead->misc.uptFeatures |= VMXNET3_F_LRO;
 680                 devRead->misc.maxNumRxSG = 0;
 681         }
 682
 683         if (port_conf.rxmode.mq_mode == ETH_MQ_RX_RSS) {
 684                 ret = vmxnet3_rss_configure(dev);
 685                 if (ret != VMXNET3_SUCCESS)
 686                         return ret;
 687
 688                 devRead->misc.uptFeatures |= VMXNET3_F_RSS;
 689                 devRead->rssConfDesc.confVer = 1;
 690                 devRead->rssConfDesc.confLen = sizeof(struct VMXNET3_RSSConf);
 691                 devRead->rssConfDesc.confPA  = hw->rss_confPA;
 692         }
 693
 694         vmxnet3_dev_vlan_offload_set(dev,
 695                                      ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK);
 696
 697         vmxnet3_write_mac(hw, hw->perm_addr);
 698
 699         return VMXNET3_SUCCESS;
 700 }
 701
 702 /*
 703  * Configure device link speed and setup link.
 704  * Must be called after eth_vmxnet3_dev_init. Other wise it might fail
 705  * It returns 0 on success.
 706  */
 707 static int
 708 vmxnet3_dev_start(struct rte_eth_dev *dev)
 709 {
 710         int ret;
 711         struct vmxnet3_hw *hw = dev->data->dev_private;
 712
 713         PMD_INIT_FUNC_TRACE();
 714
 715         /* Save stats before it is reset by CMD_ACTIVATE */
 716         vmxnet3_hw_stats_save(hw);
 717
 718         ret = vmxnet3_setup_driver_shared(dev);
 719         if (ret != VMXNET3_SUCCESS)
 720                 return ret;
 721
 722         /* Exchange shared data with device */
 723         VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_DSAL,
 724                                VMXNET3_GET_ADDR_LO(hw->sharedPA));
 725         VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_DSAH,
 726                                VMXNET3_GET_ADDR_HI(hw->sharedPA));
 727
 728         /* Activate device by register write */
 729         VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, VMXNET3_CMD_ACTIVATE_DEV);
 730         ret = VMXNET3_READ_BAR1_REG(hw, VMXNET3_REG_CMD);
 731
 732         if (ret != 0) {
 733                 PMD_INIT_LOG(ERR, "Device activation: UNSUCCESSFUL");
 734                 return -EINVAL;
 735         }
 736
 737         /* Setup memory region for rx buffers */
 738         ret = vmxnet3_dev_setup_memreg(dev);
 739         if (ret == 0) {
 740                 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD,
 741                                        VMXNET3_CMD_REGISTER_MEMREGS);
 742                 ret = VMXNET3_READ_BAR1_REG(hw, VMXNET3_REG_CMD);
 743                 if (ret != 0)
 744                         PMD_INIT_LOG(DEBUG,
 745                                      "Failed in setup memory region cmd\n");
 746                 ret = 0;
 747         } else {
 748                 PMD_INIT_LOG(DEBUG, "Failed to setup memory region\n");
 749         }
 750
 751         /* Disable interrupts */
 752         vmxnet3_disable_intr(hw);
 753
 754         /*
 755          * Load RX queues with blank mbufs and update next2fill index for device
 756          * Update RxMode of the device
 757          */
 758         ret = vmxnet3_dev_rxtx_init(dev);
 759         if (ret != VMXNET3_SUCCESS) {
 760                 PMD_INIT_LOG(ERR, "Device queue init: UNSUCCESSFUL");
 761                 return ret;
 762         }
 763
 764         hw->adapter_stopped = FALSE;
 765
 766         /* Setting proper Rx Mode and issue Rx Mode Update command */
 767         vmxnet3_dev_set_rxmode(hw, VMXNET3_RXM_UCAST | VMXNET3_RXM_BCAST, 1);
 768
 769         /*
 770          * Don't need to handle events for now
 771          */
 772 #if PROCESS_SYS_EVENTS == 1
 773         events = VMXNET3_READ_BAR1_REG(hw, VMXNET3_REG_ECR);
 774         PMD_INIT_LOG(DEBUG, "Reading events: 0x%X", events);
 775         vmxnet3_process_events(hw);
 776 #endif
 777         return VMXNET3_SUCCESS;
 778 }
 779
 780 /*
 781  * Stop device: disable rx and tx functions to allow for reconfiguring.
 782  */
 783 static void
 784 vmxnet3_dev_stop(struct rte_eth_dev *dev)
 785 {
 786         struct rte_eth_link link;
 787         struct vmxnet3_hw *hw = dev->data->dev_private;
 788
 789         PMD_INIT_FUNC_TRACE();
 790
 791         if (hw->adapter_stopped == 1) {
 792                 PMD_INIT_LOG(DEBUG, "Device already closed.");
 793                 return;
 794         }
 795
 796         /* disable interrupts */
 797         vmxnet3_disable_intr(hw);
 798
 799         /* quiesce the device first */
 800         VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, VMXNET3_CMD_QUIESCE_DEV);
 801         VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_DSAL, 0);
 802         VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_DSAH, 0);
 803
 804         /* reset the device */
 805         VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, VMXNET3_CMD_RESET_DEV);
 806         PMD_INIT_LOG(DEBUG, "Device reset.");
 807         hw->adapter_stopped = 0;
 808
 809         vmxnet3_dev_clear_queues(dev);
 810
 811         /* Clear recorded link status */
 812         memset(&link, 0, sizeof(link));
 813         vmxnet3_dev_atomic_write_link_status(dev, &link);
 814 }
 815
 816 /*
 817  * Reset and stop device.
 818  */
 819 static void
 820 vmxnet3_dev_close(struct rte_eth_dev *dev)
 821 {
 822         struct vmxnet3_hw *hw = dev->data->dev_private;
 823
 824         PMD_INIT_FUNC_TRACE();
 825
 826         vmxnet3_dev_stop(dev);
 827         hw->adapter_stopped = 1;
 828 }
 829
 830 static void
 831 vmxnet3_hw_tx_stats_get(struct vmxnet3_hw *hw, unsigned int q,
 832                         struct UPT1_TxStats *res)
 833 {
 834 #define VMXNET3_UPDATE_TX_STAT(h, i, f, r)              \
 835                 ((r)->f = (h)->tqd_start[(i)].stats.f + \
 836                         (h)->saved_tx_stats[(i)].f)
 837
 838         VMXNET3_UPDATE_TX_STAT(hw, q, ucastPktsTxOK, res);
 839         VMXNET3_UPDATE_TX_STAT(hw, q, mcastPktsTxOK, res);
 840         VMXNET3_UPDATE_TX_STAT(hw, q, bcastPktsTxOK, res);
 841         VMXNET3_UPDATE_TX_STAT(hw, q, ucastBytesTxOK, res);
 842         VMXNET3_UPDATE_TX_STAT(hw, q, mcastBytesTxOK, res);
 843         VMXNET3_UPDATE_TX_STAT(hw, q, bcastBytesTxOK, res);
 844         VMXNET3_UPDATE_TX_STAT(hw, q, pktsTxError, res);
 845         VMXNET3_UPDATE_TX_STAT(hw, q, pktsTxDiscard, res);
 846
 847 #undef VMXNET3_UPDATE_TX_STAT
 848 }
 849
 850 static void
 851 vmxnet3_hw_rx_stats_get(struct vmxnet3_hw *hw, unsigned int q,
 852                         struct UPT1_RxStats *res)
 853 {
 854 #define VMXNET3_UPDATE_RX_STAT(h, i, f, r)              \
 855                 ((r)->f = (h)->rqd_start[(i)].stats.f + \
 856                         (h)->saved_rx_stats[(i)].f)
 857
 858         VMXNET3_UPDATE_RX_STAT(hw, q, ucastPktsRxOK, res);
 859         VMXNET3_UPDATE_RX_STAT(hw, q, mcastPktsRxOK, res);
 860         VMXNET3_UPDATE_RX_STAT(hw, q, bcastPktsRxOK, res);
 861         VMXNET3_UPDATE_RX_STAT(hw, q, ucastBytesRxOK, res);
 862         VMXNET3_UPDATE_RX_STAT(hw, q, mcastBytesRxOK, res);
 863         VMXNET3_UPDATE_RX_STAT(hw, q, bcastBytesRxOK, res);
 864         VMXNET3_UPDATE_RX_STAT(hw, q, pktsRxError, res);
 865         VMXNET3_UPDATE_RX_STAT(hw, q, pktsRxOutOfBuf, res);
 866
 867 #undef VMXNET3_UPDATE_RX_STATS
 868 }
 869
 870 static void
 871 vmxnet3_hw_stats_save(struct vmxnet3_hw *hw)
 872 {
 873         unsigned int i;
 874
 875         VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, VMXNET3_CMD_GET_STATS);
 876
 877         RTE_BUILD_BUG_ON(RTE_ETHDEV_QUEUE_STAT_CNTRS < VMXNET3_MAX_TX_QUEUES);
 878
 879         for (i = 0; i < hw->num_tx_queues; i++)
 880                 vmxnet3_hw_tx_stats_get(hw, i, &hw->saved_tx_stats[i]);
 881         for (i = 0; i < hw->num_rx_queues; i++)
 882                 vmxnet3_hw_rx_stats_get(hw, i, &hw->saved_rx_stats[i]);
 883 }
 884
 885 static void
 886 vmxnet3_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
 887 {
 888         unsigned int i;
 889         struct vmxnet3_hw *hw = dev->data->dev_private;
 890         struct UPT1_TxStats txStats;
 891         struct UPT1_RxStats rxStats;
 892
 893         VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, VMXNET3_CMD_GET_STATS);
 894
 895         RTE_BUILD_BUG_ON(RTE_ETHDEV_QUEUE_STAT_CNTRS < VMXNET3_MAX_TX_QUEUES);
 896         for (i = 0; i < hw->num_tx_queues; i++) {
 897                 vmxnet3_hw_tx_stats_get(hw, i, &txStats);
 898
 899                 stats->q_opackets[i] = txStats.ucastPktsTxOK +
 900                         txStats.mcastPktsTxOK +
 901                         txStats.bcastPktsTxOK;
 902
 903                 stats->q_obytes[i] = txStats.ucastBytesTxOK +
 904                         txStats.mcastBytesTxOK +
 905                         txStats.bcastBytesTxOK;
 906
 907                 stats->opackets += stats->q_opackets[i];
 908                 stats->obytes += stats->q_obytes[i];
 909                 stats->oerrors += txStats.pktsTxError + txStats.pktsTxDiscard;
 910         }
 911
 912         RTE_BUILD_BUG_ON(RTE_ETHDEV_QUEUE_STAT_CNTRS < VMXNET3_MAX_RX_QUEUES);
 913         for (i = 0; i < hw->num_rx_queues; i++) {
 914                 vmxnet3_hw_rx_stats_get(hw, i, &rxStats);
 915
 916                 stats->q_ipackets[i] = rxStats.ucastPktsRxOK +
 917                         rxStats.mcastPktsRxOK +
 918                         rxStats.bcastPktsRxOK;
 919
 920                 stats->q_ibytes[i] = rxStats.ucastBytesRxOK +
 921                         rxStats.mcastBytesRxOK +
 922                         rxStats.bcastBytesRxOK;
 923
 924                 stats->ipackets += stats->q_ipackets[i];
 925                 stats->ibytes += stats->q_ibytes[i];
 926
 927                 stats->q_errors[i] = rxStats.pktsRxError;
 928                 stats->ierrors += rxStats.pktsRxError;
 929                 stats->rx_nombuf += rxStats.pktsRxOutOfBuf;
 930         }
 931 }
 932
 933 static void
 934 vmxnet3_dev_info_get(struct rte_eth_dev *dev,
 935                      struct rte_eth_dev_info *dev_info)
 936 {
 937         dev_info->pci_dev = RTE_ETH_DEV_TO_PCI(dev);
 938
 939         dev_info->max_rx_queues = VMXNET3_MAX_RX_QUEUES;
 940         dev_info->max_tx_queues = VMXNET3_MAX_TX_QUEUES;
 941         dev_info->min_rx_bufsize = 1518 + RTE_PKTMBUF_HEADROOM;
 942         dev_info->max_rx_pktlen = 16384; /* includes CRC, cf MAXFRS register */
 943         dev_info->speed_capa = ETH_LINK_SPEED_10G;
 944         dev_info->max_mac_addrs = VMXNET3_MAX_MAC_ADDRS;
 945
 946         dev_info->default_txconf.txq_flags = ETH_TXQ_FLAGS_NOXSUMSCTP;
 947         dev_info->flow_type_rss_offloads = VMXNET3_RSS_OFFLOAD_ALL;
 948
 949         dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
 950                 .nb_max = VMXNET3_RX_RING_MAX_SIZE,
 951                 .nb_min = VMXNET3_DEF_RX_RING_SIZE,
 952                 .nb_align = 1,
 953         };
 954
 955         dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
 956                 .nb_max = VMXNET3_TX_RING_MAX_SIZE,
 957                 .nb_min = VMXNET3_DEF_TX_RING_SIZE,
 958                 .nb_align = 1,
 959                 .nb_seg_max = VMXNET3_TX_MAX_SEG,
 960                 .nb_mtu_seg_max = VMXNET3_MAX_TXD_PER_PKT,
 961         };
 962
 963         dev_info->rx_offload_capa =
 964                 DEV_RX_OFFLOAD_VLAN_STRIP |
 965                 DEV_RX_OFFLOAD_UDP_CKSUM |
 966                 DEV_RX_OFFLOAD_TCP_CKSUM |
 967                 DEV_RX_OFFLOAD_TCP_LRO;
 968
 969         dev_info->tx_offload_capa =
 970                 DEV_TX_OFFLOAD_VLAN_INSERT |
 971                 DEV_TX_OFFLOAD_TCP_CKSUM |
 972                 DEV_TX_OFFLOAD_UDP_CKSUM |
 973                 DEV_TX_OFFLOAD_TCP_TSO;
 974 }
 975
 976 static const uint32_t *
 977 vmxnet3_dev_supported_ptypes_get(struct rte_eth_dev *dev)
 978 {
 979         static const uint32_t ptypes[] = {
 980                 RTE_PTYPE_L3_IPV4_EXT,
 981                 RTE_PTYPE_L3_IPV4,
 982                 RTE_PTYPE_UNKNOWN
 983         };
 984
 985         if (dev->rx_pkt_burst == vmxnet3_recv_pkts)
 986                 return ptypes;
 987         return NULL;
 988 }
 989
 990 static void
 991 vmxnet3_mac_addr_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr)
 992 {
 993         struct vmxnet3_hw *hw = dev->data->dev_private;
 994
 995         vmxnet3_write_mac(hw, mac_addr->addr_bytes);
 996 }
 997
 998 /* return 0 means link status changed, -1 means not changed */
 999 static int
1000 vmxnet3_dev_link_update(struct rte_eth_dev *dev,
1001                         __rte_unused int wait_to_complete)
1002 {
1003         struct vmxnet3_hw *hw = dev->data->dev_private;
1004         struct rte_eth_link old = { 0 }, link;
1005         uint32_t ret;
1006
1007         /* Link status doesn't change for stopped dev */
1008         if (dev->data->dev_started == 0)
1009                 return -1;
1010
1011         memset(&link, 0, sizeof(link));
1012         vmxnet3_dev_atomic_read_link_status(dev, &old);
1013
1014         VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, VMXNET3_CMD_GET_LINK);
1015         ret = VMXNET3_READ_BAR1_REG(hw, VMXNET3_REG_CMD);
1016
1017         if (ret & 0x1) {
1018                 link.link_status = ETH_LINK_UP;
1019                 link.link_duplex = ETH_LINK_FULL_DUPLEX;
1020                 link.link_speed = ETH_SPEED_NUM_10G;
1021                 link.link_autoneg = ETH_LINK_SPEED_FIXED;
1022         }
1023
1024         vmxnet3_dev_atomic_write_link_status(dev, &link);
1025
1026         return (old.link_status == link.link_status) ? -1 : 0;
1027 }
1028
1029 /* Updating rxmode through Vmxnet3_DriverShared structure in adapter */
1030 static void
1031 vmxnet3_dev_set_rxmode(struct vmxnet3_hw *hw, uint32_t feature, int set)
1032 {
1033         struct Vmxnet3_RxFilterConf *rxConf = &hw->shared->devRead.rxFilterConf;
1034
1035         if (set)
1036                 rxConf->rxMode = rxConf->rxMode | feature;
1037         else
1038                 rxConf->rxMode = rxConf->rxMode & (~feature);
1039
1040         VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, VMXNET3_CMD_UPDATE_RX_MODE);
1041 }
1042
1043 /* Promiscuous supported only if Vmxnet3_DriverShared is initialized in adapter */
1044 static void
1045 vmxnet3_dev_promiscuous_enable(struct rte_eth_dev *dev)
1046 {
1047         struct vmxnet3_hw *hw = dev->data->dev_private;
1048         uint32_t *vf_table = hw->shared->devRead.rxFilterConf.vfTable;
1049
1050         memset(vf_table, 0, VMXNET3_VFT_TABLE_SIZE);
1051         vmxnet3_dev_set_rxmode(hw, VMXNET3_RXM_PROMISC, 1);
1052
1053         VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD,
1054                                VMXNET3_CMD_UPDATE_VLAN_FILTERS);
1055 }
1056
1057 /* Promiscuous supported only if Vmxnet3_DriverShared is initialized in adapter */
1058 static void
1059 vmxnet3_dev_promiscuous_disable(struct rte_eth_dev *dev)
1060 {
1061         struct vmxnet3_hw *hw = dev->data->dev_private;
1062         uint32_t *vf_table = hw->shared->devRead.rxFilterConf.vfTable;
1063
1064         memcpy(vf_table, hw->shadow_vfta, VMXNET3_VFT_TABLE_SIZE);
1065         vmxnet3_dev_set_rxmode(hw, VMXNET3_RXM_PROMISC, 0);
1066         VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD,
1067                                VMXNET3_CMD_UPDATE_VLAN_FILTERS);
1068 }
1069
1070 /* Allmulticast supported only if Vmxnet3_DriverShared is initialized in adapter */
1071 static void
1072 vmxnet3_dev_allmulticast_enable(struct rte_eth_dev *dev)
1073 {
1074         struct vmxnet3_hw *hw = dev->data->dev_private;
1075
1076         vmxnet3_dev_set_rxmode(hw, VMXNET3_RXM_ALL_MULTI, 1);
1077 }
1078
1079 /* Allmulticast supported only if Vmxnet3_DriverShared is initialized in adapter */
1080 static void
1081 vmxnet3_dev_allmulticast_disable(struct rte_eth_dev *dev)
1082 {
1083         struct vmxnet3_hw *hw = dev->data->dev_private;
1084
1085         vmxnet3_dev_set_rxmode(hw, VMXNET3_RXM_ALL_MULTI, 0);
1086 }
1087
1088 /* Enable/disable filter on vlan */
1089 static int
1090 vmxnet3_dev_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vid, int on)
1091 {
1092         struct vmxnet3_hw *hw = dev->data->dev_private;
1093         struct Vmxnet3_RxFilterConf *rxConf = &hw->shared->devRead.rxFilterConf;
1094         uint32_t *vf_table = rxConf->vfTable;
1095
1096         /* save state for restore */
1097         if (on)
1098                 VMXNET3_SET_VFTABLE_ENTRY(hw->shadow_vfta, vid);
1099         else
1100                 VMXNET3_CLEAR_VFTABLE_ENTRY(hw->shadow_vfta, vid);
1101
1102         /* don't change active filter if in promiscuous mode */
1103         if (rxConf->rxMode & VMXNET3_RXM_PROMISC)
1104                 return 0;
1105
1106         /* set in hardware */
1107         if (on)
1108                 VMXNET3_SET_VFTABLE_ENTRY(vf_table, vid);
1109         else
1110                 VMXNET3_CLEAR_VFTABLE_ENTRY(vf_table, vid);
1111
1112         VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD,
1113                                VMXNET3_CMD_UPDATE_VLAN_FILTERS);
1114         return 0;
1115 }
1116
1117 static void
1118 vmxnet3_dev_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1119 {
1120         struct vmxnet3_hw *hw = dev->data->dev_private;
1121         Vmxnet3_DSDevRead *devRead = &hw->shared->devRead;
1122         uint32_t *vf_table = devRead->rxFilterConf.vfTable;
1123
1124         if (mask & ETH_VLAN_STRIP_MASK) {
1125                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
1126                         devRead->misc.uptFeatures |= UPT1_F_RXVLAN;
1127                 else
1128                         devRead->misc.uptFeatures &= ~UPT1_F_RXVLAN;
1129
1130                 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD,
1131                                        VMXNET3_CMD_UPDATE_FEATURE);
1132         }
1133
1134         if (mask & ETH_VLAN_FILTER_MASK) {
1135                 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
1136                         memcpy(vf_table, hw->shadow_vfta, VMXNET3_VFT_TABLE_SIZE);
1137                 else
1138                         memset(vf_table, 0xff, VMXNET3_VFT_TABLE_SIZE);
1139
1140                 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD,
1141                                        VMXNET3_CMD_UPDATE_VLAN_FILTERS);
1142         }
1143 }
1144
1145 #if PROCESS_SYS_EVENTS == 1
1146 static void
1147 vmxnet3_process_events(struct vmxnet3_hw *hw)
1148 {
1149         uint32_t events = hw->shared->ecr;
1150
1151         if (!events) {
1152                 PMD_INIT_LOG(ERR, "No events to process");
1153                 return;
1154         }
1155
1156         /*
1157          * ECR bits when written with 1b are cleared. Hence write
1158          * events back to ECR so that the bits which were set will be reset.
1159          */
1160         VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_ECR, events);
1161
1162         /* Check if link state has changed */
1163         if (events & VMXNET3_ECR_LINK)
1164                 PMD_INIT_LOG(ERR,
1165                              "Process events in %s(): VMXNET3_ECR_LINK event",
1166                              __func__);
1167
1168         /* Check if there is an error on xmit/recv queues */
1169         if (events & (VMXNET3_ECR_TQERR | VMXNET3_ECR_RQERR)) {
1170                 VMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD,
1171                                        VMXNET3_CMD_GET_QUEUE_STATUS);
1172
1173                 if (hw->tqd_start->status.stopped)
1174                         PMD_INIT_LOG(ERR, "tq error 0x%x",
1175                                      hw->tqd_start->status.error);
1176
1177                 if (hw->rqd_start->status.stopped)
1178                         PMD_INIT_LOG(ERR, "rq error 0x%x",
1179                                      hw->rqd_start->status.error);
1180
1181                 /* Reset the device */
1182                 /* Have to reset the device */
1183         }
1184
1185         if (events & VMXNET3_ECR_DIC)
1186                 PMD_INIT_LOG(ERR, "Device implementation change event.");
1187
1188         if (events & VMXNET3_ECR_DEBUG)
1189                 PMD_INIT_LOG(ERR, "Debug event generated by device.");
1190 }
1191 #endif
1192
1193 RTE_PMD_REGISTER_PCI(net_vmxnet3, rte_vmxnet3_pmd);
1194 RTE_PMD_REGISTER_PCI_TABLE(net_vmxnet3, pci_id_vmxnet3_map);
1195 RTE_PMD_REGISTER_KMOD_DEP(net_vmxnet3, "* igb_uio | uio_pci_generic | vfio-pci");