1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2010-2014 Intel Corporation
5 #ifndef _VMXNET3_ETHDEV_H_
6 #define _VMXNET3_ETHDEV_H_
10 #define VMXNET3_MAX_MAC_ADDRS 1
12 /* UPT feature to negotiate */
13 #define VMXNET3_F_RXCSUM 0x0001
14 #define VMXNET3_F_RSS 0x0002
15 #define VMXNET3_F_RXVLAN 0x0004
16 #define VMXNET3_F_LRO 0x0008
18 /* Hash Types supported by device */
19 #define VMXNET3_RSS_HASH_TYPE_NONE 0x0
20 #define VMXNET3_RSS_HASH_TYPE_IPV4 0x01
21 #define VMXNET3_RSS_HASH_TYPE_TCP_IPV4 0x02
22 #define VMXNET3_RSS_HASH_TYPE_IPV6 0x04
23 #define VMXNET3_RSS_HASH_TYPE_TCP_IPV6 0x08
25 #define VMXNET3_RSS_HASH_FUNC_NONE 0x0
26 #define VMXNET3_RSS_HASH_FUNC_TOEPLITZ 0x01
28 #define VMXNET3_RSS_MAX_KEY_SIZE 40
29 #define VMXNET3_RSS_MAX_IND_TABLE_SIZE 128
31 #define VMXNET3_RSS_OFFLOAD_ALL ( \
33 ETH_RSS_NONFRAG_IPV4_TCP | \
35 ETH_RSS_NONFRAG_IPV6_TCP)
37 #define VMXNET3_V4_RSS_MASK ( \
38 ETH_RSS_NONFRAG_IPV4_UDP | \
39 ETH_RSS_NONFRAG_IPV6_UDP)
41 #define VMXNET3_MANDATORY_V4_RSS ( \
42 ETH_RSS_NONFRAG_IPV4_TCP | \
43 ETH_RSS_NONFRAG_IPV6_TCP)
45 /* RSS configuration structure - shared with device through GPA */
46 typedef struct VMXNET3_RSSConf {
50 uint16_t indTableSize;
51 uint8_t hashKey[VMXNET3_RSS_MAX_KEY_SIZE];
53 * indTable is only element that can be changed without
54 * device quiesce-reset-update-activation cycle
56 uint8_t indTable[VMXNET3_RSS_MAX_IND_TABLE_SIZE];
59 typedef struct vmxnet3_mf_table {
60 void *mfTableBase; /* Multicast addresses list */
61 uint64_t mfTablePA; /* Physical address of the list */
62 uint16_t num_addrs; /* number of multicast addrs */
66 uint8_t *hw_addr0; /* BAR0: PT-Passthrough Regs */
67 uint8_t *hw_addr1; /* BAR1: VD-Virtual Device Regs */
68 /* BAR2: MSI-X Regs */
74 uint16_t subsystem_device_id;
75 uint16_t subsystem_vendor_id;
78 uint8_t perm_addr[RTE_ETHER_ADDR_LEN];
79 uint8_t num_tx_queues;
80 uint8_t num_rx_queues;
85 uint16_t txdata_desc_size; /* tx data ring buffer size */
86 uint16_t rxdata_desc_size; /* rx data ring buffer size */
90 Vmxnet3_TxQueueDesc *tqd_start; /* start address of all tx queue desc */
91 Vmxnet3_RxQueueDesc *rqd_start; /* start address of all rx queue desc */
93 Vmxnet3_DriverShared *shared;
97 uint16_t queue_desc_len;
100 VMXNET3_RSSConf *rss_conf;
102 vmxnet3_mf_table_t *mf_table;
103 uint32_t shadow_vfta[VMXNET3_VFT_SIZE];
104 Vmxnet3_MemRegs *memRegs;
106 #define VMXNET3_VFT_TABLE_SIZE (VMXNET3_VFT_SIZE * sizeof(uint32_t))
107 UPT1_TxStats saved_tx_stats[VMXNET3_MAX_TX_QUEUES];
108 UPT1_RxStats saved_rx_stats[VMXNET3_MAX_RX_QUEUES];
110 UPT1_TxStats snapshot_tx_stats[VMXNET3_MAX_TX_QUEUES];
111 UPT1_RxStats snapshot_rx_stats[VMXNET3_MAX_RX_QUEUES];
114 #define VMXNET3_REV_4 3 /* Vmxnet3 Rev. 4 */
115 #define VMXNET3_REV_3 2 /* Vmxnet3 Rev. 3 */
116 #define VMXNET3_REV_2 1 /* Vmxnet3 Rev. 2 */
117 #define VMXNET3_REV_1 0 /* Vmxnet3 Rev. 1 */
119 #define VMXNET3_VERSION_GE_4(hw) ((hw)->version >= VMXNET3_REV_4 + 1)
120 #define VMXNET3_VERSION_GE_3(hw) ((hw)->version >= VMXNET3_REV_3 + 1)
121 #define VMXNET3_VERSION_GE_2(hw) ((hw)->version >= VMXNET3_REV_2 + 1)
123 #define VMXNET3_GET_ADDR_LO(reg) ((uint32_t)(reg))
124 #define VMXNET3_GET_ADDR_HI(reg) ((uint32_t)(((uint64_t)(reg)) >> 32))
126 /* Config space read/writes */
128 #define VMXNET3_PCI_REG(reg) rte_read32(reg)
130 static inline uint32_t
131 vmxnet3_read_addr(volatile void *addr)
133 return VMXNET3_PCI_REG(addr);
136 #define VMXNET3_PCI_REG_WRITE(reg, value) rte_write32((value), (reg))
138 #define VMXNET3_PCI_BAR0_REG_ADDR(hw, reg) \
139 ((volatile uint32_t *)((char *)(hw)->hw_addr0 + (reg)))
140 #define VMXNET3_READ_BAR0_REG(hw, reg) \
141 vmxnet3_read_addr(VMXNET3_PCI_BAR0_REG_ADDR((hw), (reg)))
142 #define VMXNET3_WRITE_BAR0_REG(hw, reg, value) \
143 VMXNET3_PCI_REG_WRITE(VMXNET3_PCI_BAR0_REG_ADDR((hw), (reg)), (value))
145 #define VMXNET3_PCI_BAR1_REG_ADDR(hw, reg) \
146 ((volatile uint32_t *)((char *)(hw)->hw_addr1 + (reg)))
147 #define VMXNET3_READ_BAR1_REG(hw, reg) \
148 vmxnet3_read_addr(VMXNET3_PCI_BAR1_REG_ADDR((hw), (reg)))
149 #define VMXNET3_WRITE_BAR1_REG(hw, reg, value) \
150 VMXNET3_PCI_REG_WRITE(VMXNET3_PCI_BAR1_REG_ADDR((hw), (reg)), (value))
152 static inline uint8_t
153 vmxnet3_get_ring_idx(struct vmxnet3_hw *hw, uint32 rqID)
155 return (rqID >= hw->num_rx_queues &&
156 rqID < 2 * hw->num_rx_queues) ? 1 : 0;
160 vmxnet3_rx_data_ring(struct vmxnet3_hw *hw, uint32 rqID)
162 return (rqID >= 2 * hw->num_rx_queues &&
163 rqID < 3 * hw->num_rx_queues);
167 * RX/TX function prototypes
170 void vmxnet3_dev_clear_queues(struct rte_eth_dev *dev);
172 void vmxnet3_dev_rx_queue_release(void *rxq);
173 void vmxnet3_dev_tx_queue_release(void *txq);
175 int vmxnet3_v4_rss_configure(struct rte_eth_dev *dev);
177 int vmxnet3_dev_rx_queue_setup(struct rte_eth_dev *dev, uint16_t rx_queue_id,
178 uint16_t nb_rx_desc, unsigned int socket_id,
179 const struct rte_eth_rxconf *rx_conf,
180 struct rte_mempool *mb_pool);
181 int vmxnet3_dev_tx_queue_setup(struct rte_eth_dev *dev, uint16_t tx_queue_id,
182 uint16_t nb_tx_desc, unsigned int socket_id,
183 const struct rte_eth_txconf *tx_conf);
185 int vmxnet3_dev_rxtx_init(struct rte_eth_dev *dev);
187 int vmxnet3_rss_configure(struct rte_eth_dev *dev);
189 uint16_t vmxnet3_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
191 uint16_t vmxnet3_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
193 uint16_t vmxnet3_prep_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
196 #endif /* _VMXNET3_ETHDEV_H_ */