4 * Copyright(c) 2010-2015 Intel Corporation. All rights reserved.
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8 * modification, are permitted provided that the following conditions
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14 * notice, this list of conditions and the following disclaimer in
15 * the documentation and/or other materials provided with the
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34 #include <sys/queue.h>
45 #include <rte_byteorder.h>
46 #include <rte_common.h>
47 #include <rte_cycles.h>
49 #include <rte_debug.h>
50 #include <rte_interrupts.h>
52 #include <rte_memory.h>
53 #include <rte_memzone.h>
54 #include <rte_launch.h>
56 #include <rte_per_lcore.h>
57 #include <rte_lcore.h>
58 #include <rte_atomic.h>
59 #include <rte_branch_prediction.h>
61 #include <rte_mempool.h>
62 #include <rte_malloc.h>
64 #include <rte_ether.h>
65 #include <rte_ethdev.h>
66 #include <rte_prefetch.h>
71 #include <rte_string_fns.h>
72 #include <rte_errno.h>
74 #include "base/vmxnet3_defs.h"
75 #include "vmxnet3_ring.h"
77 #include "vmxnet3_logs.h"
78 #include "vmxnet3_ethdev.h"
80 #define RTE_MBUF_DATA_DMA_ADDR(mb) \
81 (uint64_t) ((mb)->buf_physaddr + (mb)->data_off)
83 #define RTE_MBUF_DATA_DMA_ADDR_DEFAULT(mb) \
84 (uint64_t) ((mb)->buf_physaddr + RTE_PKTMBUF_HEADROOM)
86 static const uint32_t rxprod_reg[2] = {VMXNET3_REG_RXPROD, VMXNET3_REG_RXPROD2};
88 static int vmxnet3_post_rx_bufs(vmxnet3_rx_queue_t*, uint8_t);
89 static void vmxnet3_tq_tx_complete(vmxnet3_tx_queue_t *);
90 #ifdef RTE_LIBRTE_VMXNET3_DEBUG_DRIVER_NOT_USED
91 static void vmxnet3_rxq_dump(struct vmxnet3_rx_queue *);
92 static void vmxnet3_txq_dump(struct vmxnet3_tx_queue *);
95 static struct rte_mbuf *
96 rte_rxmbuf_alloc(struct rte_mempool *mp)
100 m = __rte_mbuf_raw_alloc(mp);
101 __rte_mbuf_sanity_check_raw(m, 0);
105 #ifdef RTE_LIBRTE_VMXNET3_DEBUG_DRIVER_NOT_USED
107 vmxnet3_rxq_dump(struct vmxnet3_rx_queue *rxq)
115 "RXQ: cmd0 base : 0x%p cmd1 base : 0x%p comp ring base : 0x%p.",
116 rxq->cmd_ring[0].base, rxq->cmd_ring[1].base, rxq->comp_ring.base);
118 "RXQ: cmd0 basePA : 0x%lx cmd1 basePA : 0x%lx comp ring basePA : 0x%lx.",
119 (unsigned long)rxq->cmd_ring[0].basePA,
120 (unsigned long)rxq->cmd_ring[1].basePA,
121 (unsigned long)rxq->comp_ring.basePA);
123 avail = vmxnet3_cmd_ring_desc_avail(&rxq->cmd_ring[0]);
125 "RXQ:cmd0: size=%u; free=%u; next2proc=%u; queued=%u",
126 (uint32_t)rxq->cmd_ring[0].size, avail,
127 rxq->comp_ring.next2proc,
128 rxq->cmd_ring[0].size - avail);
130 avail = vmxnet3_cmd_ring_desc_avail(&rxq->cmd_ring[1]);
131 PMD_RX_LOG(DEBUG, "RXQ:cmd1 size=%u; free=%u; next2proc=%u; queued=%u",
132 (uint32_t)rxq->cmd_ring[1].size, avail, rxq->comp_ring.next2proc,
133 rxq->cmd_ring[1].size - avail);
138 vmxnet3_txq_dump(struct vmxnet3_tx_queue *txq)
145 PMD_TX_LOG(DEBUG, "TXQ: cmd base : 0x%p comp ring base : 0x%p data ring base : 0x%p.",
146 txq->cmd_ring.base, txq->comp_ring.base, txq->data_ring.base);
147 PMD_TX_LOG(DEBUG, "TXQ: cmd basePA : 0x%lx comp ring basePA : 0x%lx data ring basePA : 0x%lx.",
148 (unsigned long)txq->cmd_ring.basePA,
149 (unsigned long)txq->comp_ring.basePA,
150 (unsigned long)txq->data_ring.basePA);
152 avail = vmxnet3_cmd_ring_desc_avail(&txq->cmd_ring);
153 PMD_TX_LOG(DEBUG, "TXQ: size=%u; free=%u; next2proc=%u; queued=%u",
154 (uint32_t)txq->cmd_ring.size, avail,
155 txq->comp_ring.next2proc, txq->cmd_ring.size - avail);
160 vmxnet3_cmd_ring_release_mbufs(vmxnet3_cmd_ring_t *ring)
162 while (ring->next2comp != ring->next2fill) {
163 /* No need to worry about tx desc ownership, device is quiesced by now. */
164 vmxnet3_buf_info_t *buf_info = ring->buf_info + ring->next2comp;
167 rte_pktmbuf_free(buf_info->m);
172 vmxnet3_cmd_ring_adv_next2comp(ring);
177 vmxnet3_cmd_ring_release(vmxnet3_cmd_ring_t *ring)
179 vmxnet3_cmd_ring_release_mbufs(ring);
180 rte_free(ring->buf_info);
181 ring->buf_info = NULL;
186 vmxnet3_dev_tx_queue_release(void *txq)
188 vmxnet3_tx_queue_t *tq = txq;
191 /* Release the cmd_ring */
192 vmxnet3_cmd_ring_release(&tq->cmd_ring);
197 vmxnet3_dev_rx_queue_release(void *rxq)
200 vmxnet3_rx_queue_t *rq = rxq;
203 /* Release both the cmd_rings */
204 for (i = 0; i < VMXNET3_RX_CMDRING_SIZE; i++)
205 vmxnet3_cmd_ring_release(&rq->cmd_ring[i]);
210 vmxnet3_dev_tx_queue_reset(void *txq)
212 vmxnet3_tx_queue_t *tq = txq;
213 struct vmxnet3_cmd_ring *ring = &tq->cmd_ring;
214 struct vmxnet3_comp_ring *comp_ring = &tq->comp_ring;
215 struct vmxnet3_data_ring *data_ring = &tq->data_ring;
219 /* Release the cmd_ring mbufs */
220 vmxnet3_cmd_ring_release_mbufs(&tq->cmd_ring);
223 /* Tx vmxnet rings structure initialization*/
226 ring->gen = VMXNET3_INIT_GEN;
227 comp_ring->next2proc = 0;
228 comp_ring->gen = VMXNET3_INIT_GEN;
230 size = sizeof(struct Vmxnet3_TxDesc) * ring->size;
231 size += sizeof(struct Vmxnet3_TxCompDesc) * comp_ring->size;
232 size += sizeof(struct Vmxnet3_TxDataDesc) * data_ring->size;
234 memset(ring->base, 0, size);
238 vmxnet3_dev_rx_queue_reset(void *rxq)
241 vmxnet3_rx_queue_t *rq = rxq;
242 struct vmxnet3_cmd_ring *ring0, *ring1;
243 struct vmxnet3_comp_ring *comp_ring;
247 /* Release both the cmd_rings mbufs */
248 for (i = 0; i < VMXNET3_RX_CMDRING_SIZE; i++)
249 vmxnet3_cmd_ring_release_mbufs(&rq->cmd_ring[i]);
252 ring0 = &rq->cmd_ring[0];
253 ring1 = &rq->cmd_ring[1];
254 comp_ring = &rq->comp_ring;
256 /* Rx vmxnet rings structure initialization */
257 ring0->next2fill = 0;
258 ring1->next2fill = 0;
259 ring0->next2comp = 0;
260 ring1->next2comp = 0;
261 ring0->gen = VMXNET3_INIT_GEN;
262 ring1->gen = VMXNET3_INIT_GEN;
263 comp_ring->next2proc = 0;
264 comp_ring->gen = VMXNET3_INIT_GEN;
266 size = sizeof(struct Vmxnet3_RxDesc) * (ring0->size + ring1->size);
267 size += sizeof(struct Vmxnet3_RxCompDesc) * comp_ring->size;
269 memset(ring0->base, 0, size);
273 vmxnet3_dev_clear_queues(struct rte_eth_dev *dev)
277 PMD_INIT_FUNC_TRACE();
279 for (i = 0; i < dev->data->nb_tx_queues; i++) {
280 struct vmxnet3_tx_queue *txq = dev->data->tx_queues[i];
284 vmxnet3_dev_tx_queue_reset(txq);
288 for (i = 0; i < dev->data->nb_rx_queues; i++) {
289 struct vmxnet3_rx_queue *rxq = dev->data->rx_queues[i];
293 vmxnet3_dev_rx_queue_reset(rxq);
299 vmxnet3_tq_tx_complete(vmxnet3_tx_queue_t *txq)
302 struct rte_mbuf *mbuf;
303 vmxnet3_comp_ring_t *comp_ring = &txq->comp_ring;
304 struct Vmxnet3_TxCompDesc *tcd = (struct Vmxnet3_TxCompDesc *)
305 (comp_ring->base + comp_ring->next2proc);
307 while (tcd->gen == comp_ring->gen) {
308 /* Release cmd_ring descriptor and free mbuf */
309 VMXNET3_ASSERT(txq->cmd_ring.base[tcd->txdIdx].txd.eop == 1);
310 while (txq->cmd_ring.next2comp != tcd->txdIdx) {
311 mbuf = txq->cmd_ring.buf_info[txq->cmd_ring.next2comp].m;
312 txq->cmd_ring.buf_info[txq->cmd_ring.next2comp].m = NULL;
313 rte_pktmbuf_free_seg(mbuf);
315 /* Mark the txd for which tcd was generated as completed */
316 vmxnet3_cmd_ring_adv_next2comp(&txq->cmd_ring);
320 vmxnet3_comp_ring_adv_next2proc(comp_ring);
321 tcd = (struct Vmxnet3_TxCompDesc *)(comp_ring->base +
322 comp_ring->next2proc);
325 PMD_TX_LOG(DEBUG, "Processed %d tx comps & command descs.", completed);
329 vmxnet3_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
333 vmxnet3_tx_queue_t *txq = tx_queue;
334 struct vmxnet3_hw *hw = txq->hw;
336 if (unlikely(txq->stopped)) {
337 PMD_TX_LOG(DEBUG, "Tx queue is stopped.");
341 /* Free up the comp_descriptors aggressively */
342 vmxnet3_tq_tx_complete(txq);
345 while (nb_tx < nb_pkts) {
346 Vmxnet3_GenericDesc *gdesc;
347 vmxnet3_buf_info_t *tbi;
348 uint32_t first2fill, avail, dw2;
349 struct rte_mbuf *txm = tx_pkts[nb_tx];
350 struct rte_mbuf *m_seg = txm;
352 /* Is this packet execessively fragmented, then drop */
353 if (unlikely(txm->nb_segs > VMXNET3_MAX_TXD_PER_PKT)) {
354 ++txq->stats.drop_too_many_segs;
355 ++txq->stats.drop_total;
356 rte_pktmbuf_free(txm);
361 /* Is command ring full? */
362 avail = vmxnet3_cmd_ring_desc_avail(&txq->cmd_ring);
363 if (txm->nb_segs > avail) {
364 ++txq->stats.tx_ring_full;
368 /* use the previous gen bit for the SOP desc */
369 dw2 = (txq->cmd_ring.gen ^ 0x1) << VMXNET3_TXD_GEN_SHIFT;
370 first2fill = txq->cmd_ring.next2fill;
372 /* Remember the transmit buffer for cleanup */
373 tbi = txq->cmd_ring.buf_info + txq->cmd_ring.next2fill;
376 /* NB: the following assumes that VMXNET3 maximum
377 transmit buffer size (16K) is greater than
378 maximum sizeof mbuf segment size. */
379 gdesc = txq->cmd_ring.base + txq->cmd_ring.next2fill;
380 gdesc->txd.addr = RTE_MBUF_DATA_DMA_ADDR(m_seg);
381 gdesc->dword[2] = dw2 | m_seg->data_len;
384 /* move to the next2fill descriptor */
385 vmxnet3_cmd_ring_adv_next2fill(&txq->cmd_ring);
387 /* use the right gen for non-SOP desc */
388 dw2 = txq->cmd_ring.gen << VMXNET3_TXD_GEN_SHIFT;
389 } while ((m_seg = m_seg->next) != NULL);
391 /* Update the EOP descriptor */
392 gdesc->dword[3] |= VMXNET3_TXD_EOP | VMXNET3_TXD_CQ;
394 /* Add VLAN tag if present */
395 gdesc = txq->cmd_ring.base + first2fill;
396 if (txm->ol_flags & PKT_TX_VLAN_PKT) {
398 gdesc->txd.tci = txm->vlan_tci;
401 /* TODO: Add transmit checksum offload here */
403 /* flip the GEN bit on the SOP */
404 rte_compiler_barrier();
405 gdesc->dword[2] ^= VMXNET3_TXD_GEN;
407 txq->shared->ctrl.txNumDeferred++;
411 PMD_TX_LOG(DEBUG, "vmxnet3 txThreshold: %u", txq->shared->ctrl.txThreshold);
413 if (txq->shared->ctrl.txNumDeferred >= txq->shared->ctrl.txThreshold) {
415 txq->shared->ctrl.txNumDeferred = 0;
416 /* Notify vSwitch that packets are available. */
417 VMXNET3_WRITE_BAR0_REG(hw, (VMXNET3_REG_TXPROD + txq->queue_id * VMXNET3_REG_ALIGN),
418 txq->cmd_ring.next2fill);
425 * Allocates mbufs and clusters. Post rx descriptors with buffer details
426 * so that device can receive packets in those buffers.
428 * Among the two rings, 1st ring contains buffers of type 0 and type1.
429 * bufs_per_pkt is set such that for non-LRO cases all the buffers required
430 * by a frame will fit in 1st ring (1st buf of type0 and rest of type1).
431 * 2nd ring contains buffers of type 1 alone. Second ring mostly be used
436 vmxnet3_post_rx_bufs(vmxnet3_rx_queue_t *rxq, uint8_t ring_id)
439 uint32_t i = 0, val = 0;
440 struct vmxnet3_cmd_ring *ring = &rxq->cmd_ring[ring_id];
443 /* Usually: One HEAD type buf per packet
444 * val = (ring->next2fill % rxq->hw->bufs_per_pkt) ?
445 * VMXNET3_RXD_BTYPE_BODY : VMXNET3_RXD_BTYPE_HEAD;
448 /* We use single packet buffer so all heads here */
449 val = VMXNET3_RXD_BTYPE_HEAD;
451 /* All BODY type buffers for 2nd ring */
452 val = VMXNET3_RXD_BTYPE_BODY;
455 while (vmxnet3_cmd_ring_desc_avail(ring) > 0) {
456 struct Vmxnet3_RxDesc *rxd;
457 struct rte_mbuf *mbuf;
458 vmxnet3_buf_info_t *buf_info = &ring->buf_info[ring->next2fill];
460 rxd = (struct Vmxnet3_RxDesc *)(ring->base + ring->next2fill);
462 /* Allocate blank mbuf for the current Rx Descriptor */
463 mbuf = rte_rxmbuf_alloc(rxq->mp);
464 if (unlikely(mbuf == NULL)) {
465 PMD_RX_LOG(ERR, "Error allocating mbuf in %s", __func__);
466 rxq->stats.rx_buf_alloc_failure++;
472 * Load mbuf pointer into buf_info[ring_size]
473 * buf_info structure is equivalent to cookie for virtio-virtqueue
476 buf_info->len = (uint16_t)(mbuf->buf_len -
477 RTE_PKTMBUF_HEADROOM);
478 buf_info->bufPA = RTE_MBUF_DATA_DMA_ADDR_DEFAULT(mbuf);
480 /* Load Rx Descriptor with the buffer's GPA */
481 rxd->addr = buf_info->bufPA;
483 /* After this point rxd->addr MUST not be NULL */
485 rxd->len = buf_info->len;
486 /* Flip gen bit at the end to change ownership */
487 rxd->gen = ring->gen;
489 vmxnet3_cmd_ring_adv_next2fill(ring);
493 /* Return error only if no buffers are posted at present */
494 if (vmxnet3_cmd_ring_desc_avail(ring) >= (ring->size - 1))
501 /* Receive side checksum and other offloads */
503 vmxnet3_rx_offload(const Vmxnet3_RxCompDesc *rcd, struct rte_mbuf *rxm)
505 /* Check for hardware stripped VLAN tag */
507 rxm->ol_flags |= PKT_RX_VLAN_PKT;
508 rxm->vlan_tci = rte_le_to_cpu_16((uint16_t)rcd->tci);
512 if (rcd->rssType != VMXNET3_RCD_RSS_TYPE_NONE) {
513 rxm->ol_flags |= PKT_RX_RSS_HASH;
514 rxm->hash.rss = rcd->rssHash;
517 /* Check packet type, checksum errors, etc. Only support IPv4 for now. */
519 struct ether_hdr *eth = rte_pktmbuf_mtod(rxm, struct ether_hdr *);
520 struct ipv4_hdr *ip = (struct ipv4_hdr *)(eth + 1);
522 if (((ip->version_ihl & 0xf) << 2) > (int)sizeof(struct ipv4_hdr))
524 rxm->packet_type = RTE_PTYPE_L3_IPV4_EXT;
526 rxm->ol_flags |= PKT_RX_IPV4_HDR_EXT;
530 rxm->packet_type = RTE_PTYPE_L3_IPV4;
532 rxm->ol_flags |= PKT_RX_IPV4_HDR;
537 rxm->ol_flags |= PKT_RX_IP_CKSUM_BAD;
539 if ((rcd->tcp || rcd->udp) && !rcd->tuc)
540 rxm->ol_flags |= PKT_RX_L4_CKSUM_BAD;
546 * Process the Rx Completion Ring of given vmxnet3_rx_queue
547 * for nb_pkts burst and return the number of packets received
550 vmxnet3_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
553 uint32_t nb_rxd, idx;
555 vmxnet3_rx_queue_t *rxq;
556 Vmxnet3_RxCompDesc *rcd;
557 vmxnet3_buf_info_t *rbi;
559 struct rte_mbuf *rxm = NULL;
560 struct vmxnet3_hw *hw;
570 rcd = &rxq->comp_ring.base[rxq->comp_ring.next2proc].rcd;
572 if (unlikely(rxq->stopped)) {
573 PMD_RX_LOG(DEBUG, "Rx queue is stopped.");
577 while (rcd->gen == rxq->comp_ring.gen) {
578 if (nb_rx >= nb_pkts)
582 ring_idx = (uint8_t)((rcd->rqID == rxq->qid1) ? 0 : 1);
583 rxd = (Vmxnet3_RxDesc *)rxq->cmd_ring[ring_idx].base + idx;
584 rbi = rxq->cmd_ring[ring_idx].buf_info + idx;
586 if (unlikely(rcd->sop != 1 || rcd->eop != 1)) {
587 rte_pktmbuf_free_seg(rbi->m);
588 PMD_RX_LOG(DEBUG, "Packet spread across multiple buffers\n)");
592 PMD_RX_LOG(DEBUG, "rxd idx: %d ring idx: %d.", idx, ring_idx);
594 VMXNET3_ASSERT(rcd->len <= rxd->len);
595 VMXNET3_ASSERT(rbi->m);
597 if (unlikely(rcd->len == 0)) {
598 PMD_RX_LOG(DEBUG, "Rx buf was skipped. rxring[%d][%d]\n)",
600 VMXNET3_ASSERT(rcd->sop && rcd->eop);
601 rte_pktmbuf_free_seg(rbi->m);
605 /* Assuming a packet is coming in a single packet buffer */
606 if (unlikely(rxd->btype != VMXNET3_RXD_BTYPE_HEAD)) {
608 "Alert : Misbehaving device, incorrect "
609 " buffer type used. iPacket dropped.");
610 rte_pktmbuf_free_seg(rbi->m);
613 VMXNET3_ASSERT(rxd->btype == VMXNET3_RXD_BTYPE_HEAD);
615 /* Get the packet buffer pointer from buf_info */
618 /* Clear descriptor associated buf_info to be reused */
622 /* Update the index that we received a packet */
623 rxq->cmd_ring[ring_idx].next2comp = idx;
625 /* For RCD with EOP set, check if there is frame error */
626 if (unlikely(rcd->err)) {
627 rxq->stats.drop_total++;
628 rxq->stats.drop_err++;
631 rxq->stats.drop_fcs++;
632 PMD_RX_LOG(ERR, "Recv packet dropped due to frame err.");
634 PMD_RX_LOG(ERR, "Error in received packet rcd#:%d rxd:%d",
635 (int)(rcd - (struct Vmxnet3_RxCompDesc *)
636 rxq->comp_ring.base), rcd->rxdIdx);
637 rte_pktmbuf_free_seg(rxm);
642 /* Initialize newly received packet buffer */
643 rxm->port = rxq->port_id;
646 rxm->pkt_len = (uint16_t)rcd->len;
647 rxm->data_len = (uint16_t)rcd->len;
648 rxm->data_off = RTE_PKTMBUF_HEADROOM;
652 vmxnet3_rx_offload(rcd, rxm);
654 rx_pkts[nb_rx++] = rxm;
656 rxq->cmd_ring[ring_idx].next2comp = idx;
657 VMXNET3_INC_RING_IDX_ONLY(rxq->cmd_ring[ring_idx].next2comp, rxq->cmd_ring[ring_idx].size);
659 /* It's time to allocate some new buf and renew descriptors */
660 vmxnet3_post_rx_bufs(rxq, ring_idx);
661 if (unlikely(rxq->shared->ctrl.updateRxProd)) {
662 VMXNET3_WRITE_BAR0_REG(hw, rxprod_reg[ring_idx] + (rxq->queue_id * VMXNET3_REG_ALIGN),
663 rxq->cmd_ring[ring_idx].next2fill);
666 /* Advance to the next descriptor in comp_ring */
667 vmxnet3_comp_ring_adv_next2proc(&rxq->comp_ring);
669 rcd = &rxq->comp_ring.base[rxq->comp_ring.next2proc].rcd;
671 if (nb_rxd > rxq->cmd_ring[0].size) {
673 "Used up quota of receiving packets,"
674 " relinquish control.");
683 * Create memzone for device rings. malloc can't be used as the physical address is
684 * needed. If the memzone is already created, then this function returns a ptr
687 static const struct rte_memzone *
688 ring_dma_zone_reserve(struct rte_eth_dev *dev, const char *ring_name,
689 uint16_t queue_id, uint32_t ring_size, int socket_id)
691 char z_name[RTE_MEMZONE_NAMESIZE];
692 const struct rte_memzone *mz;
694 snprintf(z_name, sizeof(z_name), "%s_%s_%d_%d",
695 dev->driver->pci_drv.name, ring_name,
696 dev->data->port_id, queue_id);
698 mz = rte_memzone_lookup(z_name);
702 return rte_memzone_reserve_aligned(z_name, ring_size,
703 socket_id, 0, VMXNET3_RING_BA_ALIGN);
707 vmxnet3_dev_tx_queue_setup(struct rte_eth_dev *dev,
710 unsigned int socket_id,
711 __attribute__((unused)) const struct rte_eth_txconf *tx_conf)
713 struct vmxnet3_hw *hw = dev->data->dev_private;
714 const struct rte_memzone *mz;
715 struct vmxnet3_tx_queue *txq;
716 struct vmxnet3_cmd_ring *ring;
717 struct vmxnet3_comp_ring *comp_ring;
718 struct vmxnet3_data_ring *data_ring;
721 PMD_INIT_FUNC_TRACE();
723 if ((tx_conf->txq_flags & ETH_TXQ_FLAGS_NOXSUMS) !=
724 ETH_TXQ_FLAGS_NOXSUMS) {
725 PMD_INIT_LOG(ERR, "TX no support for checksum offload yet");
729 txq = rte_zmalloc("ethdev_tx_queue", sizeof(struct vmxnet3_tx_queue), RTE_CACHE_LINE_SIZE);
731 PMD_INIT_LOG(ERR, "Can not allocate tx queue structure");
735 txq->queue_id = queue_idx;
736 txq->port_id = dev->data->port_id;
737 txq->shared = &hw->tqd_start[queue_idx];
739 txq->qid = queue_idx;
742 ring = &txq->cmd_ring;
743 comp_ring = &txq->comp_ring;
744 data_ring = &txq->data_ring;
746 /* Tx vmxnet ring length should be between 512-4096 */
747 if (nb_desc < VMXNET3_DEF_TX_RING_SIZE) {
748 PMD_INIT_LOG(ERR, "VMXNET3 Tx Ring Size Min: %u",
749 VMXNET3_DEF_TX_RING_SIZE);
751 } else if (nb_desc > VMXNET3_TX_RING_MAX_SIZE) {
752 PMD_INIT_LOG(ERR, "VMXNET3 Tx Ring Size Max: %u",
753 VMXNET3_TX_RING_MAX_SIZE);
756 ring->size = nb_desc;
757 ring->size &= ~VMXNET3_RING_SIZE_MASK;
759 comp_ring->size = data_ring->size = ring->size;
761 /* Tx vmxnet rings structure initialization*/
764 ring->gen = VMXNET3_INIT_GEN;
765 comp_ring->next2proc = 0;
766 comp_ring->gen = VMXNET3_INIT_GEN;
768 size = sizeof(struct Vmxnet3_TxDesc) * ring->size;
769 size += sizeof(struct Vmxnet3_TxCompDesc) * comp_ring->size;
770 size += sizeof(struct Vmxnet3_TxDataDesc) * data_ring->size;
772 mz = ring_dma_zone_reserve(dev, "txdesc", queue_idx, size, socket_id);
774 PMD_INIT_LOG(ERR, "ERROR: Creating queue descriptors zone");
777 memset(mz->addr, 0, mz->len);
779 /* cmd_ring initialization */
780 ring->base = mz->addr;
781 ring->basePA = mz->phys_addr;
783 /* comp_ring initialization */
784 comp_ring->base = ring->base + ring->size;
785 comp_ring->basePA = ring->basePA +
786 (sizeof(struct Vmxnet3_TxDesc) * ring->size);
788 /* data_ring initialization */
789 data_ring->base = (Vmxnet3_TxDataDesc *)(comp_ring->base + comp_ring->size);
790 data_ring->basePA = comp_ring->basePA +
791 (sizeof(struct Vmxnet3_TxCompDesc) * comp_ring->size);
793 /* cmd_ring0 buf_info allocation */
794 ring->buf_info = rte_zmalloc("tx_ring_buf_info",
795 ring->size * sizeof(vmxnet3_buf_info_t), RTE_CACHE_LINE_SIZE);
796 if (ring->buf_info == NULL) {
797 PMD_INIT_LOG(ERR, "ERROR: Creating tx_buf_info structure");
801 /* Update the data portion with txq */
802 dev->data->tx_queues[queue_idx] = txq;
808 vmxnet3_dev_rx_queue_setup(struct rte_eth_dev *dev,
811 unsigned int socket_id,
812 __attribute__((unused)) const struct rte_eth_rxconf *rx_conf,
813 struct rte_mempool *mp)
815 const struct rte_memzone *mz;
816 struct vmxnet3_rx_queue *rxq;
817 struct vmxnet3_hw *hw = dev->data->dev_private;
818 struct vmxnet3_cmd_ring *ring0, *ring1, *ring;
819 struct vmxnet3_comp_ring *comp_ring;
825 PMD_INIT_FUNC_TRACE();
827 buf_size = rte_pktmbuf_data_room_size(mp) -
828 RTE_PKTMBUF_HEADROOM;
830 if (dev->data->dev_conf.rxmode.max_rx_pkt_len > buf_size) {
831 PMD_INIT_LOG(ERR, "buf_size = %u, max_pkt_len = %u, "
832 "VMXNET3 don't support scatter packets yet",
833 buf_size, dev->data->dev_conf.rxmode.max_rx_pkt_len);
837 rxq = rte_zmalloc("ethdev_rx_queue", sizeof(struct vmxnet3_rx_queue), RTE_CACHE_LINE_SIZE);
839 PMD_INIT_LOG(ERR, "Can not allocate rx queue structure");
844 rxq->queue_id = queue_idx;
845 rxq->port_id = dev->data->port_id;
846 rxq->shared = &hw->rqd_start[queue_idx];
848 rxq->qid1 = queue_idx;
849 rxq->qid2 = queue_idx + hw->num_rx_queues;
852 ring0 = &rxq->cmd_ring[0];
853 ring1 = &rxq->cmd_ring[1];
854 comp_ring = &rxq->comp_ring;
856 /* Rx vmxnet rings length should be between 256-4096 */
857 if (nb_desc < VMXNET3_DEF_RX_RING_SIZE) {
858 PMD_INIT_LOG(ERR, "VMXNET3 Rx Ring Size Min: 256");
860 } else if (nb_desc > VMXNET3_RX_RING_MAX_SIZE) {
861 PMD_INIT_LOG(ERR, "VMXNET3 Rx Ring Size Max: 4096");
864 ring0->size = nb_desc;
865 ring0->size &= ~VMXNET3_RING_SIZE_MASK;
866 ring1->size = ring0->size;
869 comp_ring->size = ring0->size + ring1->size;
871 /* Rx vmxnet rings structure initialization */
872 ring0->next2fill = 0;
873 ring1->next2fill = 0;
874 ring0->next2comp = 0;
875 ring1->next2comp = 0;
876 ring0->gen = VMXNET3_INIT_GEN;
877 ring1->gen = VMXNET3_INIT_GEN;
878 comp_ring->next2proc = 0;
879 comp_ring->gen = VMXNET3_INIT_GEN;
881 size = sizeof(struct Vmxnet3_RxDesc) * (ring0->size + ring1->size);
882 size += sizeof(struct Vmxnet3_RxCompDesc) * comp_ring->size;
884 mz = ring_dma_zone_reserve(dev, "rxdesc", queue_idx, size, socket_id);
886 PMD_INIT_LOG(ERR, "ERROR: Creating queue descriptors zone");
889 memset(mz->addr, 0, mz->len);
891 /* cmd_ring0 initialization */
892 ring0->base = mz->addr;
893 ring0->basePA = mz->phys_addr;
895 /* cmd_ring1 initialization */
896 ring1->base = ring0->base + ring0->size;
897 ring1->basePA = ring0->basePA + sizeof(struct Vmxnet3_RxDesc) * ring0->size;
899 /* comp_ring initialization */
900 comp_ring->base = ring1->base + ring1->size;
901 comp_ring->basePA = ring1->basePA + sizeof(struct Vmxnet3_RxDesc) *
904 /* cmd_ring0-cmd_ring1 buf_info allocation */
905 for (i = 0; i < VMXNET3_RX_CMDRING_SIZE; i++) {
907 ring = &rxq->cmd_ring[i];
909 snprintf(mem_name, sizeof(mem_name), "rx_ring_%d_buf_info", i);
911 ring->buf_info = rte_zmalloc(mem_name, ring->size * sizeof(vmxnet3_buf_info_t), RTE_CACHE_LINE_SIZE);
912 if (ring->buf_info == NULL) {
913 PMD_INIT_LOG(ERR, "ERROR: Creating rx_buf_info structure");
918 /* Update the data portion with rxq */
919 dev->data->rx_queues[queue_idx] = rxq;
925 * Initializes Receive Unit
926 * Load mbufs in rx queue in advance
929 vmxnet3_dev_rxtx_init(struct rte_eth_dev *dev)
931 struct vmxnet3_hw *hw = dev->data->dev_private;
936 PMD_INIT_FUNC_TRACE();
938 for (i = 0; i < hw->num_rx_queues; i++) {
939 vmxnet3_rx_queue_t *rxq = dev->data->rx_queues[i];
941 for (j = 0; j < VMXNET3_RX_CMDRING_SIZE; j++) {
942 /* Passing 0 as alloc_num will allocate full ring */
943 ret = vmxnet3_post_rx_bufs(rxq, j);
945 PMD_INIT_LOG(ERR, "ERROR: Posting Rxq: %d buffers ring: %d", i, j);
948 /* Updating device with the index:next2fill to fill the mbufs for coming packets */
949 if (unlikely(rxq->shared->ctrl.updateRxProd)) {
950 VMXNET3_WRITE_BAR0_REG(hw, rxprod_reg[j] + (rxq->queue_id * VMXNET3_REG_ALIGN),
951 rxq->cmd_ring[j].next2fill);
954 rxq->stopped = FALSE;
957 for (i = 0; i < dev->data->nb_tx_queues; i++) {
958 struct vmxnet3_tx_queue *txq = dev->data->tx_queues[i];
960 txq->stopped = FALSE;
966 static uint8_t rss_intel_key[40] = {
967 0x6D, 0x5A, 0x56, 0xDA, 0x25, 0x5B, 0x0E, 0xC2,
968 0x41, 0x67, 0x25, 0x3D, 0x43, 0xA3, 0x8F, 0xB0,
969 0xD0, 0xCA, 0x2B, 0xCB, 0xAE, 0x7B, 0x30, 0xB4,
970 0x77, 0xCB, 0x2D, 0xA3, 0x80, 0x30, 0xF2, 0x0C,
971 0x6A, 0x42, 0xB7, 0x3B, 0xBE, 0xAC, 0x01, 0xFA,
975 * Configure RSS feature
978 vmxnet3_rss_configure(struct rte_eth_dev *dev)
980 struct vmxnet3_hw *hw = dev->data->dev_private;
981 struct VMXNET3_RSSConf *dev_rss_conf;
982 struct rte_eth_rss_conf *port_rss_conf;
986 PMD_INIT_FUNC_TRACE();
988 dev_rss_conf = hw->rss_conf;
989 port_rss_conf = &dev->data->dev_conf.rx_adv_conf.rss_conf;
991 /* loading hashFunc */
992 dev_rss_conf->hashFunc = VMXNET3_RSS_HASH_FUNC_TOEPLITZ;
993 /* loading hashKeySize */
994 dev_rss_conf->hashKeySize = VMXNET3_RSS_MAX_KEY_SIZE;
995 /* loading indTableSize : Must not exceed VMXNET3_RSS_MAX_IND_TABLE_SIZE (128)*/
996 dev_rss_conf->indTableSize = (uint16_t)(hw->num_rx_queues * 4);
998 if (port_rss_conf->rss_key == NULL) {
999 /* Default hash key */
1000 port_rss_conf->rss_key = rss_intel_key;
1003 /* loading hashKey */
1004 memcpy(&dev_rss_conf->hashKey[0], port_rss_conf->rss_key, dev_rss_conf->hashKeySize);
1006 /* loading indTable */
1007 for (i = 0, j = 0; i < dev_rss_conf->indTableSize; i++, j++) {
1008 if (j == dev->data->nb_rx_queues)
1010 dev_rss_conf->indTable[i] = j;
1013 /* loading hashType */
1014 dev_rss_conf->hashType = 0;
1015 rss_hf = port_rss_conf->rss_hf & VMXNET3_RSS_OFFLOAD_ALL;
1016 if (rss_hf & ETH_RSS_IPV4)
1017 dev_rss_conf->hashType |= VMXNET3_RSS_HASH_TYPE_IPV4;
1018 if (rss_hf & ETH_RSS_NONFRAG_IPV4_TCP)
1019 dev_rss_conf->hashType |= VMXNET3_RSS_HASH_TYPE_TCP_IPV4;
1020 if (rss_hf & ETH_RSS_IPV6)
1021 dev_rss_conf->hashType |= VMXNET3_RSS_HASH_TYPE_IPV6;
1022 if (rss_hf & ETH_RSS_NONFRAG_IPV6_TCP)
1023 dev_rss_conf->hashType |= VMXNET3_RSS_HASH_TYPE_TCP_IPV6;
1025 return VMXNET3_SUCCESS;