1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(C) 2021 Marvell.
8 #include "cnxk_bphy_irq.h"
10 enum cnxk_bphy_cgx_msg_type {
11 CNXK_BPHY_CGX_MSG_TYPE_GET_LINKINFO,
12 CNXK_BPHY_CGX_MSG_TYPE_INTLBK_DISABLE,
13 CNXK_BPHY_CGX_MSG_TYPE_INTLBK_ENABLE,
14 CNXK_BPHY_CGX_MSG_TYPE_PTP_RX_DISABLE,
15 CNXK_BPHY_CGX_MSG_TYPE_PTP_RX_ENABLE,
16 CNXK_BPHY_CGX_MSG_TYPE_SET_LINK_MODE,
17 CNXK_BPHY_CGX_MSG_TYPE_SET_LINK_STATE,
18 CNXK_BPHY_CGX_MSG_TYPE_START_RXTX,
19 CNXK_BPHY_CGX_MSG_TYPE_STOP_RXTX,
20 CNXK_BPHY_CGX_MSG_TYPE_GET_SUPPORTED_FEC,
21 CNXK_BPHY_CGX_MSG_TYPE_SET_FEC,
24 enum cnxk_bphy_cgx_eth_link_speed {
25 CNXK_BPHY_CGX_ETH_LINK_SPEED_NONE,
26 CNXK_BPHY_CGX_ETH_LINK_SPEED_10M,
27 CNXK_BPHY_CGX_ETH_LINK_SPEED_100M,
28 CNXK_BPHY_CGX_ETH_LINK_SPEED_1G,
29 CNXK_BPHY_CGX_ETH_LINK_SPEED_2HG,
30 CNXK_BPHY_CGX_ETH_LINK_SPEED_5G,
31 CNXK_BPHY_CGX_ETH_LINK_SPEED_10G,
32 CNXK_BPHY_CGX_ETH_LINK_SPEED_20G,
33 CNXK_BPHY_CGX_ETH_LINK_SPEED_25G,
34 CNXK_BPHY_CGX_ETH_LINK_SPEED_40G,
35 CNXK_BPHY_CGX_ETH_LINK_SPEED_50G,
36 CNXK_BPHY_CGX_ETH_LINK_SPEED_80G,
37 CNXK_BPHY_CGX_ETH_LINK_SPEED_100G,
38 __CNXK_BPHY_CGX_ETH_LINK_SPEED_MAX
41 enum cnxk_bphy_cgx_eth_link_fec {
42 CNXK_BPHY_CGX_ETH_LINK_FEC_NONE,
43 CNXK_BPHY_CGX_ETH_LINK_FEC_BASE_R,
44 CNXK_BPHY_CGX_ETH_LINK_FEC_RS,
45 __CNXK_BPHY_CGX_ETH_LINK_FEC_MAX
48 enum cnxk_bphy_cgx_eth_link_mode {
49 CNXK_BPHY_CGX_ETH_LINK_MODE_SGMII_BIT,
50 CNXK_BPHY_CGX_ETH_LINK_MODE_1000_BASEX_BIT,
51 CNXK_BPHY_CGX_ETH_LINK_MODE_QSGMII_BIT,
52 CNXK_BPHY_CGX_ETH_LINK_MODE_10G_C2C_BIT,
53 CNXK_BPHY_CGX_ETH_LINK_MODE_10G_C2M_BIT,
54 CNXK_BPHY_CGX_ETH_LINK_MODE_10G_KR_BIT,
55 CNXK_BPHY_CGX_ETH_LINK_MODE_20G_C2C_BIT,
56 CNXK_BPHY_CGX_ETH_LINK_MODE_25G_C2C_BIT,
57 CNXK_BPHY_CGX_ETH_LINK_MODE_25G_C2M_BIT,
58 CNXK_BPHY_CGX_ETH_LINK_MODE_25G_2_C2C_BIT,
59 CNXK_BPHY_CGX_ETH_LINK_MODE_25G_CR_BIT,
60 CNXK_BPHY_CGX_ETH_LINK_MODE_25G_KR_BIT,
61 CNXK_BPHY_CGX_ETH_LINK_MODE_40G_C2C_BIT,
62 CNXK_BPHY_CGX_ETH_LINK_MODE_40G_C2M_BIT,
63 CNXK_BPHY_CGX_ETH_LINK_MODE_40G_CR4_BIT,
64 CNXK_BPHY_CGX_ETH_LINK_MODE_40G_KR4_BIT,
65 CNXK_BPHY_CGX_ETH_LINK_MODE_40GAUI_C2C_BIT,
66 CNXK_BPHY_CGX_ETH_LINK_MODE_50G_C2C_BIT,
67 CNXK_BPHY_CGX_ETH_LINK_MODE_50G_C2M_BIT,
68 CNXK_BPHY_CGX_ETH_LINK_MODE_50G_4_C2C_BIT,
69 CNXK_BPHY_CGX_ETH_LINK_MODE_50G_CR_BIT,
70 CNXK_BPHY_CGX_ETH_LINK_MODE_50G_KR_BIT,
71 CNXK_BPHY_CGX_ETH_LINK_MODE_80GAUI_C2C_BIT,
72 CNXK_BPHY_CGX_ETH_LINK_MODE_100G_C2C_BIT,
73 CNXK_BPHY_CGX_ETH_LINK_MODE_100G_C2M_BIT,
74 CNXK_BPHY_CGX_ETH_LINK_MODE_100G_CR4_BIT,
75 CNXK_BPHY_CGX_ETH_LINK_MODE_100G_KR4_BIT,
76 __CNXK_BPHY_CGX_ETH_LINK_MODE_MAX
79 struct cnxk_bphy_cgx_msg_link_mode {
82 enum cnxk_bphy_cgx_eth_link_speed speed;
83 enum cnxk_bphy_cgx_eth_link_mode mode;
86 struct cnxk_bphy_cgx_msg_link_info {
89 enum cnxk_bphy_cgx_eth_link_speed speed;
91 enum cnxk_bphy_cgx_eth_link_fec fec;
92 enum cnxk_bphy_cgx_eth_link_mode mode;
95 struct cnxk_bphy_cgx_msg_set_link_state {
96 bool state; /* up or down */
99 struct cnxk_bphy_cgx_msg {
100 enum cnxk_bphy_cgx_msg_type type;
102 * data depends on message type and whether
103 * it's a request or a response
108 #define cnxk_bphy_mem bphy_mem
109 #define CNXK_BPHY_DEF_QUEUE 0
111 enum cnxk_bphy_irq_msg_type {
112 CNXK_BPHY_IRQ_MSG_TYPE_INIT,
113 CNXK_BPHY_IRQ_MSG_TYPE_FINI,
114 CNXK_BPHY_IRQ_MSG_TYPE_REGISTER,
115 CNXK_BPHY_IRQ_MSG_TYPE_UNREGISTER,
116 CNXK_BPHY_IRQ_MSG_TYPE_MEM_GET,
119 struct cnxk_bphy_irq_msg {
120 enum cnxk_bphy_irq_msg_type type;
122 * The data field, depending on message type, may point to
123 * - (enq) full struct cnxk_bphy_irq_info for registration request
124 * - (enq) struct cnxk_bphy_irq_info with irq_num set for unregistration
125 * - (deq) struct cnxk_bphy_mem for memory range request response
131 struct cnxk_bphy_irq_info {
133 cnxk_bphy_intr_handler_t handler;
138 static __rte_always_inline int
139 rte_pmd_bphy_intr_init(uint16_t dev_id)
141 struct cnxk_bphy_irq_msg msg = {
142 .type = CNXK_BPHY_IRQ_MSG_TYPE_INIT,
144 struct rte_rawdev_buf *bufs[1];
145 struct rte_rawdev_buf buf;
150 return rte_rawdev_enqueue_buffers(dev_id, bufs, 1, CNXK_BPHY_DEF_QUEUE);
153 static __rte_always_inline void
154 rte_pmd_bphy_intr_fini(uint16_t dev_id)
156 struct cnxk_bphy_irq_msg msg = {
157 .type = CNXK_BPHY_IRQ_MSG_TYPE_FINI,
159 struct rte_rawdev_buf *bufs[1];
160 struct rte_rawdev_buf buf;
165 rte_rawdev_enqueue_buffers(dev_id, bufs, 1, CNXK_BPHY_DEF_QUEUE);
168 static __rte_always_inline int
169 rte_pmd_bphy_intr_register(uint16_t dev_id, int irq_num,
170 cnxk_bphy_intr_handler_t handler, void *data,
173 struct cnxk_bphy_irq_info info = {
179 struct cnxk_bphy_irq_msg msg = {
180 .type = CNXK_BPHY_IRQ_MSG_TYPE_REGISTER,
183 struct rte_rawdev_buf *bufs[1];
184 struct rte_rawdev_buf buf;
189 return rte_rawdev_enqueue_buffers(dev_id, bufs, 1, CNXK_BPHY_DEF_QUEUE);
192 static __rte_always_inline void
193 rte_pmd_bphy_intr_unregister(uint16_t dev_id, int irq_num)
195 struct cnxk_bphy_irq_info info = {
198 struct cnxk_bphy_irq_msg msg = {
199 .type = CNXK_BPHY_IRQ_MSG_TYPE_UNREGISTER,
202 struct rte_rawdev_buf *bufs[1];
203 struct rte_rawdev_buf buf;
208 rte_rawdev_enqueue_buffers(dev_id, bufs, 1, 0);
211 static __rte_always_inline struct cnxk_bphy_mem *
212 rte_pmd_bphy_intr_mem_get(uint16_t dev_id)
214 struct cnxk_bphy_irq_msg msg = {
215 .type = CNXK_BPHY_IRQ_MSG_TYPE_MEM_GET,
217 struct rte_rawdev_buf *bufs[1];
218 struct rte_rawdev_buf buf;
224 ret = rte_rawdev_enqueue_buffers(dev_id, bufs, 1, CNXK_BPHY_DEF_QUEUE);
228 ret = rte_rawdev_dequeue_buffers(dev_id, bufs, 1, CNXK_BPHY_DEF_QUEUE);
235 #endif /* _CNXK_BPHY_H_ */