drivers/raw/cnxk_bphy/rte_pmd_bphy.h

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(C) 2021 Marvell.
   3  */
   4
   5 #ifndef _CNXK_BPHY_H_
   6 #define _CNXK_BPHY_H_
   7
   8 enum cnxk_bphy_cgx_msg_type {
   9         CNXK_BPHY_CGX_MSG_TYPE_GET_LINKINFO,
  10         CNXK_BPHY_CGX_MSG_TYPE_INTLBK_DISABLE,
  11         CNXK_BPHY_CGX_MSG_TYPE_INTLBK_ENABLE,
  12         CNXK_BPHY_CGX_MSG_TYPE_PTP_RX_DISABLE,
  13         CNXK_BPHY_CGX_MSG_TYPE_PTP_RX_ENABLE,
  14         CNXK_BPHY_CGX_MSG_TYPE_SET_LINK_MODE,
  15         CNXK_BPHY_CGX_MSG_TYPE_SET_LINK_STATE,
  16         CNXK_BPHY_CGX_MSG_TYPE_START_RXTX,
  17         CNXK_BPHY_CGX_MSG_TYPE_STOP_RXTX,
  18 };
  19
  20 enum cnxk_bphy_cgx_eth_link_speed {
  21         CNXK_BPHY_CGX_ETH_LINK_SPEED_NONE,
  22         CNXK_BPHY_CGX_ETH_LINK_SPEED_10M,
  23         CNXK_BPHY_CGX_ETH_LINK_SPEED_100M,
  24         CNXK_BPHY_CGX_ETH_LINK_SPEED_1G,
  25         CNXK_BPHY_CGX_ETH_LINK_SPEED_2HG,
  26         CNXK_BPHY_CGX_ETH_LINK_SPEED_5G,
  27         CNXK_BPHY_CGX_ETH_LINK_SPEED_10G,
  28         CNXK_BPHY_CGX_ETH_LINK_SPEED_20G,
  29         CNXK_BPHY_CGX_ETH_LINK_SPEED_25G,
  30         CNXK_BPHY_CGX_ETH_LINK_SPEED_40G,
  31         CNXK_BPHY_CGX_ETH_LINK_SPEED_50G,
  32         CNXK_BPHY_CGX_ETH_LINK_SPEED_80G,
  33         CNXK_BPHY_CGX_ETH_LINK_SPEED_100G,
  34         __CNXK_BPHY_CGX_ETH_LINK_SPEED_MAX
  35 };
  36
  37 enum cnxk_bphy_cgx_eth_link_fec {
  38         CNXK_BPHY_CGX_ETH_LINK_FEC_NONE,
  39         CNXK_BPHY_CGX_ETH_LINK_FEC_BASE_R,
  40         CNXK_BPHY_CGX_ETH_LINK_FEC_RS,
  41         __CNXK_BPHY_CGX_ETH_LINK_FEC_MAX
  42 };
  43
  44 enum cnxk_bphy_cgx_eth_link_mode {
  45         CNXK_BPHY_CGX_ETH_LINK_MODE_SGMII_BIT,
  46         CNXK_BPHY_CGX_ETH_LINK_MODE_1000_BASEX_BIT,
  47         CNXK_BPHY_CGX_ETH_LINK_MODE_QSGMII_BIT,
  48         CNXK_BPHY_CGX_ETH_LINK_MODE_10G_C2C_BIT,
  49         CNXK_BPHY_CGX_ETH_LINK_MODE_10G_C2M_BIT,
  50         CNXK_BPHY_CGX_ETH_LINK_MODE_10G_KR_BIT,
  51         CNXK_BPHY_CGX_ETH_LINK_MODE_20G_C2C_BIT,
  52         CNXK_BPHY_CGX_ETH_LINK_MODE_25G_C2C_BIT,
  53         CNXK_BPHY_CGX_ETH_LINK_MODE_25G_C2M_BIT,
  54         CNXK_BPHY_CGX_ETH_LINK_MODE_25G_2_C2C_BIT,
  55         CNXK_BPHY_CGX_ETH_LINK_MODE_25G_CR_BIT,
  56         CNXK_BPHY_CGX_ETH_LINK_MODE_25G_KR_BIT,
  57         CNXK_BPHY_CGX_ETH_LINK_MODE_40G_C2C_BIT,
  58         CNXK_BPHY_CGX_ETH_LINK_MODE_40G_C2M_BIT,
  59         CNXK_BPHY_CGX_ETH_LINK_MODE_40G_CR4_BIT,
  60         CNXK_BPHY_CGX_ETH_LINK_MODE_40G_KR4_BIT,
  61         CNXK_BPHY_CGX_ETH_LINK_MODE_40GAUI_C2C_BIT,
  62         CNXK_BPHY_CGX_ETH_LINK_MODE_50G_C2C_BIT,
  63         CNXK_BPHY_CGX_ETH_LINK_MODE_50G_C2M_BIT,
  64         CNXK_BPHY_CGX_ETH_LINK_MODE_50G_4_C2C_BIT,
  65         CNXK_BPHY_CGX_ETH_LINK_MODE_50G_CR_BIT,
  66         CNXK_BPHY_CGX_ETH_LINK_MODE_50G_KR_BIT,
  67         CNXK_BPHY_CGX_ETH_LINK_MODE_80GAUI_C2C_BIT,
  68         CNXK_BPHY_CGX_ETH_LINK_MODE_100G_C2C_BIT,
  69         CNXK_BPHY_CGX_ETH_LINK_MODE_100G_C2M_BIT,
  70         CNXK_BPHY_CGX_ETH_LINK_MODE_100G_CR4_BIT,
  71         CNXK_BPHY_CGX_ETH_LINK_MODE_100G_KR4_BIT,
  72         __CNXK_BPHY_CGX_ETH_LINK_MODE_MAX
  73 };
  74
  75 struct cnxk_bphy_cgx_msg_link_mode {
  76         bool full_duplex;
  77         bool autoneg;
  78         enum cnxk_bphy_cgx_eth_link_speed speed;
  79         enum cnxk_bphy_cgx_eth_link_mode mode;
  80 };
  81
  82 struct cnxk_bphy_cgx_msg_link_info {
  83         bool link_up;
  84         bool full_duplex;
  85         enum cnxk_bphy_cgx_eth_link_speed speed;
  86         bool autoneg;
  87         enum cnxk_bphy_cgx_eth_link_fec fec;
  88         enum cnxk_bphy_cgx_eth_link_mode mode;
  89 };
  90
  91 struct cnxk_bphy_cgx_msg_set_link_state {
  92         bool state; /* up or down */
  93 };
  94
  95 struct cnxk_bphy_cgx_msg {
  96         enum cnxk_bphy_cgx_msg_type type;
  97         /*
  98          * data depends on message type and whether
  99          * it's a request or a response
 100          */
 101         void *data;
 102 };
 103
 104 #endif /* _CNXK_BPHY_H_ */