1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(C) 2021 Marvell.
10 #include <rte_common.h>
12 #include <rte_malloc.h>
13 #include <rte_memcpy.h>
14 #include <rte_rawdev.h>
20 enum cnxk_bphy_cgx_msg_type {
21 CNXK_BPHY_CGX_MSG_TYPE_GET_LINKINFO,
22 CNXK_BPHY_CGX_MSG_TYPE_INTLBK_DISABLE,
23 CNXK_BPHY_CGX_MSG_TYPE_INTLBK_ENABLE,
24 CNXK_BPHY_CGX_MSG_TYPE_PTP_RX_DISABLE,
25 CNXK_BPHY_CGX_MSG_TYPE_PTP_RX_ENABLE,
26 CNXK_BPHY_CGX_MSG_TYPE_SET_LINK_MODE,
27 CNXK_BPHY_CGX_MSG_TYPE_SET_LINK_STATE,
28 CNXK_BPHY_CGX_MSG_TYPE_START_RXTX,
29 CNXK_BPHY_CGX_MSG_TYPE_STOP_RXTX,
30 CNXK_BPHY_CGX_MSG_TYPE_GET_SUPPORTED_FEC,
31 CNXK_BPHY_CGX_MSG_TYPE_SET_FEC,
34 enum cnxk_bphy_cgx_eth_link_speed {
35 CNXK_BPHY_CGX_ETH_LINK_SPEED_NONE,
36 CNXK_BPHY_CGX_ETH_LINK_SPEED_10M,
37 CNXK_BPHY_CGX_ETH_LINK_SPEED_100M,
38 CNXK_BPHY_CGX_ETH_LINK_SPEED_1G,
39 CNXK_BPHY_CGX_ETH_LINK_SPEED_2HG,
40 CNXK_BPHY_CGX_ETH_LINK_SPEED_5G,
41 CNXK_BPHY_CGX_ETH_LINK_SPEED_10G,
42 CNXK_BPHY_CGX_ETH_LINK_SPEED_20G,
43 CNXK_BPHY_CGX_ETH_LINK_SPEED_25G,
44 CNXK_BPHY_CGX_ETH_LINK_SPEED_40G,
45 CNXK_BPHY_CGX_ETH_LINK_SPEED_50G,
46 CNXK_BPHY_CGX_ETH_LINK_SPEED_80G,
47 CNXK_BPHY_CGX_ETH_LINK_SPEED_100G,
48 __CNXK_BPHY_CGX_ETH_LINK_SPEED_MAX
51 enum cnxk_bphy_cgx_eth_link_fec {
52 CNXK_BPHY_CGX_ETH_LINK_FEC_NONE,
53 CNXK_BPHY_CGX_ETH_LINK_FEC_BASE_R,
54 CNXK_BPHY_CGX_ETH_LINK_FEC_RS,
55 __CNXK_BPHY_CGX_ETH_LINK_FEC_MAX
58 enum cnxk_bphy_cgx_eth_link_mode {
59 CNXK_BPHY_CGX_ETH_LINK_MODE_SGMII_BIT,
60 CNXK_BPHY_CGX_ETH_LINK_MODE_1000_BASEX_BIT,
61 CNXK_BPHY_CGX_ETH_LINK_MODE_QSGMII_BIT,
62 CNXK_BPHY_CGX_ETH_LINK_MODE_10G_C2C_BIT,
63 CNXK_BPHY_CGX_ETH_LINK_MODE_10G_C2M_BIT,
64 CNXK_BPHY_CGX_ETH_LINK_MODE_10G_KR_BIT,
65 CNXK_BPHY_CGX_ETH_LINK_MODE_20G_C2C_BIT,
66 CNXK_BPHY_CGX_ETH_LINK_MODE_25G_C2C_BIT,
67 CNXK_BPHY_CGX_ETH_LINK_MODE_25G_C2M_BIT,
68 CNXK_BPHY_CGX_ETH_LINK_MODE_25G_2_C2C_BIT,
69 CNXK_BPHY_CGX_ETH_LINK_MODE_25G_CR_BIT,
70 CNXK_BPHY_CGX_ETH_LINK_MODE_25G_KR_BIT,
71 CNXK_BPHY_CGX_ETH_LINK_MODE_40G_C2C_BIT,
72 CNXK_BPHY_CGX_ETH_LINK_MODE_40G_C2M_BIT,
73 CNXK_BPHY_CGX_ETH_LINK_MODE_40G_CR4_BIT,
74 CNXK_BPHY_CGX_ETH_LINK_MODE_40G_KR4_BIT,
75 CNXK_BPHY_CGX_ETH_LINK_MODE_40GAUI_C2C_BIT,
76 CNXK_BPHY_CGX_ETH_LINK_MODE_50G_C2C_BIT,
77 CNXK_BPHY_CGX_ETH_LINK_MODE_50G_C2M_BIT,
78 CNXK_BPHY_CGX_ETH_LINK_MODE_50G_4_C2C_BIT,
79 CNXK_BPHY_CGX_ETH_LINK_MODE_50G_CR_BIT,
80 CNXK_BPHY_CGX_ETH_LINK_MODE_50G_KR_BIT,
81 CNXK_BPHY_CGX_ETH_LINK_MODE_80GAUI_C2C_BIT,
82 CNXK_BPHY_CGX_ETH_LINK_MODE_100G_C2C_BIT,
83 CNXK_BPHY_CGX_ETH_LINK_MODE_100G_C2M_BIT,
84 CNXK_BPHY_CGX_ETH_LINK_MODE_100G_CR4_BIT,
85 CNXK_BPHY_CGX_ETH_LINK_MODE_100G_KR4_BIT,
86 __CNXK_BPHY_CGX_ETH_LINK_MODE_MAX
89 struct cnxk_bphy_cgx_msg_link_mode {
92 enum cnxk_bphy_cgx_eth_link_speed speed;
93 enum cnxk_bphy_cgx_eth_link_mode mode;
96 struct cnxk_bphy_cgx_msg_link_info {
99 enum cnxk_bphy_cgx_eth_link_speed speed;
101 enum cnxk_bphy_cgx_eth_link_fec fec;
102 enum cnxk_bphy_cgx_eth_link_mode mode;
105 struct cnxk_bphy_cgx_msg_set_link_state {
106 bool state; /* up or down */
109 struct cnxk_bphy_cgx_msg {
110 enum cnxk_bphy_cgx_msg_type type;
112 * data depends on message type and whether
113 * it's a request or a response
118 #define CNXK_BPHY_DEF_QUEUE 0
120 typedef void (*cnxk_bphy_intr_handler_t)(int irq_num, void *isr_data);
122 struct cnxk_bphy_mem {
123 struct rte_mem_resource res0;
124 struct rte_mem_resource res2;
127 enum cnxk_bphy_irq_msg_type {
128 CNXK_BPHY_IRQ_MSG_TYPE_INIT,
129 CNXK_BPHY_IRQ_MSG_TYPE_FINI,
130 CNXK_BPHY_IRQ_MSG_TYPE_REGISTER,
131 CNXK_BPHY_IRQ_MSG_TYPE_UNREGISTER,
132 CNXK_BPHY_IRQ_MSG_TYPE_MEM_GET,
133 CNXK_BPHY_MSG_TYPE_NPA_PF_FUNC,
134 CNXK_BPHY_MSG_TYPE_SSO_PF_FUNC,
137 struct cnxk_bphy_irq_msg {
138 enum cnxk_bphy_irq_msg_type type;
140 * The data field, depending on message type, may point to
141 * - (enq) full struct cnxk_bphy_irq_info for registration request
142 * - (enq) struct cnxk_bphy_irq_info with irq_num set for unregistration
143 * - (deq) struct cnxk_bphy_mem for memory range request response
149 struct cnxk_bphy_irq_info {
151 cnxk_bphy_intr_handler_t handler;
156 static __rte_always_inline int
157 __rte_pmd_bphy_enq_deq(uint16_t dev_id, unsigned int queue, void *req,
158 void *rsp, size_t rsp_size)
160 struct rte_rawdev_buf *bufs[1];
161 struct rte_rawdev_buf buf;
165 q = (void *)(size_t)queue;
169 ret = rte_rawdev_enqueue_buffers(dev_id, bufs, RTE_DIM(bufs), q);
172 if (ret != RTE_DIM(bufs))
178 ret = rte_rawdev_dequeue_buffers(dev_id, bufs, RTE_DIM(bufs), q);
181 if (ret != RTE_DIM(bufs))
184 rte_memcpy(rsp, buf.buf_addr, rsp_size);
185 rte_free(buf.buf_addr);
190 static __rte_always_inline int
191 rte_pmd_bphy_intr_init(uint16_t dev_id)
193 struct cnxk_bphy_irq_msg msg = {
194 .type = CNXK_BPHY_IRQ_MSG_TYPE_INIT,
197 return __rte_pmd_bphy_enq_deq(dev_id, CNXK_BPHY_DEF_QUEUE, &msg,
201 static __rte_always_inline int
202 rte_pmd_bphy_intr_fini(uint16_t dev_id)
204 struct cnxk_bphy_irq_msg msg = {
205 .type = CNXK_BPHY_IRQ_MSG_TYPE_FINI,
208 return __rte_pmd_bphy_enq_deq(dev_id, CNXK_BPHY_DEF_QUEUE, &msg,
212 static __rte_always_inline int
213 rte_pmd_bphy_intr_register(uint16_t dev_id, int irq_num,
214 cnxk_bphy_intr_handler_t handler, void *data,
217 struct cnxk_bphy_irq_info info = {
223 struct cnxk_bphy_irq_msg msg = {
224 .type = CNXK_BPHY_IRQ_MSG_TYPE_REGISTER,
228 return __rte_pmd_bphy_enq_deq(dev_id, CNXK_BPHY_DEF_QUEUE, &msg,
232 static __rte_always_inline int
233 rte_pmd_bphy_intr_unregister(uint16_t dev_id, int irq_num)
235 struct cnxk_bphy_irq_info info = {
238 struct cnxk_bphy_irq_msg msg = {
239 .type = CNXK_BPHY_IRQ_MSG_TYPE_UNREGISTER,
243 return __rte_pmd_bphy_enq_deq(dev_id, CNXK_BPHY_DEF_QUEUE, &msg,
247 static __rte_always_inline int
248 rte_pmd_bphy_intr_mem_get(uint16_t dev_id, struct cnxk_bphy_mem *mem)
250 struct cnxk_bphy_irq_msg msg = {
251 .type = CNXK_BPHY_IRQ_MSG_TYPE_MEM_GET,
254 return __rte_pmd_bphy_enq_deq(dev_id, CNXK_BPHY_DEF_QUEUE, &msg,
258 static __rte_always_inline int
259 rte_pmd_bphy_npa_pf_func_get(uint16_t dev_id, uint16_t *pf_func)
261 struct cnxk_bphy_irq_msg msg = {
262 .type = CNXK_BPHY_MSG_TYPE_NPA_PF_FUNC,
265 return __rte_pmd_bphy_enq_deq(dev_id, CNXK_BPHY_DEF_QUEUE, &msg,
266 pf_func, sizeof(*pf_func));
269 static __rte_always_inline int
270 rte_pmd_bphy_sso_pf_func_get(uint16_t dev_id, uint16_t *pf_func)
272 struct cnxk_bphy_irq_msg msg = {
273 .type = CNXK_BPHY_MSG_TYPE_SSO_PF_FUNC,
276 return __rte_pmd_bphy_enq_deq(dev_id, CNXK_BPHY_DEF_QUEUE, &msg,
277 pf_func, sizeof(*pf_func));
280 static __rte_always_inline int
281 rte_pmd_bphy_cgx_get_link_info(uint16_t dev_id, uint16_t lmac,
282 struct cnxk_bphy_cgx_msg_link_info *info)
284 struct cnxk_bphy_cgx_msg msg = {
285 .type = CNXK_BPHY_CGX_MSG_TYPE_GET_LINKINFO,
288 return __rte_pmd_bphy_enq_deq(dev_id, lmac, &msg, info, sizeof(*info));
291 static __rte_always_inline int
292 rte_pmd_bphy_cgx_intlbk_disable(uint16_t dev_id, uint16_t lmac)
294 struct cnxk_bphy_cgx_msg msg = {
295 .type = CNXK_BPHY_CGX_MSG_TYPE_INTLBK_DISABLE,
298 return __rte_pmd_bphy_enq_deq(dev_id, lmac, &msg, NULL, 0);
301 static __rte_always_inline int
302 rte_pmd_bphy_cgx_intlbk_enable(uint16_t dev_id, uint16_t lmac)
304 struct cnxk_bphy_cgx_msg msg = {
305 .type = CNXK_BPHY_CGX_MSG_TYPE_INTLBK_ENABLE,
308 return __rte_pmd_bphy_enq_deq(dev_id, lmac, &msg, NULL, 0);
311 static __rte_always_inline int
312 rte_pmd_bphy_cgx_ptp_rx_disable(uint16_t dev_id, uint16_t lmac)
314 struct cnxk_bphy_cgx_msg msg = {
315 .type = CNXK_BPHY_CGX_MSG_TYPE_PTP_RX_DISABLE,
318 return __rte_pmd_bphy_enq_deq(dev_id, lmac, &msg, NULL, 0);
321 static __rte_always_inline int
322 rte_pmd_bphy_cgx_ptp_rx_enable(uint16_t dev_id, uint16_t lmac)
324 struct cnxk_bphy_cgx_msg msg = {
325 .type = CNXK_BPHY_CGX_MSG_TYPE_PTP_RX_ENABLE,
328 return __rte_pmd_bphy_enq_deq(dev_id, lmac, &msg, NULL, 0);
331 static __rte_always_inline int
332 rte_pmd_bphy_cgx_set_link_mode(uint16_t dev_id, uint16_t lmac,
333 struct cnxk_bphy_cgx_msg_link_mode *mode)
335 struct cnxk_bphy_cgx_msg msg = {
336 .type = CNXK_BPHY_CGX_MSG_TYPE_SET_LINK_MODE,
340 return __rte_pmd_bphy_enq_deq(dev_id, lmac, &msg, NULL, 0);
343 static __rte_always_inline int
344 rte_pmd_bphy_cgx_set_link_state(uint16_t dev_id, uint16_t lmac, bool up)
346 struct cnxk_bphy_cgx_msg_set_link_state state = {
349 struct cnxk_bphy_cgx_msg msg = {
350 .type = CNXK_BPHY_CGX_MSG_TYPE_SET_LINK_STATE,
354 return __rte_pmd_bphy_enq_deq(dev_id, lmac, &msg, NULL, 0);
357 static __rte_always_inline int
358 rte_pmd_bphy_cgx_start_rxtx(uint16_t dev_id, uint16_t lmac)
360 struct cnxk_bphy_cgx_msg msg = {
361 .type = CNXK_BPHY_CGX_MSG_TYPE_START_RXTX,
364 return __rte_pmd_bphy_enq_deq(dev_id, lmac, &msg, NULL, 0);
367 static __rte_always_inline int
368 rte_pmd_bphy_cgx_stop_rxtx(uint16_t dev_id, uint16_t lmac)
370 struct cnxk_bphy_cgx_msg msg = {
371 .type = CNXK_BPHY_CGX_MSG_TYPE_STOP_RXTX,
374 return __rte_pmd_bphy_enq_deq(dev_id, lmac, &msg, NULL, 0);
377 static __rte_always_inline int
378 rte_pmd_bphy_cgx_get_supported_fec(uint16_t dev_id, uint16_t lmac,
379 enum cnxk_bphy_cgx_eth_link_fec *fec)
381 struct cnxk_bphy_cgx_msg msg = {
382 .type = CNXK_BPHY_CGX_MSG_TYPE_GET_SUPPORTED_FEC,
385 return __rte_pmd_bphy_enq_deq(dev_id, lmac, &msg, fec, sizeof(*fec));
388 static __rte_always_inline int
389 rte_pmd_bphy_cgx_set_fec(uint16_t dev_id, uint16_t lmac,
390 enum cnxk_bphy_cgx_eth_link_fec fec)
392 struct cnxk_bphy_cgx_msg msg = {
393 .type = CNXK_BPHY_CGX_MSG_TYPE_SET_FEC,
397 return __rte_pmd_bphy_enq_deq(dev_id, lmac, &msg, NULL, 0);
404 #endif /* _CNXK_BPHY_H_ */