1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(C) 2021 Marvell.
8 #include <rte_memcpy.h>
10 #include "cnxk_bphy_irq.h"
12 enum cnxk_bphy_cgx_msg_type {
13 CNXK_BPHY_CGX_MSG_TYPE_GET_LINKINFO,
14 CNXK_BPHY_CGX_MSG_TYPE_INTLBK_DISABLE,
15 CNXK_BPHY_CGX_MSG_TYPE_INTLBK_ENABLE,
16 CNXK_BPHY_CGX_MSG_TYPE_PTP_RX_DISABLE,
17 CNXK_BPHY_CGX_MSG_TYPE_PTP_RX_ENABLE,
18 CNXK_BPHY_CGX_MSG_TYPE_SET_LINK_MODE,
19 CNXK_BPHY_CGX_MSG_TYPE_SET_LINK_STATE,
20 CNXK_BPHY_CGX_MSG_TYPE_START_RXTX,
21 CNXK_BPHY_CGX_MSG_TYPE_STOP_RXTX,
22 CNXK_BPHY_CGX_MSG_TYPE_GET_SUPPORTED_FEC,
23 CNXK_BPHY_CGX_MSG_TYPE_SET_FEC,
26 enum cnxk_bphy_cgx_eth_link_speed {
27 CNXK_BPHY_CGX_ETH_LINK_SPEED_NONE,
28 CNXK_BPHY_CGX_ETH_LINK_SPEED_10M,
29 CNXK_BPHY_CGX_ETH_LINK_SPEED_100M,
30 CNXK_BPHY_CGX_ETH_LINK_SPEED_1G,
31 CNXK_BPHY_CGX_ETH_LINK_SPEED_2HG,
32 CNXK_BPHY_CGX_ETH_LINK_SPEED_5G,
33 CNXK_BPHY_CGX_ETH_LINK_SPEED_10G,
34 CNXK_BPHY_CGX_ETH_LINK_SPEED_20G,
35 CNXK_BPHY_CGX_ETH_LINK_SPEED_25G,
36 CNXK_BPHY_CGX_ETH_LINK_SPEED_40G,
37 CNXK_BPHY_CGX_ETH_LINK_SPEED_50G,
38 CNXK_BPHY_CGX_ETH_LINK_SPEED_80G,
39 CNXK_BPHY_CGX_ETH_LINK_SPEED_100G,
40 __CNXK_BPHY_CGX_ETH_LINK_SPEED_MAX
43 enum cnxk_bphy_cgx_eth_link_fec {
44 CNXK_BPHY_CGX_ETH_LINK_FEC_NONE,
45 CNXK_BPHY_CGX_ETH_LINK_FEC_BASE_R,
46 CNXK_BPHY_CGX_ETH_LINK_FEC_RS,
47 __CNXK_BPHY_CGX_ETH_LINK_FEC_MAX
50 enum cnxk_bphy_cgx_eth_link_mode {
51 CNXK_BPHY_CGX_ETH_LINK_MODE_SGMII_BIT,
52 CNXK_BPHY_CGX_ETH_LINK_MODE_1000_BASEX_BIT,
53 CNXK_BPHY_CGX_ETH_LINK_MODE_QSGMII_BIT,
54 CNXK_BPHY_CGX_ETH_LINK_MODE_10G_C2C_BIT,
55 CNXK_BPHY_CGX_ETH_LINK_MODE_10G_C2M_BIT,
56 CNXK_BPHY_CGX_ETH_LINK_MODE_10G_KR_BIT,
57 CNXK_BPHY_CGX_ETH_LINK_MODE_20G_C2C_BIT,
58 CNXK_BPHY_CGX_ETH_LINK_MODE_25G_C2C_BIT,
59 CNXK_BPHY_CGX_ETH_LINK_MODE_25G_C2M_BIT,
60 CNXK_BPHY_CGX_ETH_LINK_MODE_25G_2_C2C_BIT,
61 CNXK_BPHY_CGX_ETH_LINK_MODE_25G_CR_BIT,
62 CNXK_BPHY_CGX_ETH_LINK_MODE_25G_KR_BIT,
63 CNXK_BPHY_CGX_ETH_LINK_MODE_40G_C2C_BIT,
64 CNXK_BPHY_CGX_ETH_LINK_MODE_40G_C2M_BIT,
65 CNXK_BPHY_CGX_ETH_LINK_MODE_40G_CR4_BIT,
66 CNXK_BPHY_CGX_ETH_LINK_MODE_40G_KR4_BIT,
67 CNXK_BPHY_CGX_ETH_LINK_MODE_40GAUI_C2C_BIT,
68 CNXK_BPHY_CGX_ETH_LINK_MODE_50G_C2C_BIT,
69 CNXK_BPHY_CGX_ETH_LINK_MODE_50G_C2M_BIT,
70 CNXK_BPHY_CGX_ETH_LINK_MODE_50G_4_C2C_BIT,
71 CNXK_BPHY_CGX_ETH_LINK_MODE_50G_CR_BIT,
72 CNXK_BPHY_CGX_ETH_LINK_MODE_50G_KR_BIT,
73 CNXK_BPHY_CGX_ETH_LINK_MODE_80GAUI_C2C_BIT,
74 CNXK_BPHY_CGX_ETH_LINK_MODE_100G_C2C_BIT,
75 CNXK_BPHY_CGX_ETH_LINK_MODE_100G_C2M_BIT,
76 CNXK_BPHY_CGX_ETH_LINK_MODE_100G_CR4_BIT,
77 CNXK_BPHY_CGX_ETH_LINK_MODE_100G_KR4_BIT,
78 __CNXK_BPHY_CGX_ETH_LINK_MODE_MAX
81 struct cnxk_bphy_cgx_msg_link_mode {
84 enum cnxk_bphy_cgx_eth_link_speed speed;
85 enum cnxk_bphy_cgx_eth_link_mode mode;
88 struct cnxk_bphy_cgx_msg_link_info {
91 enum cnxk_bphy_cgx_eth_link_speed speed;
93 enum cnxk_bphy_cgx_eth_link_fec fec;
94 enum cnxk_bphy_cgx_eth_link_mode mode;
97 struct cnxk_bphy_cgx_msg_set_link_state {
98 bool state; /* up or down */
101 struct cnxk_bphy_cgx_msg {
102 enum cnxk_bphy_cgx_msg_type type;
104 * data depends on message type and whether
105 * it's a request or a response
110 #define cnxk_bphy_mem bphy_mem
111 #define CNXK_BPHY_DEF_QUEUE 0
113 enum cnxk_bphy_irq_msg_type {
114 CNXK_BPHY_IRQ_MSG_TYPE_INIT,
115 CNXK_BPHY_IRQ_MSG_TYPE_FINI,
116 CNXK_BPHY_IRQ_MSG_TYPE_REGISTER,
117 CNXK_BPHY_IRQ_MSG_TYPE_UNREGISTER,
118 CNXK_BPHY_IRQ_MSG_TYPE_MEM_GET,
119 CNXK_BPHY_MSG_TYPE_NPA_PF_FUNC,
120 CNXK_BPHY_MSG_TYPE_SSO_PF_FUNC,
123 struct cnxk_bphy_irq_msg {
124 enum cnxk_bphy_irq_msg_type type;
126 * The data field, depending on message type, may point to
127 * - (enq) full struct cnxk_bphy_irq_info for registration request
128 * - (enq) struct cnxk_bphy_irq_info with irq_num set for unregistration
129 * - (deq) struct cnxk_bphy_mem for memory range request response
135 struct cnxk_bphy_irq_info {
137 cnxk_bphy_intr_handler_t handler;
142 static __rte_always_inline int
143 __rte_pmd_bphy_enq_deq(uint16_t dev_id, unsigned int queue, void *req,
144 void *rsp, size_t rsp_size)
146 struct rte_rawdev_buf *bufs[1];
147 struct rte_rawdev_buf buf;
151 q = (void *)(size_t)queue;
155 ret = rte_rawdev_enqueue_buffers(dev_id, bufs, RTE_DIM(bufs), q);
158 if (ret != RTE_DIM(bufs))
164 ret = rte_rawdev_dequeue_buffers(dev_id, bufs, RTE_DIM(bufs), q);
167 if (ret != RTE_DIM(bufs))
170 rte_memcpy(rsp, buf.buf_addr, rsp_size);
171 rte_free(buf.buf_addr);
176 static __rte_always_inline int
177 rte_pmd_bphy_intr_init(uint16_t dev_id)
179 struct cnxk_bphy_irq_msg msg = {
180 .type = CNXK_BPHY_IRQ_MSG_TYPE_INIT,
183 return __rte_pmd_bphy_enq_deq(dev_id, CNXK_BPHY_DEF_QUEUE, &msg,
187 static __rte_always_inline int
188 rte_pmd_bphy_intr_fini(uint16_t dev_id)
190 struct cnxk_bphy_irq_msg msg = {
191 .type = CNXK_BPHY_IRQ_MSG_TYPE_FINI,
194 return __rte_pmd_bphy_enq_deq(dev_id, CNXK_BPHY_DEF_QUEUE, &msg,
198 static __rte_always_inline int
199 rte_pmd_bphy_intr_register(uint16_t dev_id, int irq_num,
200 cnxk_bphy_intr_handler_t handler, void *data,
203 struct cnxk_bphy_irq_info info = {
209 struct cnxk_bphy_irq_msg msg = {
210 .type = CNXK_BPHY_IRQ_MSG_TYPE_REGISTER,
214 return __rte_pmd_bphy_enq_deq(dev_id, CNXK_BPHY_DEF_QUEUE, &msg,
218 static __rte_always_inline int
219 rte_pmd_bphy_intr_unregister(uint16_t dev_id, int irq_num)
221 struct cnxk_bphy_irq_info info = {
224 struct cnxk_bphy_irq_msg msg = {
225 .type = CNXK_BPHY_IRQ_MSG_TYPE_UNREGISTER,
229 return __rte_pmd_bphy_enq_deq(dev_id, CNXK_BPHY_DEF_QUEUE, &msg,
233 static __rte_always_inline int
234 rte_pmd_bphy_intr_mem_get(uint16_t dev_id, struct cnxk_bphy_mem *mem)
236 struct cnxk_bphy_irq_msg msg = {
237 .type = CNXK_BPHY_IRQ_MSG_TYPE_MEM_GET,
240 return __rte_pmd_bphy_enq_deq(dev_id, CNXK_BPHY_DEF_QUEUE, &msg,
244 static __rte_always_inline int
245 rte_pmd_bphy_npa_pf_func_get(uint16_t dev_id, uint16_t *pf_func)
247 struct cnxk_bphy_irq_msg msg = {
248 .type = CNXK_BPHY_MSG_TYPE_NPA_PF_FUNC,
251 return __rte_pmd_bphy_enq_deq(dev_id, CNXK_BPHY_DEF_QUEUE, &msg,
252 pf_func, sizeof(*pf_func));
255 static __rte_always_inline int
256 rte_pmd_bphy_sso_pf_func_get(uint16_t dev_id, uint16_t *pf_func)
258 struct cnxk_bphy_irq_msg msg = {
259 .type = CNXK_BPHY_MSG_TYPE_SSO_PF_FUNC,
262 return __rte_pmd_bphy_enq_deq(dev_id, CNXK_BPHY_DEF_QUEUE, &msg,
263 pf_func, sizeof(*pf_func));
266 static __rte_always_inline int
267 rte_pmd_bphy_cgx_get_link_info(uint16_t dev_id, uint16_t lmac,
268 struct cnxk_bphy_cgx_msg_link_info *info)
270 struct cnxk_bphy_cgx_msg msg = {
271 .type = CNXK_BPHY_CGX_MSG_TYPE_GET_LINKINFO,
274 return __rte_pmd_bphy_enq_deq(dev_id, lmac, &msg, info, sizeof(*info));
277 static __rte_always_inline int
278 rte_pmd_bphy_cgx_intlbk_disable(uint16_t dev_id, uint16_t lmac)
280 struct cnxk_bphy_cgx_msg msg = {
281 .type = CNXK_BPHY_CGX_MSG_TYPE_INTLBK_DISABLE,
284 return __rte_pmd_bphy_enq_deq(dev_id, lmac, &msg, NULL, 0);
287 static __rte_always_inline int
288 rte_pmd_bphy_cgx_intlbk_enable(uint16_t dev_id, uint16_t lmac)
290 struct cnxk_bphy_cgx_msg msg = {
291 .type = CNXK_BPHY_CGX_MSG_TYPE_INTLBK_ENABLE,
294 return __rte_pmd_bphy_enq_deq(dev_id, lmac, &msg, NULL, 0);
297 static __rte_always_inline int
298 rte_pmd_bphy_cgx_ptp_rx_disable(uint16_t dev_id, uint16_t lmac)
300 struct cnxk_bphy_cgx_msg msg = {
301 .type = CNXK_BPHY_CGX_MSG_TYPE_PTP_RX_DISABLE,
304 return __rte_pmd_bphy_enq_deq(dev_id, lmac, &msg, NULL, 0);
307 static __rte_always_inline int
308 rte_pmd_bphy_cgx_ptp_rx_enable(uint16_t dev_id, uint16_t lmac)
310 struct cnxk_bphy_cgx_msg msg = {
311 .type = CNXK_BPHY_CGX_MSG_TYPE_PTP_RX_ENABLE,
314 return __rte_pmd_bphy_enq_deq(dev_id, lmac, &msg, NULL, 0);
317 static __rte_always_inline int
318 rte_pmd_bphy_cgx_set_link_mode(uint16_t dev_id, uint16_t lmac,
319 struct cnxk_bphy_cgx_msg_link_mode *mode)
321 struct cnxk_bphy_cgx_msg msg = {
322 .type = CNXK_BPHY_CGX_MSG_TYPE_SET_LINK_MODE,
326 return __rte_pmd_bphy_enq_deq(dev_id, lmac, &msg, NULL, 0);
329 static __rte_always_inline int
330 rte_pmd_bphy_cgx_set_link_state(uint16_t dev_id, uint16_t lmac, bool up)
332 struct cnxk_bphy_cgx_msg_set_link_state state = {
335 struct cnxk_bphy_cgx_msg msg = {
336 .type = CNXK_BPHY_CGX_MSG_TYPE_SET_LINK_STATE,
340 return __rte_pmd_bphy_enq_deq(dev_id, lmac, &msg, NULL, 0);
343 static __rte_always_inline int
344 rte_pmd_bphy_cgx_start_rxtx(uint16_t dev_id, uint16_t lmac)
346 struct cnxk_bphy_cgx_msg msg = {
347 .type = CNXK_BPHY_CGX_MSG_TYPE_START_RXTX,
350 return __rte_pmd_bphy_enq_deq(dev_id, lmac, &msg, NULL, 0);
353 static __rte_always_inline int
354 rte_pmd_bphy_cgx_stop_rxtx(uint16_t dev_id, uint16_t lmac)
356 struct cnxk_bphy_cgx_msg msg = {
357 .type = CNXK_BPHY_CGX_MSG_TYPE_STOP_RXTX,
360 return __rte_pmd_bphy_enq_deq(dev_id, lmac, &msg, NULL, 0);
363 static __rte_always_inline int
364 rte_pmd_bphy_cgx_get_supported_fec(uint16_t dev_id, uint16_t lmac,
365 enum cnxk_bphy_cgx_eth_link_fec *fec)
367 struct cnxk_bphy_cgx_msg msg = {
368 .type = CNXK_BPHY_CGX_MSG_TYPE_GET_SUPPORTED_FEC,
371 return __rte_pmd_bphy_enq_deq(dev_id, lmac, &msg, fec, sizeof(*fec));
374 static __rte_always_inline int
375 rte_pmd_bphy_cgx_set_fec(uint16_t dev_id, uint16_t lmac,
376 enum cnxk_bphy_cgx_eth_link_fec fec)
378 struct cnxk_bphy_cgx_msg msg = {
379 .type = CNXK_BPHY_CGX_MSG_TYPE_SET_FEC,
383 return __rte_pmd_bphy_enq_deq(dev_id, lmac, &msg, NULL, 0);
386 #endif /* _CNXK_BPHY_H_ */