1 /* SPDX-License-Identifier: BSD-3-Clause
5 #ifndef __DPAA2_QDMA_H__
6 #define __DPAA2_QDMA_H__
11 #define DPAA2_QDMA_MAX_FLE 3
12 #define DPAA2_QDMA_MAX_SDD 2
14 #define DPAA2_DPDMAI_MAX_QUEUES 8
16 /** FLE pool size: 3 Frame list + 2 source/destination descriptor */
17 #define QDMA_FLE_POOL_SIZE (sizeof(struct qdma_io_meta) + \
18 sizeof(struct qbman_fle) * DPAA2_QDMA_MAX_FLE + \
19 sizeof(struct qdma_sdd) * DPAA2_QDMA_MAX_SDD)
20 /** FLE pool cache size */
21 #define QDMA_FLE_CACHE_SIZE(_num) (_num/(RTE_MAX_LCORE * 2))
23 /** Notification by FQD_CTX[fqid] */
24 #define QDMA_SER_CTX (1 << 8)
27 * Source descriptor command read transaction type for RBP=0:
28 * coherent copy of cacheable memory
30 #define DPAA2_SET_SDD_RD_COHERENT(sdd) ((sdd)->cmd = (0xb << 28))
32 * Destination descriptor command write transaction type for RBP=0:
33 * coherent copy of cacheable memory
35 #define DPAA2_SET_SDD_WR_COHERENT(sdd) ((sdd)->cmd = (0x6 << 28))
37 /** Maximum possible H/W Queues on each core */
38 #define MAX_HW_QUEUE_PER_CORE 64
41 * In case of Virtual Queue mode, this specifies the number of
42 * dequeue the 'qdma_vq_dequeue/multi' API does from the H/W Queue
43 * in case there is no job present on the Virtual Queue ring.
45 #define QDMA_DEQUEUE_BUDGET 64
48 * Represents a QDMA device.
49 * A single QDMA device exists which is combination of multiple DPDMAI rawdev's.
52 /** total number of hw queues. */
53 uint16_t num_hw_queues;
55 * Maximum number of hw queues to be alocated per core.
56 * This is limited by MAX_HW_QUEUE_PER_CORE
58 uint16_t max_hw_queues_per_core;
59 /** Maximum number of VQ's */
61 /** mode of operation - physical(h/w) or virtual */
63 /** Device state - started or stopped */
65 /** FLE pool for the device */
66 struct rte_mempool *fle_pool;
69 /** A lock to QDMA device whenever required */
73 /** Represents a QDMA H/W queue */
74 struct qdma_hw_queue {
75 /** Pointer to Next instance */
76 TAILQ_ENTRY(qdma_hw_queue) next;
77 /** DPDMAI device to communicate with HW */
78 struct dpaa2_dpdmai_dev *dpdmai_dev;
79 /** queue ID to communicate with HW */
81 /** Associated lcore id */
83 /** Number of users of this hw queue */
87 /** Represents a QDMA virtual queue */
88 struct qdma_virt_queue {
89 /** Status ring of the virtual queue */
90 struct rte_ring *status_ring;
91 /** Associated hw queue */
92 struct qdma_hw_queue *hw_queue;
93 /** Associated lcore id */
95 /** States if this vq is in use or not */
97 /** States if this vq has exclusively associated hw queue */
98 uint8_t exclusive_hw_queue;
99 /* Total number of enqueues on this VQ */
100 uint64_t num_enqueues;
101 /* Total number of dequeues from this VQ */
102 uint64_t num_dequeues;
105 /** Represents a QDMA per core hw queues allocation in virtual mode */
106 struct qdma_per_core_info {
107 /** list for allocated hw queues */
108 struct qdma_hw_queue *hw_queues[MAX_HW_QUEUE_PER_CORE];
109 /* Number of hw queues allocated for this core */
110 uint16_t num_hw_queues;
113 /** Metadata which is stored with each operation */
114 struct qdma_io_meta {
116 * Context which is stored in the FLE pool (just before the FLE).
117 * QDMA job is stored as a this context as a part of metadata.
120 /** VQ ID is stored as a part of metadata of the enqueue command */
124 /** Source/Destination Descriptor */
127 /** Stride configuration */
129 /** Route-by-port command */
132 } __attribute__((__packed__));
134 /** Represents a DPDMAI raw device */
135 struct dpaa2_dpdmai_dev {
136 /** Pointer to Next device instance */
137 TAILQ_ENTRY(dpaa2_qdma_device) next;
138 /** handle to DPDMAI object */
139 struct fsl_mc_io dpdmai;
140 /** HW ID for DPDMAI object */
142 /** Tocken of this device */
144 /** Number of queue in this DPDMAI device */
147 struct dpaa2_queue rx_queue[DPAA2_DPDMAI_MAX_QUEUES];
149 struct dpaa2_queue tx_queue[DPAA2_DPDMAI_MAX_QUEUES];
152 #endif /* __DPAA2_QDMA_H__ */