1 /* SPDX-License-Identifier: BSD-3-Clause
5 #ifndef __DPAA2_QDMA_H__
6 #define __DPAA2_QDMA_H__
11 #define DPAA2_QDMA_MAX_FLE 3
12 #define DPAA2_QDMA_MAX_SDD 2
14 /** FLE pool size: 3 Frame list + 2 source/destination descriptor */
15 #define QDMA_FLE_POOL_SIZE (sizeof(struct qdma_io_meta) + \
16 sizeof(struct qbman_fle) * DPAA2_QDMA_MAX_FLE + \
17 sizeof(struct qdma_sdd) * DPAA2_QDMA_MAX_SDD)
18 /** FLE pool cache size */
19 #define QDMA_FLE_CACHE_SIZE(_num) (_num/(RTE_MAX_LCORE * 2))
21 /** Notification by FQD_CTX[fqid] */
22 #define QDMA_SER_CTX (1 << 8)
25 * Source descriptor command read transaction type for RBP=0:
26 * coherent copy of cacheable memory
28 #define DPAA2_SET_SDD_RD_COHERENT(sdd) ((sdd)->cmd = (0xb << 28))
30 * Destination descriptor command write transaction type for RBP=0:
31 * coherent copy of cacheable memory
33 #define DPAA2_SET_SDD_WR_COHERENT(sdd) ((sdd)->cmd = (0x6 << 28))
35 /** Maximum possible H/W Queues on each core */
36 #define MAX_HW_QUEUE_PER_CORE 64
39 * In case of Virtual Queue mode, this specifies the number of
40 * dequeue the 'qdma_vq_dequeue/multi' API does from the H/W Queue
41 * in case there is no job present on the Virtual Queue ring.
43 #define QDMA_DEQUEUE_BUDGET 64
46 * Represents a QDMA device.
47 * A single QDMA device exists which is combination of multiple DPDMAI rawdev's.
50 /** total number of hw queues. */
51 uint16_t num_hw_queues;
53 * Maximum number of hw queues to be alocated per core.
54 * This is limited by MAX_HW_QUEUE_PER_CORE
56 uint16_t max_hw_queues_per_core;
57 /** Maximum number of VQ's */
59 /** mode of operation - physical(h/w) or virtual */
61 /** Device state - started or stopped */
63 /** FLE pool for the device */
64 struct rte_mempool *fle_pool;
67 /** A lock to QDMA device whenever required */
71 /** Represents a QDMA H/W queue */
72 struct qdma_hw_queue {
73 /** Pointer to Next instance */
74 TAILQ_ENTRY(qdma_hw_queue) next;
75 /** DPDMAI device to communicate with HW */
76 struct dpaa2_dpdmai_dev *dpdmai_dev;
77 /** queue ID to communicate with HW */
79 /** Associated lcore id */
81 /** Number of users of this hw queue */
85 /** Represents a QDMA virtual queue */
86 struct qdma_virt_queue {
87 /** Status ring of the virtual queue */
88 struct rte_ring *status_ring;
89 /** Associated hw queue */
90 struct qdma_hw_queue *hw_queue;
91 /** Associated lcore id */
93 /** States if this vq is in use or not */
95 /** States if this vq has exclusively associated hw queue */
96 uint8_t exclusive_hw_queue;
97 /* Total number of enqueues on this VQ */
98 uint64_t num_enqueues;
99 /* Total number of dequeues from this VQ */
100 uint64_t num_dequeues;
103 /** Represents a QDMA per core hw queues allocation in virtual mode */
104 struct qdma_per_core_info {
105 /** list for allocated hw queues */
106 struct qdma_hw_queue *hw_queues[MAX_HW_QUEUE_PER_CORE];
107 /* Number of hw queues allocated for this core */
108 uint16_t num_hw_queues;
111 /** Metadata which is stored with each operation */
112 struct qdma_io_meta {
114 * Context which is stored in the FLE pool (just before the FLE).
115 * QDMA job is stored as a this context as a part of metadata.
118 /** VQ ID is stored as a part of metadata of the enqueue command */
122 /** Source/Destination Descriptor */
125 /** Stride configuration */
127 /** Route-by-port command */
130 } __attribute__((__packed__));
132 /** Represents a DPDMAI raw device */
133 struct dpaa2_dpdmai_dev {
134 /** Pointer to Next device instance */
135 TAILQ_ENTRY(dpaa2_qdma_device) next;
136 /** handle to DPDMAI object */
137 struct fsl_mc_io dpdmai;
138 /** HW ID for DPDMAI object */
140 /** Tocken of this device */
142 /** Number of queue in this DPDMAI device */
145 struct dpaa2_queue rx_queue[DPDMAI_PRIO_NUM];
147 struct dpaa2_queue tx_queue[DPDMAI_PRIO_NUM];
150 #endif /* __DPAA2_QDMA_H__ */