1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2018-2020 NXP
5 #ifndef __DPAA2_QDMA_H__
6 #define __DPAA2_QDMA_H__
11 #define DPAA2_QDMA_MAX_FLE 3
12 #define DPAA2_QDMA_MAX_SDD 2
14 #define DPAA2_DPDMAI_MAX_QUEUES 8
16 /** FLE pool size: 3 Frame list + 2 source/destination descriptor */
17 #define QDMA_FLE_POOL_SIZE (sizeof(struct rte_qdma_job *) + \
18 sizeof(struct qbman_fle) * DPAA2_QDMA_MAX_FLE + \
19 sizeof(struct qdma_sdd) * DPAA2_QDMA_MAX_SDD)
21 #define QDMA_FLE_JOB_OFFSET 0
22 #define QDMA_FLE_FLE_OFFSET \
23 (QDMA_FLE_JOB_OFFSET + sizeof(struct rte_qdma_job *))
25 /** FLE pool cache size */
26 #define QDMA_FLE_CACHE_SIZE(_num) (_num/(RTE_MAX_LCORE * 2))
28 /** Notification by FQD_CTX[fqid] */
29 #define QDMA_SER_CTX (1 << 8)
30 #define DPAA2_RBP_MEM_RW 0x0
32 * Source descriptor command read transaction type for RBP=0:
33 * coherent copy of cacheable memory
35 #define DPAA2_COHERENT_NO_ALLOCATE_CACHE 0xb
36 #define DPAA2_LX2_COHERENT_NO_ALLOCATE_CACHE 0x7
38 * Destination descriptor command write transaction type for RBP=0:
39 * coherent copy of cacheable memory
41 #define DPAA2_COHERENT_ALLOCATE_CACHE 0x6
42 #define DPAA2_LX2_COHERENT_ALLOCATE_CACHE 0xb
44 /** Maximum possible H/W Queues on each core */
45 #define MAX_HW_QUEUE_PER_CORE 64
47 #define QDMA_RBP_UPPER_ADDRESS_MASK (0xfff0000000000)
49 * Represents a QDMA device.
50 * A single QDMA device exists which is combination of multiple DPDMAI rawdev's.
53 /** total number of hw queues. */
54 uint16_t num_hw_queues;
56 * Maximum number of hw queues to be alocated per core.
57 * This is limited by MAX_HW_QUEUE_PER_CORE
59 uint16_t max_hw_queues_per_core;
61 /** VQ's of this device */
62 struct qdma_virt_queue *vqs;
63 /** Maximum number of VQ's */
65 /** Device state - started or stopped */
67 /** FLE pool for the device */
68 struct rte_mempool *fle_pool;
71 /** A lock to QDMA device whenever required */
75 /** Represents a QDMA H/W queue */
76 struct qdma_hw_queue {
77 /** Pointer to Next instance */
78 TAILQ_ENTRY(qdma_hw_queue) next;
79 /** DPDMAI device to communicate with HW */
80 struct dpaa2_dpdmai_dev *dpdmai_dev;
81 /** queue ID to communicate with HW */
83 /** Associated lcore id */
85 /** Number of users of this hw queue */
89 struct qdma_virt_queue;
91 typedef uint16_t (qdma_get_job_t)(struct qdma_virt_queue *qdma_vq,
92 const struct qbman_fd *fd,
93 struct rte_qdma_job **job);
94 typedef int (qdma_set_fd_t)(struct qdma_virt_queue *qdma_vq,
96 struct rte_qdma_job *job);
98 typedef int (qdma_dequeue_multijob_t)(
99 struct qdma_virt_queue *qdma_vq,
101 struct rte_qdma_job **job,
104 typedef int (qdma_enqueue_multijob_t)(
105 struct qdma_virt_queue *qdma_vq,
106 struct rte_qdma_job **job,
109 /** Represents a QDMA virtual queue */
110 struct qdma_virt_queue {
111 /** Status ring of the virtual queue */
112 struct rte_ring *status_ring;
113 /** Associated hw queue */
114 struct qdma_hw_queue *hw_queue;
116 struct rte_qdma_rbp rbp;
117 /** Associated lcore id */
119 /** States if this vq is in use or not */
121 /** States if this vq has exclusively associated hw queue */
122 uint8_t exclusive_hw_queue;
123 /* Total number of enqueues on this VQ */
124 uint64_t num_enqueues;
125 /* Total number of dequeues from this VQ */
126 uint64_t num_dequeues;
130 qdma_set_fd_t *set_fd;
131 qdma_get_job_t *get_job;
133 qdma_dequeue_multijob_t *dequeue_job;
134 qdma_enqueue_multijob_t *enqueue_job;
137 /** Represents a QDMA per core hw queues allocation in virtual mode */
138 struct qdma_per_core_info {
139 /** list for allocated hw queues */
140 struct qdma_hw_queue *hw_queues[MAX_HW_QUEUE_PER_CORE];
141 /* Number of hw queues allocated for this core */
142 uint16_t num_hw_queues;
145 /** Source/Destination Descriptor */
148 /** Stride configuration */
150 /** Route-by-port command */
194 /** Represents a DPDMAI raw device */
195 struct dpaa2_dpdmai_dev {
196 /** Pointer to Next device instance */
197 TAILQ_ENTRY(dpaa2_qdma_device) next;
198 /** handle to DPDMAI object */
199 struct fsl_mc_io dpdmai;
200 /** HW ID for DPDMAI object */
202 /** Tocken of this device */
204 /** Number of queue in this DPDMAI device */
207 struct dpaa2_queue rx_queue[DPAA2_DPDMAI_MAX_QUEUES];
209 struct dpaa2_queue tx_queue[DPAA2_DPDMAI_MAX_QUEUES];
210 struct qdma_device *qdma_dev;
213 static inline struct qdma_device *
214 QDMA_DEV_OF_VQ(struct qdma_virt_queue *vq)
216 return vq->hw_queue->dpdmai_dev->qdma_dev;
219 #endif /* __DPAA2_QDMA_H__ */