1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2022 Intel Corporation
16 #include <rte_spinlock.h>
17 #include <rte_cycles.h>
18 #include <rte_bus_ifpga.h>
19 #include <rte_rawdev.h>
21 #include "ifpga_rawdev.h"
23 #define AFU_RAWDEV_MAX_DRVS 32
28 int (*init)(struct afu_rawdev *dev);
29 int (*config)(struct afu_rawdev *dev, void *config,
31 int (*start)(struct afu_rawdev *dev);
32 int (*stop)(struct afu_rawdev *dev);
33 int (*test)(struct afu_rawdev *dev);
34 int (*close)(struct afu_rawdev *dev);
35 int (*reset)(struct afu_rawdev *dev);
36 int (*dump)(struct afu_rawdev *dev, FILE *f);
39 struct afu_shared_data {
40 rte_spinlock_t lock; /* lock for multi-process access */
43 struct afu_rawdev_drv {
44 TAILQ_ENTRY(afu_rawdev_drv) next;
45 struct rte_afu_uuid uuid;
50 struct rte_rawdev *rawdev; /* point to parent raw device */
51 struct afu_shared_data *sd; /* shared data for multi-process */
52 struct afu_ops *ops; /* device operation functions */
53 int port; /* index of port the AFU attached */
54 void *addr; /* base address of AFU registers */
55 void *priv; /* private driver data */
58 static inline struct afu_rawdev *
59 afu_rawdev_get_priv(const struct rte_rawdev *rawdev)
61 return rawdev ? (struct afu_rawdev *)rawdev->dev_private : NULL;
64 #define CLS_TO_SIZE(n) ((n) << 6) /* get size of n cache lines */
65 #define SIZE_TO_CLS(s) ((s) >> 6) /* convert size to number of cache lines */
66 #define MHZ(f) ((f) * 1000000)
68 #define dsm_poll_timeout(addr, val, cond, invl, timeout) \
70 uint64_t __wait = 0; \
71 uint64_t __invl = (invl); \
72 uint64_t __timeout = (timeout); \
73 for (; __wait <= __timeout; __wait += __invl) { \
77 rte_delay_ms(__invl); \
82 void afu_pmd_register(struct afu_rawdev_drv *driver);
83 void afu_pmd_unregister(struct afu_rawdev_drv *driver);
85 #define AFU_PMD_REGISTER(drv)\
86 RTE_INIT(afupmdinitfunc_ ##drv)\
88 afu_pmd_register(&drv);\
95 #endif /* AFU_PMD_CORE_H */