drivers/raw/ifpga/afu_pmd_he_hssi.h

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2022 Intel Corporation
   3  */
   4
   5 #ifndef AFU_PMD_HE_HSSI_H
   6 #define AFU_PMD_HE_HSSI_H
   7
   8 #ifdef __cplusplus
   9 extern "C" {
  10 #endif
  11
  12 #include "afu_pmd_core.h"
  13 #include "rte_pmd_afu.h"
  14
  15 #define HE_HSSI_UUID_L    0xbb370242ac130002
  16 #define HE_HSSI_UUID_H    0x823c334c98bf11ea
  17 #define NUM_HE_HSSI_PORTS 8
  18
  19 /* HE-HSSI registers definition */
  20 #define TRAFFIC_CTRL_CMD    0x30
  21 #define TRAFFIC_CTRL_DATA   0x38
  22 #define TRAFFIC_CTRL_CH_SEL 0x40
  23 #define AFU_SCRATCHPAD      0x48
  24
  25 #define TG_NUM_PKT        0x3c00
  26 #define TG_PKT_LEN_TYPE   0x3c01
  27 #define TG_DATA_PATTERN   0x3c02
  28 #define TG_START_XFR      0x3c03
  29 #define TG_STOP_XFR       0x3c04
  30 #define TG_SRC_MAC_L      0x3c05
  31 #define TG_SRC_MAC_H      0x3c06
  32 #define TG_DST_MAC_L      0x3c07
  33 #define TG_DST_MAC_H      0x3c08
  34 #define TG_PKT_XFRD       0x3c09
  35 #define TG_NUM_RND_SEEDS  3
  36 #define TG_RANDOM_SEED(n) (0x3c0a + (n))
  37 #define TG_PKT_LEN        0x3c0d
  38
  39 #define TM_NUM_PKT        0x3d00
  40 #define TM_PKT_GOOD       0x3d01
  41 #define TM_PKT_BAD        0x3d02
  42 #define TM_BYTE_CNT0      0x3d03
  43 #define TM_BYTE_CNT1      0x3d04
  44 #define TM_AVST_RX_ERR    0x3d07
  45 #define   OVERFLOW_ERR    (1 << 9)
  46 #define   LENGTH_ERR      (1 << 8)
  47 #define   OVERSIZE_ERR    (1 << 7)
  48 #define   UNDERSIZE_ERR   (1 << 6)
  49 #define   MAC_CRC_ERR     (1 << 5)
  50 #define   PHY_ERR         (1 << 4)
  51 #define   ERR_VALID       (1 << 3)
  52
  53 #define LOOPBACK_EN          0x3e00
  54 #define LOOPBACK_FIFO_STATUS 0x3e01
  55 #define   ALMOST_EMPTY    (1 << 1)
  56 #define   ALMOST_FULL     (1 << 0)
  57
  58 #define MAILBOX_TIMEOUT_MS       100
  59 #define MAILBOX_POLL_INTERVAL_MS 10
  60
  61 struct traffic_ctrl_cmd {
  62         union {
  63                 uint64_t csr;
  64                 struct {
  65                         uint32_t read_cmd:1;
  66                         uint32_t write_cmd:1;
  67                         uint32_t ack_trans:1;
  68                         uint32_t rsvd1:29;
  69                         uint32_t afu_cmd_addr:16;
  70                         uint32_t rsvd2:16;
  71                 };
  72         };
  73 };
  74
  75 struct traffic_ctrl_data {
  76         union {
  77                 uint64_t csr;
  78                 struct {
  79                         uint32_t read_data;
  80                         uint32_t write_data;
  81                 };
  82         };
  83 };
  84
  85 struct traffic_ctrl_ch_sel {
  86         union {
  87                 uint64_t csr;
  88                 struct {
  89                         uint32_t channel_sel:3;
  90                         uint32_t rsvd1:29;
  91                         uint32_t rsvd2;
  92                 };
  93         };
  94 };
  95
  96 struct he_hssi_ctx {
  97         uint8_t *addr;
  98 };
  99
 100 struct he_hssi_priv {
 101         struct rte_pmd_afu_he_hssi_cfg he_hssi_cfg;
 102         struct he_hssi_ctx he_hssi_ctx;
 103 };
 104
 105 #ifdef __cplusplus
 106 }
 107 #endif
 108
 109 #endif /* AFU_PMD_HE_HSSI_H */