drivers/raw/ifpga/base/ifpga_hw.h

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2010-2018 Intel Corporation
   3  */
   4
   5 #ifndef _IFPGA_HW_H_
   6 #define _IFPGA_HW_H_
   7
   8 #include "ifpga_defines.h"
   9 #include "opae_ifpga_hw_api.h"
  10 #include "opae_eth_group.h"
  11
  12 /** List of private feateues */
  13 TAILQ_HEAD(ifpga_feature_list, ifpga_feature);
  14
  15 enum ifpga_feature_state {
  16         IFPGA_FEATURE_UNUSED = 0,
  17         IFPGA_FEATURE_ATTACHED,
  18 };
  19
  20 enum feature_type {
  21         FEATURE_FME_TYPE = 0,
  22         FEATURE_PORT_TYPE,
  23 };
  24
  25 struct feature_irq_ctx {
  26         int eventfd;
  27         int idx;
  28 };
  29
  30 struct ifpga_feature {
  31         TAILQ_ENTRY(ifpga_feature)next;
  32         enum ifpga_feature_state state;
  33         enum feature_type type;
  34         const char *name;
  35         u64 id;
  36         u8 *addr;
  37         uint64_t phys_addr;
  38         u32 size;
  39         int revision;
  40         u64 cap;
  41         int vfio_dev_fd;
  42         struct feature_irq_ctx *ctx;
  43         unsigned int ctx_num;
  44
  45         void *parent;           /* to parent hw data structure */
  46
  47         struct ifpga_feature_ops *ops;/* callback to this private feature */
  48         unsigned int vec_start;
  49         unsigned int vec_cnt;
  50 };
  51
  52 struct ifpga_feature_ops {
  53         int (*init)(struct ifpga_feature *feature);
  54         void (*uinit)(struct ifpga_feature *feature);
  55         int (*get_prop)(struct ifpga_feature *feature,
  56                         struct feature_prop *prop);
  57         int (*set_prop)(struct ifpga_feature *feature,
  58                         struct feature_prop *prop);
  59         int (*set_irq)(struct ifpga_feature *feature, void *irq_set);
  60 };
  61
  62 enum ifpga_fme_state {
  63         IFPGA_FME_UNUSED = 0,
  64         IFPGA_FME_IMPLEMENTED,
  65 };
  66
  67 struct ifpga_fme_hw {
  68         enum ifpga_fme_state state;
  69
  70         struct ifpga_feature_list feature_list;
  71         spinlock_t lock;        /* protect hardware access */
  72
  73         void *parent;           /* pointer to ifpga_hw */
  74
  75         /* provied by HEADER feature */
  76         u32 port_num;
  77         struct uuid bitstream_id;
  78         u64 bitstream_md;
  79         size_t pr_bandwidth;
  80         u32 socket_id;
  81         u32 fabric_version_id;
  82         u32 cache_size;
  83
  84         u32 capability;
  85
  86         void *max10_dev; /* MAX10 device */
  87         void *i2c_master; /* I2C Master device */
  88         void *eth_dev[MAX_ETH_GROUP_DEVICES];
  89         struct opae_reg_region
  90                 eth_group_region[MAX_ETH_GROUP_DEVICES];
  91         struct opae_board_info board_info;
  92         int nums_eth_dev;
  93         unsigned int nums_acc_region;
  94 };
  95
  96 enum ifpga_port_state {
  97         IFPGA_PORT_UNUSED = 0,
  98         IFPGA_PORT_ATTACHED,
  99         IFPGA_PORT_DETACHED,
 100 };
 101
 102 struct ifpga_port_hw {
 103         enum ifpga_port_state state;
 104
 105         struct ifpga_feature_list feature_list;
 106         spinlock_t lock;        /* protect access to hw */
 107
 108         void *parent;           /* pointer to ifpga_hw */
 109
 110         int port_id;            /* provied by HEADER feature */
 111         struct uuid afu_id;     /* provied by User AFU feature */
 112
 113         unsigned int disable_count;
 114
 115         u32 capability;
 116         u32 num_umsgs;  /* The number of allocated umsgs */
 117         u32 num_uafu_irqs;      /* The number of uafu interrupts */
 118         u8 *stp_addr;
 119         u32 stp_size;
 120 };
 121
 122 #define AFU_MAX_REGION 1
 123
 124 struct ifpga_afu_info {
 125         struct opae_reg_region region[AFU_MAX_REGION];
 126         unsigned int num_regions;
 127         unsigned int num_irqs;
 128 };
 129
 130 struct ifpga_hw {
 131         struct opae_adapter *adapter;
 132         struct opae_adapter_data_pci *pci_data;
 133
 134         struct ifpga_fme_hw fme;
 135         struct ifpga_port_hw port[MAX_FPGA_PORT_NUM];
 136 };
 137
 138 static inline bool is_ifpga_hw_pf(struct ifpga_hw *hw)
 139 {
 140         return hw->fme.state != IFPGA_FME_UNUSED;
 141 }
 142
 143 static inline bool is_valid_port_id(struct ifpga_hw *hw, u32 port_id)
 144 {
 145         if (port_id >= MAX_FPGA_PORT_NUM ||
 146             hw->port[port_id].state != IFPGA_PORT_ATTACHED)
 147                 return false;
 148
 149         return true;
 150 }
 151 #endif /* _IFPGA_HW_H_ */