1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2010-2018 Intel Corporation
5 #include "ifpga_feature_dev.h"
7 int port_get_prop(struct ifpga_port_hw *port, struct feature_prop *prop)
9 struct ifpga_feature *feature;
14 feature = get_port_feature_by_id(port, prop->feature_id);
16 if (feature && feature->ops && feature->ops->get_prop)
17 return feature->ops->get_prop(feature, prop);
22 int port_set_prop(struct ifpga_port_hw *port, struct feature_prop *prop)
24 struct ifpga_feature *feature;
29 feature = get_port_feature_by_id(port, prop->feature_id);
31 if (feature && feature->ops && feature->ops->set_prop)
32 return feature->ops->set_prop(feature, prop);
37 int port_set_irq(struct ifpga_port_hw *port, u32 feature_id, void *irq_set)
39 struct ifpga_feature *feature;
44 feature = get_port_feature_by_id(port, feature_id);
46 if (feature && feature->ops && feature->ops->set_irq)
47 return feature->ops->set_irq(feature, irq_set);
52 static int port_get_revision(struct ifpga_port_hw *port, u64 *revision)
54 struct feature_port_header *port_hdr
55 = get_port_feature_ioaddr_by_index(port,
56 PORT_FEATURE_ID_HEADER);
57 struct feature_header header;
59 header.csr = readq(&port_hdr->header);
61 *revision = header.revision;
66 static int port_get_portidx(struct ifpga_port_hw *port, u64 *idx)
68 struct feature_port_header *port_hdr;
69 struct feature_port_capability capability;
71 port_hdr = get_port_feature_ioaddr_by_index(port,
72 PORT_FEATURE_ID_HEADER);
74 capability.csr = readq(&port_hdr->capability);
75 *idx = capability.port_number;
80 static int port_get_latency_tolerance(struct ifpga_port_hw *port, u64 *val)
82 struct feature_port_header *port_hdr;
83 struct feature_port_control control;
85 port_hdr = get_port_feature_ioaddr_by_index(port,
86 PORT_FEATURE_ID_HEADER);
88 control.csr = readq(&port_hdr->control);
89 *val = control.latency_tolerance;
94 static int port_get_ap1_event(struct ifpga_port_hw *port, u64 *val)
96 struct feature_port_header *port_hdr;
97 struct feature_port_status status;
99 port_hdr = get_port_feature_ioaddr_by_index(port,
100 PORT_FEATURE_ID_HEADER);
102 spinlock_lock(&port->lock);
103 status.csr = readq(&port_hdr->status);
104 spinlock_unlock(&port->lock);
106 *val = status.ap1_event;
111 static int port_set_ap1_event(struct ifpga_port_hw *port, u64 val)
113 struct feature_port_header *port_hdr;
114 struct feature_port_status status;
116 port_hdr = get_port_feature_ioaddr_by_index(port,
117 PORT_FEATURE_ID_HEADER);
119 spinlock_lock(&port->lock);
120 status.csr = readq(&port_hdr->status);
121 status.ap1_event = val;
122 writeq(status.csr, &port_hdr->status);
123 spinlock_unlock(&port->lock);
128 static int port_get_ap2_event(struct ifpga_port_hw *port, u64 *val)
130 struct feature_port_header *port_hdr;
131 struct feature_port_status status;
133 port_hdr = get_port_feature_ioaddr_by_index(port,
134 PORT_FEATURE_ID_HEADER);
136 spinlock_lock(&port->lock);
137 status.csr = readq(&port_hdr->status);
138 spinlock_unlock(&port->lock);
140 *val = status.ap2_event;
145 static int port_set_ap2_event(struct ifpga_port_hw *port, u64 val)
147 struct feature_port_header *port_hdr;
148 struct feature_port_status status;
150 port_hdr = get_port_feature_ioaddr_by_index(port,
151 PORT_FEATURE_ID_HEADER);
153 spinlock_lock(&port->lock);
154 status.csr = readq(&port_hdr->status);
155 status.ap2_event = val;
156 writeq(status.csr, &port_hdr->status);
157 spinlock_unlock(&port->lock);
162 static int port_get_power_state(struct ifpga_port_hw *port, u64 *val)
164 struct feature_port_header *port_hdr;
165 struct feature_port_status status;
167 port_hdr = get_port_feature_ioaddr_by_index(port,
168 PORT_FEATURE_ID_HEADER);
170 spinlock_lock(&port->lock);
171 status.csr = readq(&port_hdr->status);
172 spinlock_unlock(&port->lock);
174 *val = status.power_state;
179 static int port_get_userclk_freqcmd(struct ifpga_port_hw *port, u64 *val)
181 struct feature_port_header *port_hdr;
183 port_hdr = get_port_feature_ioaddr_by_index(port,
184 PORT_FEATURE_ID_HEADER);
186 spinlock_lock(&port->lock);
187 *val = readq(&port_hdr->user_clk_freq_cmd0);
188 spinlock_unlock(&port->lock);
193 static int port_set_userclk_freqcmd(struct ifpga_port_hw *port, u64 val)
195 struct feature_port_header *port_hdr;
197 port_hdr = get_port_feature_ioaddr_by_index(port,
198 PORT_FEATURE_ID_HEADER);
200 spinlock_lock(&port->lock);
201 writeq(val, &port_hdr->user_clk_freq_cmd0);
202 spinlock_unlock(&port->lock);
207 static int port_get_userclk_freqcntrcmd(struct ifpga_port_hw *port, u64 *val)
209 struct feature_port_header *port_hdr;
211 port_hdr = get_port_feature_ioaddr_by_index(port,
212 PORT_FEATURE_ID_HEADER);
214 spinlock_lock(&port->lock);
215 *val = readq(&port_hdr->user_clk_freq_cmd1);
216 spinlock_unlock(&port->lock);
221 static int port_set_userclk_freqcntrcmd(struct ifpga_port_hw *port, u64 val)
223 struct feature_port_header *port_hdr;
225 port_hdr = get_port_feature_ioaddr_by_index(port,
226 PORT_FEATURE_ID_HEADER);
228 spinlock_lock(&port->lock);
229 writeq(val, &port_hdr->user_clk_freq_cmd1);
230 spinlock_unlock(&port->lock);
235 static int port_get_userclk_freqsts(struct ifpga_port_hw *port, u64 *val)
237 struct feature_port_header *port_hdr;
239 port_hdr = get_port_feature_ioaddr_by_index(port,
240 PORT_FEATURE_ID_HEADER);
242 spinlock_lock(&port->lock);
243 *val = readq(&port_hdr->user_clk_freq_sts0);
244 spinlock_unlock(&port->lock);
249 static int port_get_userclk_freqcntrsts(struct ifpga_port_hw *port, u64 *val)
251 struct feature_port_header *port_hdr;
253 port_hdr = get_port_feature_ioaddr_by_index(port,
254 PORT_FEATURE_ID_HEADER);
256 spinlock_lock(&port->lock);
257 *val = readq(&port_hdr->user_clk_freq_sts1);
258 spinlock_unlock(&port->lock);
263 static int port_hdr_init(struct ifpga_feature *feature)
265 struct ifpga_port_hw *port = feature->parent;
267 dev_info(NULL, "port hdr Init.\n");
269 fpga_port_reset(port);
274 static void port_hdr_uinit(struct ifpga_feature *feature)
278 dev_info(NULL, "port hdr uinit.\n");
281 static int port_hdr_get_prop(struct ifpga_feature *feature,
282 struct feature_prop *prop)
284 struct ifpga_port_hw *port = feature->parent;
286 switch (prop->prop_id) {
287 case PORT_HDR_PROP_REVISION:
288 return port_get_revision(port, &prop->data);
289 case PORT_HDR_PROP_PORTIDX:
290 return port_get_portidx(port, &prop->data);
291 case PORT_HDR_PROP_LATENCY_TOLERANCE:
292 return port_get_latency_tolerance(port, &prop->data);
293 case PORT_HDR_PROP_AP1_EVENT:
294 return port_get_ap1_event(port, &prop->data);
295 case PORT_HDR_PROP_AP2_EVENT:
296 return port_get_ap2_event(port, &prop->data);
297 case PORT_HDR_PROP_POWER_STATE:
298 return port_get_power_state(port, &prop->data);
299 case PORT_HDR_PROP_USERCLK_FREQCMD:
300 return port_get_userclk_freqcmd(port, &prop->data);
301 case PORT_HDR_PROP_USERCLK_FREQCNTRCMD:
302 return port_get_userclk_freqcntrcmd(port, &prop->data);
303 case PORT_HDR_PROP_USERCLK_FREQSTS:
304 return port_get_userclk_freqsts(port, &prop->data);
305 case PORT_HDR_PROP_USERCLK_CNTRSTS:
306 return port_get_userclk_freqcntrsts(port, &prop->data);
312 static int port_hdr_set_prop(struct ifpga_feature *feature,
313 struct feature_prop *prop)
315 struct ifpga_port_hw *port = feature->parent;
317 switch (prop->prop_id) {
318 case PORT_HDR_PROP_AP1_EVENT:
319 return port_set_ap1_event(port, prop->data);
320 case PORT_HDR_PROP_AP2_EVENT:
321 return port_set_ap2_event(port, prop->data);
322 case PORT_HDR_PROP_USERCLK_FREQCMD:
323 return port_set_userclk_freqcmd(port, prop->data);
324 case PORT_HDR_PROP_USERCLK_FREQCNTRCMD:
325 return port_set_userclk_freqcntrcmd(port, prop->data);
331 struct ifpga_feature_ops ifpga_rawdev_port_hdr_ops = {
332 .init = port_hdr_init,
333 .uinit = port_hdr_uinit,
334 .get_prop = port_hdr_get_prop,
335 .set_prop = port_hdr_set_prop,
338 static int port_stp_init(struct ifpga_feature *feature)
340 struct ifpga_port_hw *port = feature->parent;
342 dev_info(NULL, "port stp Init.\n");
344 spinlock_lock(&port->lock);
345 port->stp_addr = feature->addr;
346 port->stp_size = feature->size;
347 spinlock_unlock(&port->lock);
352 static void port_stp_uinit(struct ifpga_feature *feature)
356 dev_info(NULL, "port stp uinit.\n");
359 struct ifpga_feature_ops ifpga_rawdev_port_stp_ops = {
360 .init = port_stp_init,
361 .uinit = port_stp_uinit,
364 static int port_uint_init(struct ifpga_feature *feature)
366 struct ifpga_port_hw *port = feature->parent;
368 dev_info(NULL, "PORT UINT Init.\n");
370 spinlock_lock(&port->lock);
371 if (feature->ctx_num) {
372 port->capability |= FPGA_PORT_CAP_UAFU_IRQ;
373 port->num_uafu_irqs = feature->ctx_num;
375 spinlock_unlock(&port->lock);
380 static void port_uint_uinit(struct ifpga_feature *feature)
384 dev_info(NULL, "PORT UINT UInit.\n");
387 static int port_uint_set_irq(struct ifpga_feature *feature, void *irq_set)
389 struct fpga_uafu_irq_set *uafu_irq_set = irq_set;
390 struct ifpga_port_hw *port = feature->parent;
393 if (!(port->capability & FPGA_PORT_CAP_UAFU_IRQ))
396 spinlock_lock(&port->lock);
397 ret = fpga_msix_set_block(feature, uafu_irq_set->start,
398 uafu_irq_set->count, uafu_irq_set->evtfds);
399 spinlock_unlock(&port->lock);
404 struct ifpga_feature_ops ifpga_rawdev_port_uint_ops = {
405 .init = port_uint_init,
406 .uinit = port_uint_uinit,
407 .set_irq = port_uint_set_irq,
410 static int port_afu_init(struct ifpga_feature *feature)
414 dev_info(NULL, "PORT AFU Init.\n");
419 static void port_afu_uinit(struct ifpga_feature *feature)
423 dev_info(NULL, "PORT AFU UInit.\n");
426 struct ifpga_feature_ops ifpga_rawdev_port_afu_ops = {
427 .init = port_afu_init,
428 .uinit = port_afu_uinit,