1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2010-2019 Intel Corporation
5 #include "opae_osdep.h"
6 #include "opae_eth_group.h"
8 #define DATA_VAL_INVL 1 /* us */
9 #define DATA_VAL_POLL_TIMEOUT 10 /* us */
11 static const char *eth_type_to_string(u8 type)
19 return "ethernet wrapper";
25 static int eth_group_get_select(struct eth_group_device *dev,
26 u8 type, u8 index, u8 *select)
29 * in different speed configuration, the index of
30 * PHY and MAC are different.
32 * 1 ethernet wrapper -> Device Select 0x0 - fixed value
33 * n PHYs -> Device Select 0x2,4,6,8,A,C,E,10,...
34 * n MACs -> Device Select 0x3,5,7,9,B,D,F,11,...
37 if (type == ETH_GROUP_PHY && index < dev->phy_num)
38 *select = index * 2 + 2;
39 else if (type == ETH_GROUP_MAC && index < dev->mac_num)
40 *select = index * 2 + 3;
41 else if (type == ETH_GROUP_ETHER && index == 0)
49 int eth_group_write_reg(struct eth_group_device *dev,
50 u8 type, u8 index, u16 addr, u32 data)
56 dev_debug(dev, "%s type %s index %u addr 0x%x\n",
57 __func__, eth_type_to_string(type), index, addr);
59 /* find device select */
60 ret = eth_group_get_select(dev, type, index, &dev_select);
64 v = CMD_WR << CTRL_CMD_SHIT |
65 (u64)dev_select << CTRL_DS_SHIFT |
66 (u64)addr << CTRL_ADDR_SHIFT |
67 (data & CTRL_WR_DATA);
69 /* only PHY has additional feature bit */
70 if (type == ETH_GROUP_PHY)
71 v |= CTRL_FEAT_SELECT;
73 opae_writeq(v, dev->base + ETH_GROUP_CTRL);
78 int eth_group_read_reg(struct eth_group_device *dev,
79 u8 type, u8 index, u16 addr, u32 *data)
85 dev_debug(dev, "%s type %s index %u addr 0x%x\n",
86 __func__, eth_type_to_string(type), index,
89 /* find device select */
90 ret = eth_group_get_select(dev, type, index, &dev_select);
94 v = CMD_RD << CTRL_CMD_SHIT |
95 (u64)dev_select << CTRL_DS_SHIFT |
96 (u64)addr << CTRL_ADDR_SHIFT;
98 /* only PHY has additional feature bit */
99 if (type == ETH_GROUP_PHY)
100 v |= CTRL_FEAT_SELECT;
102 opae_writeq(v, dev->base + ETH_GROUP_CTRL);
104 if (opae_readq_poll_timeout(dev->base + ETH_GROUP_STAT,
105 v, v & STAT_DATA_VAL, DATA_VAL_INVL,
106 DATA_VAL_POLL_TIMEOUT))
109 *data = (v & STAT_RD_DATA);
111 dev_debug(dev, "%s data 0x%x\n", __func__, *data);
116 static int eth_group_reset_mac(struct eth_group_device *dev, u8 index,
123 * only support 25G & 40G mac reset for now. It uses internal reset.
124 * as PHY and MAC are integrated together, below action will trigger
127 if (dev->speed != 25 && dev->speed != 40)
130 ret = eth_group_read_reg(dev, ETH_GROUP_MAC, index, MAC_CONFIG,
133 dev_err(dev, "fail to read PHY_CONFIG: %d\n", ret);
137 /* skip if mac is in expected state already */
138 if ((((val & MAC_RESET_MASK) == MAC_RESET_MASK) && enable) ||
139 (((val & MAC_RESET_MASK) == 0) && !enable))
143 val |= MAC_RESET_MASK;
145 val &= ~MAC_RESET_MASK;
147 ret = eth_group_write_reg(dev, ETH_GROUP_MAC, index, MAC_CONFIG,
150 dev_err(dev, "fail to write PHY_CONFIG: %d\n", ret);
155 static void eth_group_mac_uinit(struct eth_group_device *dev)
159 for (i = 0; i < dev->mac_num; i++) {
160 if (eth_group_reset_mac(dev, i, true))
161 dev_err(dev, "fail to disable mac %d\n", i);
165 static int eth_group_mac_init(struct eth_group_device *dev)
170 for (i = 0; i < dev->mac_num; i++) {
171 ret = eth_group_reset_mac(dev, i, false);
173 dev_err(dev, "fail to enable mac %d\n", i);
182 eth_group_reset_mac(dev, i, true);
187 static int eth_group_reset_phy(struct eth_group_device *dev, u8 index,
193 /* only support 10G PHY reset for now. It uses external reset. */
194 if (dev->speed != 10)
197 ret = eth_group_read_reg(dev, ETH_GROUP_PHY, index,
200 dev_err(dev, "fail to read ADD_PHY_CTRL reg: %d\n", ret);
204 /* return if PHY is already in expected state */
205 if ((val & PHY_RESET && enable) || (!(val & PHY_RESET) && !enable))
213 ret = eth_group_write_reg(dev, ETH_GROUP_PHY, index,
216 dev_err(dev, "fail to write ADD_PHY_CTRL reg: %d\n", ret);
221 static int eth_group_phy_init(struct eth_group_device *dev)
226 for (i = 0; i < dev->phy_num; i++) {
227 ret = eth_group_reset_phy(dev, i, false);
229 dev_err(dev, "fail to enable phy %d\n", i);
237 eth_group_reset_phy(dev, i, true);
242 static void eth_group_phy_uinit(struct eth_group_device *dev)
246 for (i = 0; i < dev->phy_num; i++) {
247 if (eth_group_reset_phy(dev, i, true))
248 dev_err(dev, "fail to disable phy %d\n", i);
252 static int eth_group_hw_init(struct eth_group_device *dev)
256 ret = eth_group_phy_init(dev);
258 dev_err(dev, "fail to init eth group phys\n");
262 ret = eth_group_mac_init(dev);
264 dev_err(priv->dev, "fail to init eth group macs\n");
271 eth_group_phy_uinit(dev);
275 static void eth_group_hw_uinit(struct eth_group_device *dev)
277 eth_group_mac_uinit(dev);
278 eth_group_phy_uinit(dev);
281 struct eth_group_device *eth_group_probe(void *base)
283 struct eth_group_device *dev;
285 dev = opae_malloc(sizeof(*dev));
289 dev->base = (u8 *)base;
291 dev->info.info = opae_readq(dev->base + ETH_GROUP_INFO);
292 dev->group_id = dev->info.group_id;
293 dev->phy_num = dev->mac_num = dev->info.num_phys;
294 dev->speed = dev->info.speed;
296 dev->status = ETH_GROUP_DEV_ATTACHED;
298 if (eth_group_hw_init(dev)) {
299 dev_err(dev, "eth group hw init fail\n");
303 dev_info(dev, "eth group device %d probe done: phy_num=mac_num:%d, speed=%d\n",
304 dev->group_id, dev->phy_num, dev->speed);
309 void eth_group_release(struct eth_group_device *dev)
312 eth_group_hw_uinit(dev);
313 dev->status = ETH_GROUP_DEV_NOUSED;