drivers/raw/ifpga/base/opae_eth_group.h

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2010-2019 Intel Corporation
   3  */
   4
   5 #ifndef _OPAE_PHY_MAC_H
   6 #define _OPAE_PHY_MAC_H
   7
   8 #include "opae_osdep.h"
   9
  10 #define MAX_ETH_GROUP_DEVICES 2
  11
  12 #define LINE_SIDE_GROUP_ID 0
  13 #define HOST_SIDE_GROUP_ID 1
  14
  15 #define ETH_GROUP_SELECT_FEAT 1
  16
  17 #define ETH_GROUP_PHY 1
  18 #define ETH_GROUP_MAC 2
  19 #define ETH_GROUP_ETHER 3
  20
  21 #define ETH_GROUP_INFO          0x8
  22 #define INFO_SPEED              GENMASK_ULL(23, 16)
  23 #define ETH_SPEED_10G           10
  24 #define ETH_SPEED_25G           25
  25 #define INFO_PHY_NUM            GENMASK_ULL(15, 8)
  26 #define INFO_GROUP_NUM          GENMASK_ULL(7, 0)
  27
  28 #define ETH_GROUP_CTRL          0x10
  29 #define CTRL_CMD                GENMASK_ULL(63, 62)
  30 #define CTRL_CMD_SHIT           62
  31 #define CMD_NOP                 0ULL
  32 #define CMD_RD                  1ULL
  33 #define CMD_WR                  2ULL
  34 #define CTRL_DEV_SELECT         GENMASK_ULL(53, 49)
  35 #define CTRL_DS_SHIFT   49
  36 #define CTRL_FEAT_SELECT        BIT_ULL(48)
  37 #define SELECT_IP               0
  38 #define SELECT_FEAT             1
  39 #define CTRL_ADDR               GENMASK_ULL(47, 32)
  40 #define CTRL_ADDR_SHIFT         32
  41 #define CTRL_WR_DATA            GENMASK_ULL(31, 0)
  42
  43 #define ETH_GROUP_STAT          0x18
  44 #define STAT_DATA_VAL           BIT_ULL(32)
  45 #define STAT_RD_DATA            GENMASK_ULL(31, 0)
  46
  47 /* Additional Feature Register */
  48 #define ADD_PHY_CTRL            0x0
  49 #define PHY_RESET               BIT(0)
  50 #define MAC_CONFIG      0x310
  51 #define MAC_RESET_MASK  GENMASK(2, 0)
  52
  53 struct opae_eth_group_info {
  54         u8 group_id;
  55         u8 speed;
  56         u8 nums_of_phy;
  57         u8 nums_of_mac;
  58 };
  59
  60 struct opae_eth_group_region_info {
  61         u8 group_id;
  62         u64 phys_addr;
  63         u64 len;
  64         u8 *addr;
  65         u8 mem_idx;
  66 };
  67
  68 struct eth_group_info_reg {
  69         union {
  70                 u64 info;
  71                 struct {
  72                         u8 group_id:8;
  73                         u8 num_phys:8;
  74                         u8 speed:8;
  75                         u8 direction:1;
  76                         u64 resvd:39;
  77                 };
  78         };
  79 };
  80
  81 enum eth_group_status {
  82         ETH_GROUP_DEV_NOUSED = 0,
  83         ETH_GROUP_DEV_ATTACHED,
  84 };
  85
  86 struct eth_group_device {
  87         u8 *base;
  88         struct eth_group_info_reg info;
  89         enum eth_group_status status;
  90         u8 speed;
  91         u8 group_id;
  92         u8 phy_num;
  93         u8 mac_num;
  94 };
  95
  96 struct eth_group_device *eth_group_probe(void *base);
  97 void eth_group_release(struct eth_group_device *dev);
  98 int eth_group_read_reg(struct eth_group_device *dev,
  99                 u8 type, u8 index, u16 addr, u32 *data);
 100 int eth_group_write_reg(struct eth_group_device *dev,
 101                 u8 type, u8 index, u16 addr, u32 data);
 102 #endif