1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2010-2019 Intel Corporation
5 #ifndef _OPAE_PHY_MAC_H
6 #define _OPAE_PHY_MAC_H
8 #include "opae_osdep.h"
10 #define MAX_ETH_GROUP_DEVICES 2
12 #define LINE_SIDE_GROUP_ID 0
13 #define HOST_SIDE_GROUP_ID 1
15 #define ETH_GROUP_SELECT_FEAT 1
17 #define ETH_GROUP_PHY 1
18 #define ETH_GROUP_MAC 2
19 #define ETH_GROUP_ETHER 3
21 #define ETH_GROUP_INFO 0x8
22 #define INFO_SPEED GENMASK_ULL(23, 16)
23 #define ETH_SPEED_10G 10
24 #define ETH_SPEED_25G 25
25 #define INFO_PHY_NUM GENMASK_ULL(15, 8)
26 #define INFO_GROUP_NUM GENMASK_ULL(7, 0)
28 #define ETH_GROUP_CTRL 0x10
29 #define CTRL_CMD GENMASK_ULL(63, 62)
30 #define CTRL_CMD_SHIT 62
34 #define CTRL_DEV_SELECT GENMASK_ULL(53, 49)
35 #define CTRL_DS_SHIFT 49
36 #define CTRL_FEAT_SELECT BIT_ULL(48)
39 #define CTRL_ADDR GENMASK_ULL(47, 32)
40 #define CTRL_ADDR_SHIFT 32
41 #define CTRL_WR_DATA GENMASK_ULL(31, 0)
43 #define ETH_GROUP_STAT 0x18
44 #define STAT_DATA_VAL BIT_ULL(32)
45 #define STAT_RD_DATA GENMASK_ULL(31, 0)
47 /* Additional Feature Register */
48 #define ADD_PHY_CTRL 0x0
49 #define PHY_RESET BIT(0)
50 #define MAC_CONFIG 0x310
51 #define MAC_RESET_MASK GENMASK(2, 0)
53 struct opae_eth_group_info {
60 struct opae_eth_group_region_info {
68 struct eth_group_info_reg {
81 enum eth_group_status {
82 ETH_GROUP_DEV_NOUSED = 0,
83 ETH_GROUP_DEV_ATTACHED,
86 struct eth_group_device {
88 struct eth_group_info_reg info;
89 enum eth_group_status status;
96 struct eth_group_device *eth_group_probe(void *base);
97 void eth_group_release(struct eth_group_device *dev);
98 int eth_group_read_reg(struct eth_group_device *dev,
99 u8 type, u8 index, u16 addr, u32 *data);
100 int eth_group_write_reg(struct eth_group_device *dev,
101 u8 type, u8 index, u16 addr, u32 data);