2 /* SPDX-License-Identifier: BSD-3-Clause
3 * Copyright(c) 2010-2019 Intel Corporation
6 #include "opae_osdep.h"
9 static int i2c_transfer(struct altera_i2c_dev *dev,
10 struct i2c_msg *msg, int num)
14 for (ret = 0, try = 0; try < I2C_XFER_RETRY; try++) {
15 ret = dev->xfer(dev, msg, num);
26 int i2c_read(struct altera_i2c_dev *dev, int flags, unsigned int slave_addr,
27 u32 offset, u8 *buf, u32 count)
33 pthread_mutex_lock(dev->mutex);
35 if (flags & I2C_FLAG_ADDR16)
36 msgbuf[i++] = offset >> 8;
40 struct i2c_msg msg[2] = {
60 ret = i2c_transfer(dev, msg, 2);
63 pthread_mutex_unlock(dev->mutex);
67 int i2c_write(struct altera_i2c_dev *dev, int flags, unsigned int slave_addr,
68 u32 offset, u8 *buffer, int len)
75 pthread_mutex_lock(dev->mutex);
82 buf = opae_malloc(I2C_MAX_OFFSET_LEN + len);
88 msg.addr = slave_addr;
92 if (flags & I2C_FLAG_ADDR16)
93 msg.buf[i++] = offset >> 8;
95 msg.buf[i++] = offset;
96 opae_memcpy(&msg.buf[i], buffer, len);
99 ret = i2c_transfer(dev, &msg, 1);
103 pthread_mutex_unlock(dev->mutex);
107 int i2c_read8(struct altera_i2c_dev *dev, unsigned int slave_addr, u32 offset,
110 return i2c_read(dev, 0, slave_addr, offset, buf, count);
113 int i2c_read16(struct altera_i2c_dev *dev, unsigned int slave_addr, u32 offset,
116 return i2c_read(dev, I2C_FLAG_ADDR16, slave_addr, offset,
120 int i2c_write8(struct altera_i2c_dev *dev, unsigned int slave_addr, u32 offset,
123 return i2c_write(dev, 0, slave_addr, offset, buf, count);
126 int i2c_write16(struct altera_i2c_dev *dev, unsigned int slave_addr, u32 offset,
129 return i2c_write(dev, I2C_FLAG_ADDR16, slave_addr, offset,
133 static void i2c_indirect_write(struct altera_i2c_dev *dev, u32 reg,
138 ctrl = I2C_CTRL_W | (reg >> 2);
140 opae_writeq(value & I2C_WRITE_DATA_MASK, dev->base + I2C_WRITE);
141 opae_writeq(ctrl, dev->base + I2C_CTRL);
144 static u32 i2c_indirect_read(struct altera_i2c_dev *dev, u32 reg)
150 ctrl = I2C_CTRL_R | (reg >> 2);
151 opae_writeq(ctrl, dev->base + I2C_CTRL);
153 /* FIXME: Read one more time to avoid HW timing issue. */
154 tmp = opae_readq(dev->base + I2C_READ);
155 tmp = opae_readq(dev->base + I2C_READ);
157 value = tmp & I2C_READ_DATA_MASK;
162 static void altera_i2c_transfer(struct altera_i2c_dev *dev, u32 data)
164 /*send STOP on last byte*/
165 if (dev->msg_len == 1)
166 data |= ALTERA_I2C_TFR_CMD_STO;
167 if (dev->msg_len > 0)
168 i2c_indirect_write(dev, ALTERA_I2C_TFR_CMD, data);
171 static void altera_i2c_disable(struct altera_i2c_dev *dev)
173 u32 val = i2c_indirect_read(dev, ALTERA_I2C_CTRL);
175 i2c_indirect_write(dev, ALTERA_I2C_CTRL, val&~ALTERA_I2C_CTRL_EN);
178 static void altera_i2c_enable(struct altera_i2c_dev *dev)
180 u32 val = i2c_indirect_read(dev, ALTERA_I2C_CTRL);
182 i2c_indirect_write(dev, ALTERA_I2C_CTRL, val | ALTERA_I2C_CTRL_EN);
185 static void altera_i2c_reset(struct altera_i2c_dev *dev)
187 altera_i2c_disable(dev);
188 altera_i2c_enable(dev);
191 static int altera_i2c_wait_core_idle(struct altera_i2c_dev *dev)
195 while (i2c_indirect_read(dev, ALTERA_I2C_STATUS)
196 & ALTERA_I2C_STAT_CORE) {
197 if (retry++ > ALTERA_I2C_TIMEOUT_US) {
198 dev_err(dev, "timeout: Core Status not IDLE...\n");
207 static void altera_i2c_enable_interrupt(struct altera_i2c_dev *dev,
208 u32 mask, bool enable)
212 status = i2c_indirect_read(dev, ALTERA_I2C_ISER);
214 dev->isr_mask = status | mask;
216 dev->isr_mask = status&~mask;
218 i2c_indirect_write(dev, ALTERA_I2C_ISER, dev->isr_mask);
221 static void altera_i2c_interrupt_clear(struct altera_i2c_dev *dev, u32 mask)
225 int_en = i2c_indirect_read(dev, ALTERA_I2C_ISR);
227 i2c_indirect_write(dev, ALTERA_I2C_ISR, int_en | mask);
230 static void altera_i2c_read_rx_fifo(struct altera_i2c_dev *dev)
235 rx_avail = i2c_indirect_read(dev, ALTERA_I2C_RX_FIFO_LVL);
236 bytes = min(rx_avail, dev->msg_len);
238 while (bytes-- > 0) {
239 *dev->buf++ = i2c_indirect_read(dev, ALTERA_I2C_RX_DATA);
241 altera_i2c_transfer(dev, 0);
245 static void altera_i2c_stop(struct altera_i2c_dev *dev)
247 i2c_indirect_write(dev, ALTERA_I2C_TFR_CMD, ALTERA_I2C_TFR_CMD_STO);
250 static int altera_i2c_fill_tx_fifo(struct altera_i2c_dev *dev)
256 tx_avail = dev->fifo_size -
257 i2c_indirect_read(dev, ALTERA_I2C_TC_FIFO_LVL);
258 bytes = min(tx_avail, dev->msg_len);
259 ret = dev->msg_len - bytes;
261 while (bytes-- > 0) {
262 altera_i2c_transfer(dev, *dev->buf++);
269 static u8 i2c_8bit_addr_from_msg(const struct i2c_msg *msg)
271 return (msg->addr << 1) | (msg->flags & I2C_M_RD ? 1 : 0);
274 static int altera_i2c_wait_complete(struct altera_i2c_dev *dev,
279 while (!((*status = i2c_indirect_read(dev, ALTERA_I2C_ISR))
281 if (retry++ > ALTERA_I2C_TIMEOUT_US)
290 static bool altera_handle_i2c_status(struct altera_i2c_dev *dev, u32 status)
292 bool read, finish = false;
295 read = (dev->msg->flags & I2C_M_RD) != 0;
297 if (status & ALTERA_I2C_ISR_ARB) {
298 altera_i2c_interrupt_clear(dev, ALTERA_I2C_ISR_ARB);
299 dev->msg_err = -EAGAIN;
301 } else if (status & ALTERA_I2C_ISR_NACK) {
302 dev_debug(dev, "could not get ACK\n");
303 dev->msg_err = -ENXIO;
304 altera_i2c_interrupt_clear(dev, ALTERA_I2C_ISR_NACK);
305 altera_i2c_stop(dev);
307 } else if (read && (status & ALTERA_I2C_ISR_RXOF)) {
308 /* RX FIFO Overflow */
309 altera_i2c_read_rx_fifo(dev);
310 altera_i2c_interrupt_clear(dev, ALTERA_I2C_ISER_RXOF_EN);
311 altera_i2c_stop(dev);
312 dev_err(dev, "error: RX FIFO overflow\n");
314 } else if (read && (status & ALTERA_I2C_ISR_RXRDY)) {
315 altera_i2c_read_rx_fifo(dev);
316 altera_i2c_interrupt_clear(dev, ALTERA_I2C_ISR_RXRDY);
319 } else if (!read && (status & ALTERA_I2C_ISR_TXRDY)) {
320 altera_i2c_interrupt_clear(dev, ALTERA_I2C_ISR_TXRDY);
321 if (dev->msg_len > 0)
322 altera_i2c_fill_tx_fifo(dev);
326 dev_err(dev, "unexpected status:0x%x\n", status);
327 altera_i2c_interrupt_clear(dev, ALTERA_I2C_ALL_IRQ);
331 ret = altera_i2c_wait_core_idle(dev);
333 dev_err(dev, "message timeout\n");
335 altera_i2c_enable_interrupt(dev, ALTERA_I2C_ALL_IRQ, false);
336 altera_i2c_interrupt_clear(dev, ALTERA_I2C_ALL_IRQ);
337 dev_debug(dev, "message done\n");
343 static bool altera_i2c_poll_status(struct altera_i2c_dev *dev)
350 if (altera_i2c_wait_complete(dev, &status)) {
351 dev_err(dev, "altera i2c wait complete timeout, status=0x%x\n",
356 finish = altera_handle_i2c_status(dev, status);
358 if (i++ > I2C_XFER_RETRY)
366 static int altera_i2c_xfer_msg(struct altera_i2c_dev *dev,
369 u32 int_mask = ALTERA_I2C_ISR_RXOF |
370 ALTERA_I2C_ISR_ARB | ALTERA_I2C_ISR_NACK;
371 u8 addr = i2c_8bit_addr_from_msg(msg);
375 dev->msg_len = msg->len;
378 altera_i2c_enable(dev);
380 /*make sure RX FIFO is emtry*/
382 i2c_indirect_read(dev, ALTERA_I2C_RX_DATA);
383 } while (i2c_indirect_read(dev, ALTERA_I2C_RX_FIFO_LVL));
385 i2c_indirect_write(dev, ALTERA_I2C_TFR_CMD_RW_D,
386 ALTERA_I2C_TFR_CMD_STA | addr);
389 if (msg->flags & I2C_M_RD) {
390 int_mask |= ALTERA_I2C_ISR_RXOF | ALTERA_I2C_ISR_RXRDY;
391 /* in polling mode, we should set this ISR register? */
392 altera_i2c_enable_interrupt(dev, int_mask, true);
393 altera_i2c_transfer(dev, 0);
395 int_mask |= ALTERA_I2C_ISR_TXRDY;
396 altera_i2c_enable_interrupt(dev, int_mask, true);
397 altera_i2c_fill_tx_fifo(dev);
400 finish = altera_i2c_poll_status(dev);
402 dev->msg_err = -ETIMEDOUT;
403 dev_err(dev, "%s: i2c transfer error\n", __func__);
406 altera_i2c_enable_interrupt(dev, int_mask, false);
408 if (i2c_indirect_read(dev, ALTERA_I2C_STATUS) & ALTERA_I2C_STAT_CORE)
409 dev_info(dev, "core not idle...\n");
411 altera_i2c_disable(dev);
416 static int altera_i2c_xfer(struct altera_i2c_dev *dev,
417 struct i2c_msg *msg, int num)
422 for (i = 0; i < num; i++, msg++) {
423 ret = altera_i2c_xfer_msg(dev, msg);
431 static void altera_i2c_hardware_init(struct altera_i2c_dev *dev)
433 u32 divisor = dev->i2c_clk / dev->bus_clk_rate;
434 u32 clk_mhz = dev->i2c_clk / 1000000;
435 u32 tmp = (ALTERA_I2C_THRESHOLD << ALTERA_I2C_CTRL_RXT_SHFT) |
436 (ALTERA_I2C_THRESHOLD << ALTERA_I2C_CTRL_TCT_SHFT);
439 if (dev->bus_clk_rate <= 100000) {
440 tmp &= ~ALTERA_I2C_CTRL_BSPEED;
441 /*standard mode SCL 50/50*/
442 t_high = divisor*1/2;
445 tmp |= ALTERA_I2C_CTRL_BSPEED;
446 /*Fast mode SCL 33/66*/
447 t_high = divisor*1/3;
451 i2c_indirect_write(dev, ALTERA_I2C_CTRL, tmp);
453 dev_info(dev, "%s: rate=%uHz per_clk=%uMHz -> ratio=1:%u\n",
454 __func__, dev->bus_clk_rate, clk_mhz, divisor);
457 altera_i2c_reset(dev);
459 /*Set SCL high Time*/
460 i2c_indirect_write(dev, ALTERA_I2C_SCL_HIGH, t_high);
462 i2c_indirect_write(dev, ALTERA_I2C_SCL_LOW, t_low);
463 /*Set SDA Hold time, 300ms*/
464 i2c_indirect_write(dev, ALTERA_I2C_SDA_HOLD, (300*clk_mhz)/1000);
466 altera_i2c_enable_interrupt(dev, ALTERA_I2C_ALL_IRQ, false);
469 struct altera_i2c_dev *altera_i2c_probe(void *base)
471 struct altera_i2c_dev *dev;
473 dev = opae_malloc(sizeof(*dev));
477 dev->base = (u8 *)base;
478 dev->i2c_param.info = opae_readq(dev->base + I2C_PARAM);
480 if (dev->i2c_param.devid != 0xEE011) {
481 dev_err(dev, "find a invalid i2c master\n");
485 dev->fifo_size = dev->i2c_param.fifo_depth;
487 if (dev->i2c_param.max_req == ALTERA_I2C_100KHZ)
488 dev->bus_clk_rate = 100000;
489 else if (dev->i2c_param.max_req == ALTERA_I2C_400KHZ)
490 /* i2c bus clk 400KHz*/
491 dev->bus_clk_rate = 400000;
493 /* i2c input clock for vista creek is 100MHz */
494 dev->i2c_clk = dev->i2c_param.ref_clk * 1000000;
495 dev->xfer = altera_i2c_xfer;
497 if (pthread_mutex_init(&dev->lock, NULL))
499 dev->mutex = &dev->lock;
501 altera_i2c_hardware_init(dev);
506 void altera_i2c_remove(struct altera_i2c_dev *dev)
509 pthread_mutex_destroy(&dev->lock);
510 altera_i2c_disable(dev);