1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2010-2019 Intel Corporation
5 #include "opae_intel_max10.h"
8 static struct intel_max10_device *g_max10;
10 int max10_reg_read(unsigned int reg, unsigned int *val)
15 return spi_transaction_read(g_max10->spi_tran_dev,
16 reg, 4, (unsigned char *)val);
19 int max10_reg_write(unsigned int reg, unsigned int val)
21 unsigned int tmp = val;
26 return spi_transaction_write(g_max10->spi_tran_dev,
27 reg, 4, (unsigned char *)&tmp);
30 static struct max10_compatible_id max10_id_table[] = {
31 {.compatible = MAX10_PAC,},
32 {.compatible = MAX10_PAC_N3000,},
33 {.compatible = MAX10_PAC_END,}
36 static struct max10_compatible_id *max10_match_compatible(const char *fdt_root)
38 struct max10_compatible_id *id = max10_id_table;
40 for (; strcmp(id->compatible, MAX10_PAC_END); id++) {
41 if (fdt_node_check_compatible(fdt_root, 0, id->compatible))
51 is_max10_pac_n3000(struct intel_max10_device *max10)
53 return max10->id && !strcmp(max10->id->compatible,
57 static void max10_check_capability(struct intel_max10_device *max10)
62 if (is_max10_pac_n3000(max10)) {
63 max10->flags |= MAX10_FLAGS_NO_I2C2 |
64 MAX10_FLAGS_NO_BMCIMG_FLASH;
65 dev_info(max10, "found %s card\n", max10->id->compatible);
69 static int altera_nor_flash_read(u32 offset,
70 void *buffer, u32 len)
74 unsigned int *buf = (unsigned int *)buffer;
78 if (!buffer || len <= 0)
83 for (i = 0; i < word_len; i++) {
84 ret = max10_reg_read(offset + i*4,
95 static int enable_nor_flash(bool on)
100 ret = max10_reg_read(RSU_REG_OFF, &val);
102 dev_err(NULL "enabling flash error\n");
111 return max10_reg_write(RSU_REG_OFF, val);
114 static int init_max10_device_table(struct intel_max10_device *max10)
116 struct max10_compatible_id *id;
117 struct fdt_header hdr;
118 char *fdt_root = NULL;
120 u32 dt_size, dt_addr, val;
123 ret = max10_reg_read(DT_AVAIL_REG_OFF, &val);
125 dev_err(max10 "cannot read DT_AVAIL_REG\n");
129 if (!(val & DT_AVAIL)) {
130 dev_err(max10 "DT not available\n");
134 ret = max10_reg_read(DT_BASE_ADDR_REG_OFF, &dt_addr);
136 dev_info(max10 "cannot get base addr of device table\n");
140 ret = enable_nor_flash(true);
142 dev_err(max10 "fail to enable flash\n");
146 ret = altera_nor_flash_read(dt_addr, &hdr, sizeof(hdr));
148 dev_err(max10 "read fdt header fail\n");
152 ret = fdt_check_header(&hdr);
154 dev_err(max10 "check fdt header fail\n");
158 dt_size = fdt_totalsize(&hdr);
159 if (dt_size > DFT_MAX_SIZE) {
160 dev_err(max10 "invalid device table size\n");
165 fdt_root = opae_malloc(dt_size);
171 ret = altera_nor_flash_read(dt_addr, fdt_root, dt_size);
173 dev_err(max10 "cannot read device table\n");
177 id = max10_match_compatible(fdt_root);
179 dev_err(max10 "max10 compatible not found\n");
184 max10->flags |= MAX10_FLAGS_DEVICE_TABLE;
187 max10->fdt_root = fdt_root;
190 ret = enable_nor_flash(false);
198 struct intel_max10_device *
199 intel_max10_device_probe(struct altera_spi_device *spi,
202 struct intel_max10_device *dev;
206 dev = opae_malloc(sizeof(*dev));
210 dev->spi_master = spi;
212 dev->spi_tran_dev = spi_transaction_init(spi, chipselect);
213 if (!dev->spi_tran_dev) {
214 dev_err(dev, "%s spi tran init fail\n", __func__);
218 /* set the max10 device firstly */
221 /* init the MAX10 device table */
222 ret = init_max10_device_table(dev);
224 dev_err(dev, "init max10 device table fail\n");
228 max10_check_capability(dev);
230 /* read FPGA loading information */
231 ret = max10_reg_read(FPGA_PAGE_INFO_OFF, &val);
233 dev_err(dev, "fail to get FPGA loading info\n");
236 dev_info(dev, "FPGA loaded from %s Image\n", val ? "User" : "Factory");
242 opae_free(dev->fdt_root);
243 spi_transaction_remove(dev->spi_tran_dev);
251 int intel_max10_device_remove(struct intel_max10_device *dev)
256 if (dev->spi_tran_dev)
257 spi_transaction_remove(dev->spi_tran_dev);
260 opae_free(dev->fdt_root);