1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2019 Intel Corporation
5 #ifndef _OPAE_INTEL_MAX10_H_
6 #define _OPAE_INTEL_MAX10_H_
8 #include "opae_osdep.h"
11 struct max10_compatible_id {
15 #define MAX10_PAC "intel,max10"
16 #define MAX10_PAC_N3000 "intel,max10-pac-n3000"
17 #define MAX10_PAC_END "intel,end"
19 /* max10 capability flags */
20 #define MAX10_FLAGS_NO_I2C2 BIT(0)
21 #define MAX10_FLAGS_NO_BMCIMG_FLASH BIT(1)
22 #define MAX10_FLAGS_DEVICE_TABLE BIT(2)
23 #define MAX10_FLAGS_SPI BIT(3)
24 #define MAX10_FLGAS_NIOS_SPI BIT(4)
25 #define MAX10_FLAGS_PKVL BIT(5)
26 #define MAX10_FLAGS_SECURE BIT(6)
27 #define MAX10_FLAGS_MAC_CACHE BIT(7)
29 struct intel_max10_device {
30 unsigned int flags; /*max10 hardware capability*/
31 struct altera_spi_device *spi_master;
32 struct spi_transaction_dev *spi_tran_dev;
33 struct max10_compatible_id *id; /*max10 compatible*/
35 unsigned int base; /* max10 base address */
51 struct opae_retimer_info {
52 unsigned int nums_retimer;
53 unsigned int ports_per_retimer;
54 unsigned int nums_fvl;
55 unsigned int ports_per_fvl;
56 enum retimer_speed support_speed;
60 struct opae_retimer_status {
61 enum retimer_speed speed;
63 * retimer line link status bitmap:
64 * bit 0: Retimer0 Port0 link status
65 * bit 1: Retimer0 Port1 link status
66 * bit 2: Retimer0 Port2 link status
67 * bit 3: Retimer0 Port3 link status
69 * bit 4: Retimer1 Port0 link status
70 * bit 5: Retimer1 Port1 link status
71 * bit 6: Retimer1 Port2 link status
72 * bit 7: Retimer1 Port3 link status
74 unsigned int line_link_bitmap;
77 #define FLASH_BASE 0x10000000
78 #define FLASH_OPTION_BITS 0x10000
80 /* System Registers */
81 #define MAX10_BASE_ADDR 0x300400
82 #define MAX10_SEC_BASE_ADDR 0x300800
83 /* Register offset of system registers */
84 #define NIOS2_FW_VERSION 0x0
85 #define MAX10_MACADDR1 0x10
86 #define MAX10_MAC_BYTE4 GENMASK(7, 0)
87 #define MAX10_MAC_BYTE3 GENMASK(15, 8)
88 #define MAX10_MAC_BYTE2 GENMASK(23, 16)
89 #define MAX10_MAC_BYTE1 GENMASK(31, 24)
90 #define MAX10_MACADDR2 0x14
91 #define MAX10_MAC_BYTE6 GENMASK(7, 0)
92 #define MAX10_MAC_BYTE5 GENMASK(15, 8)
93 #define MAX10_MAC_COUNT GENMASK(23, 16)
95 #define FPGA_RECONF_PAGE GENMASK(2, 0)
96 #define FPGA_RP_LOAD BIT(3)
97 #define NIOS2_PRERESET BIT(4)
98 #define NIOS2_HANG BIT(5)
99 #define RSU_ENABLE BIT(6)
100 #define NIOS2_RESET BIT(7)
101 #define NIOS2_I2C2_POLL_STOP BIT(13)
102 #define PKVL_EEPROM_LOAD BIT(31)
103 #define FPGA_RECONF_REG 0x30
104 #define MAX10_TEST_REG 0x3c
105 #define COUNTDOWN_START BIT(18)
106 #define MAX10_BUILD_VER 0x68
107 #define MAX10_VERSION_MAJOR GENMASK(23, 16)
108 #define PCB_INFO GENMASK(31, 24)
109 #define FPGA_PAGE_INFO 0x6c
110 #define DT_AVAIL_REG 0x90
111 #define DT_AVAIL BIT(0)
112 #define DT_BASE_ADDR_REG 0x94
113 #define MAX10_DOORBELL 0x400
114 #define RSU_REQUEST BIT(0)
115 #define SEC_PROGRESS GENMASK(7, 4)
116 #define HOST_STATUS GENMASK(11, 8)
117 #define SEC_STATUS GENMASK(23, 16)
119 /* PKVL related registers, in system register region */
120 #define PKVL_POLLING_CTRL 0x80
121 #define POLLING_MODE GENMASK(15, 0)
122 #define PKVL_A_PRELOAD BIT(16)
123 #define PKVL_A_PRELOAD_TIMEOUT BIT(17)
124 #define PKVL_A_DATA_TOO_BIG BIT(18)
125 #define PKVL_A_HDR_CHECKSUM BIT(20)
126 #define PKVL_B_PRELOAD BIT(24)
127 #define PKVL_B_PRELOAD_TIMEOUT BIT(25)
128 #define PKVL_B_DATA_TOO_BIG BIT(26)
129 #define PKVL_B_HDR_CHECKSUM BIT(28)
130 #define PKVL_EEPROM_UPG_STATUS GENMASK(31, 16)
131 #define PKVL_LINK_STATUS 0x164
132 #define PKVL_A_VERSION 0x254
133 #define PKVL_B_VERSION 0x258
134 #define SERDES_VERSION GENMASK(15, 0)
135 #define SBUS_VERSION GENMASK(31, 16)
137 #define DFT_MAX_SIZE 0x7e0000
139 int max10_reg_read(unsigned int reg, unsigned int *val);
140 int max10_reg_write(unsigned int reg, unsigned int val);
141 int max10_sys_read(unsigned int offset, unsigned int *val);
142 int max10_sys_write(unsigned int offset, unsigned int val);
143 struct intel_max10_device *
144 intel_max10_device_probe(struct altera_spi_device *spi,
146 int intel_max10_device_remove(struct intel_max10_device *dev);
148 /** List of opae sensors */
149 TAILQ_HEAD(opae_sensor_list, opae_sensor_info);
151 #define SENSOR_REG_VALUE 0x0
152 #define SENSOR_REG_HIGH_WARN 0x1
153 #define SENSOR_REG_HIGH_FATAL 0x2
154 #define SENSOR_REG_LOW_WARN 0x3
155 #define SENSOR_REG_LOW_FATAL 0x4
156 #define SENSOR_REG_HYSTERESIS 0x5
157 #define SENSOR_REG_MAX 0x6
159 static const char * const sensor_reg_name[] = {
173 struct raw_sensor_info {
177 unsigned int multiplier;
178 struct sensor_reg regs[SENSOR_REG_MAX];
181 #define OPAE_SENSOR_VALID 0x1
182 #define OPAE_SENSOR_HIGH_WARN_VALID 0x2
183 #define OPAE_SENSOR_HIGH_FATAL_VALID 0x4
184 #define OPAE_SENSOR_LOW_WARN_VALID 0x8
185 #define OPAE_SENSOR_LOW_FATAL_VALID 0x10
186 #define OPAE_SENSOR_HYSTERESIS_VALID 0x20
188 struct opae_sensor_info {
189 TAILQ_ENTRY(opae_sensor_info) node;
193 unsigned int high_fatal;
194 unsigned int high_warn;
195 unsigned int low_fatal;
196 unsigned int low_warn;
197 unsigned int hysteresis;
198 unsigned int multiplier;
201 unsigned int value_reg;