1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2010-2018 Intel Corporation
11 #include <sys/ioctl.h>
12 #include <sys/epoll.h>
15 #include <rte_malloc.h>
16 #include <rte_devargs.h>
17 #include <rte_memcpy.h>
19 #include <rte_bus_pci.h>
20 #include <rte_kvargs.h>
21 #include <rte_alarm.h>
22 #include <rte_interrupts.h>
23 #include <rte_errno.h>
24 #include <rte_per_lcore.h>
25 #include <rte_memory.h>
26 #include <rte_memzone.h>
28 #include <rte_common.h>
29 #include <rte_bus_vdev.h>
30 #include <rte_string_fns.h>
31 #include <rte_pmd_i40e.h>
33 #include "base/opae_hw_api.h"
34 #include "base/opae_ifpga_hw_api.h"
35 #include "base/ifpga_api.h"
36 #include "rte_rawdev.h"
37 #include "rte_rawdev_pmd.h"
38 #include "rte_bus_ifpga.h"
39 #include "ifpga_common.h"
40 #include "ifpga_logs.h"
41 #include "ifpga_rawdev.h"
42 #include "ipn3ke_rawdev_api.h"
44 #define PCI_VENDOR_ID_INTEL 0x8086
46 #define PCIE_DEVICE_ID_PF_INT_5_X 0xBCBD
47 #define PCIE_DEVICE_ID_PF_INT_6_X 0xBCC0
48 #define PCIE_DEVICE_ID_PF_DSC_1_X 0x09C4
49 #define PCIE_DEVICE_ID_PAC_N3000 0x0B30
51 #define PCIE_DEVICE_ID_VF_INT_5_X 0xBCBF
52 #define PCIE_DEVICE_ID_VF_INT_6_X 0xBCC1
53 #define PCIE_DEVICE_ID_VF_DSC_1_X 0x09C5
54 #define PCIE_DEVICE_ID_VF_PAC_N3000 0x0B31
55 #define RTE_MAX_RAW_DEVICE 10
57 static const struct rte_pci_id pci_ifpga_map[] = {
58 { RTE_PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_PF_INT_5_X) },
59 { RTE_PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_VF_INT_5_X) },
60 { RTE_PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_PF_INT_6_X) },
61 { RTE_PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_VF_INT_6_X) },
62 { RTE_PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_PF_DSC_1_X) },
63 { RTE_PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_VF_DSC_1_X) },
64 { RTE_PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_PAC_N3000),},
65 { RTE_PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_VF_PAC_N3000),},
66 { .vendor_id = 0, /* sentinel */ },
69 static struct ifpga_rawdev ifpga_rawdevices[IFPGA_RAWDEV_NUM];
71 static int ifpga_monitor_start;
72 static pthread_t ifpga_monitor_start_thread;
74 #define IFPGA_MAX_IRQ 12
75 /* 0 for FME interrupt, others are reserved for AFU irq */
76 static struct rte_intr_handle ifpga_irq_handle[IFPGA_MAX_IRQ];
78 static struct ifpga_rawdev *
79 ifpga_rawdev_allocate(struct rte_rawdev *rawdev);
80 static int set_surprise_link_check_aer(
81 struct ifpga_rawdev *ifpga_rdev, int force_disable);
82 static int ifpga_pci_find_next_ext_capability(unsigned int fd,
83 int start, uint32_t cap);
84 static int ifpga_pci_find_ext_capability(unsigned int fd, uint32_t cap);
87 ifpga_rawdev_get(const struct rte_rawdev *rawdev)
89 struct ifpga_rawdev *dev;
95 for (i = 0; i < IFPGA_RAWDEV_NUM; i++) {
96 dev = &ifpga_rawdevices[i];
97 if (dev->rawdev == rawdev)
104 static inline uint8_t
105 ifpga_rawdev_find_free_device_index(void)
109 for (dev_id = 0; dev_id < IFPGA_RAWDEV_NUM; dev_id++) {
110 if (ifpga_rawdevices[dev_id].rawdev == NULL)
114 return IFPGA_RAWDEV_NUM;
116 static struct ifpga_rawdev *
117 ifpga_rawdev_allocate(struct rte_rawdev *rawdev)
119 struct ifpga_rawdev *dev;
122 dev = ifpga_rawdev_get(rawdev);
124 IFPGA_RAWDEV_PMD_ERR("Event device already allocated!");
128 dev_id = ifpga_rawdev_find_free_device_index();
129 if (dev_id == IFPGA_RAWDEV_NUM) {
130 IFPGA_RAWDEV_PMD_ERR("Reached maximum number of raw devices");
134 dev = &ifpga_rawdevices[dev_id];
135 dev->rawdev = rawdev;
136 dev->dev_id = dev_id;
142 ifpga_pci_find_next_ext_capability(unsigned int fd, int start, uint32_t cap)
146 int pos = RTE_PCI_CFG_SPACE_SIZE;
149 /* minimum 8 bytes per capability */
150 ttl = (RTE_PCI_CFG_SPACE_EXP_SIZE - RTE_PCI_CFG_SPACE_SIZE) / 8;
154 ret = pread(fd, &header, sizeof(header), pos);
159 * If we have no capabilities, this is indicated by cap ID,
160 * cap version and next pointer all being 0.
166 if (RTE_PCI_EXT_CAP_ID(header) == cap && pos != start)
169 pos = RTE_PCI_EXT_CAP_NEXT(header);
170 if (pos < RTE_PCI_CFG_SPACE_SIZE)
172 ret = pread(fd, &header, sizeof(header), pos);
181 ifpga_pci_find_ext_capability(unsigned int fd, uint32_t cap)
183 return ifpga_pci_find_next_ext_capability(fd, 0, cap);
186 static int ifpga_get_dev_vendor_id(const char *bdf,
187 uint32_t *dev_id, uint32_t *vendor_id)
194 strlcpy(path, "/sys/bus/pci/devices/", sizeof(path));
195 strlcat(path, bdf, sizeof(path));
196 strlcat(path, "/config", sizeof(path));
197 fd = open(path, O_RDWR);
200 ret = pread(fd, &header, sizeof(header), 0);
205 (*vendor_id) = header & 0xffff;
206 (*dev_id) = (header >> 16) & 0xffff;
211 static int ifpga_rawdev_fill_info(struct ifpga_rawdev *ifpga_dev,
214 char path[1024] = "/sys/bus/pci/devices/0000:";
215 char link[1024], link1[1024];
216 char dir[1024] = "/sys/devices/";
219 char sub_brg_bdf[4][16];
222 struct dirent *entry;
225 unsigned int dom, bus, dev;
227 uint32_t dev_id, vendor_id;
229 strlcat(path, bdf, sizeof(path));
230 memset(link, 0, sizeof(link));
231 memset(link1, 0, sizeof(link1));
232 ret = readlink(path, link, (sizeof(link)-1));
235 strlcpy(link1, link, sizeof(link1));
236 memset(ifpga_dev->parent_bdf, 0, 16);
237 point = strlen(link);
245 rte_memcpy(ifpga_dev->parent_bdf, &link[point], 12);
247 point = strlen(link1);
255 c = strchr(link1, 'p');
258 strlcat(dir, c, sizeof(dir));
265 while ((entry = readdir(dp)) != NULL) {
268 if (entry->d_name[0] == '.')
270 if (strlen(entry->d_name) > 12)
272 if (sscanf(entry->d_name, "%x:%x:%x.%d",
273 &dom, &bus, &dev, &func) < 4)
276 strlcpy(sub_brg_bdf[i],
278 sizeof(sub_brg_bdf[i]));
284 /* get fpga and fvl */
286 for (i = 0; i < 4; i++) {
287 strlcpy(link, dir, sizeof(link));
288 strlcat(link, "/", sizeof(link));
289 strlcat(link, sub_brg_bdf[i], sizeof(link));
293 while ((entry = readdir(dp)) != NULL) {
296 if (entry->d_name[0] == '.')
299 if (strlen(entry->d_name) > 12)
301 if (sscanf(entry->d_name, "%x:%x:%x.%d",
302 &dom, &bus, &dev, &func) < 4)
305 if (ifpga_get_dev_vendor_id(entry->d_name,
306 &dev_id, &vendor_id))
308 if (vendor_id == 0x8086 &&
312 strlcpy(ifpga_dev->fvl_bdf[j],
314 sizeof(ifpga_dev->fvl_bdf[j]));
325 #define HIGH_FATAL(_sens, value)\
326 (((_sens)->flags & OPAE_SENSOR_HIGH_FATAL_VALID) &&\
327 (value > (_sens)->high_fatal))
329 #define HIGH_WARN(_sens, value)\
330 (((_sens)->flags & OPAE_SENSOR_HIGH_WARN_VALID) &&\
331 (value > (_sens)->high_warn))
333 #define LOW_FATAL(_sens, value)\
334 (((_sens)->flags & OPAE_SENSOR_LOW_FATAL_VALID) &&\
335 (value > (_sens)->low_fatal))
337 #define LOW_WARN(_sens, value)\
338 (((_sens)->flags & OPAE_SENSOR_LOW_WARN_VALID) &&\
339 (value > (_sens)->low_warn))
341 #define AUX_VOLTAGE_WARN 11400
344 ifpga_monitor_sensor(struct rte_rawdev *raw_dev,
347 struct opae_adapter *adapter;
348 struct opae_manager *mgr;
349 struct opae_sensor_info *sensor;
353 adapter = ifpga_rawdev_get_priv(raw_dev);
357 mgr = opae_adapter_get_mgr(adapter);
361 opae_mgr_for_each_sensor(mgr, sensor) {
362 if (!(sensor->flags & OPAE_SENSOR_VALID))
365 ret = opae_mgr_get_sensor_value(mgr, sensor, &value);
369 if (value == 0xdeadbeef) {
370 IFPGA_RAWDEV_PMD_ERR("dev_id %d sensor %s value %x\n",
371 raw_dev->dev_id, sensor->name, value);
375 /* monitor temperature sensors */
376 if (!strcmp(sensor->name, "Board Temperature") ||
377 !strcmp(sensor->name, "FPGA Die Temperature")) {
378 IFPGA_RAWDEV_PMD_INFO("read sensor %s %d %d %d\n",
379 sensor->name, value, sensor->high_warn,
382 if (HIGH_WARN(sensor, value) ||
383 LOW_WARN(sensor, value)) {
384 IFPGA_RAWDEV_PMD_INFO("%s reach theshold %d\n",
385 sensor->name, value);
391 /* monitor 12V AUX sensor */
392 if (!strcmp(sensor->name, "12V AUX Voltage")) {
393 if (value < AUX_VOLTAGE_WARN) {
394 IFPGA_RAWDEV_PMD_INFO(
395 "%s reach theshold %d mV\n",
396 sensor->name, value);
408 static int set_surprise_link_check_aer(
409 struct ifpga_rawdev *ifpga_rdev, int force_disable)
411 struct rte_rawdev *rdev;
418 uint32_t aer_new0, aer_new1;
421 printf("\n device does not exist\n");
425 rdev = ifpga_rdev->rawdev;
426 if (ifpga_rdev->aer_enable)
428 if (ifpga_monitor_sensor(rdev, &enable))
430 if (enable || force_disable) {
431 IFPGA_RAWDEV_PMD_ERR("Set AER, pls graceful shutdown\n");
432 ifpga_rdev->aer_enable = 1;
434 strlcpy(path, "/sys/bus/pci/devices/", sizeof(path));
435 strlcat(path, ifpga_rdev->parent_bdf, sizeof(path));
436 strlcat(path, "/config", sizeof(path));
437 fd = open(path, O_RDWR);
440 pos = ifpga_pci_find_ext_capability(fd, RTE_PCI_EXT_CAP_ID_ERR);
443 /* save previout ECAP_AER+0x08 */
444 ret = pread(fd, &data, sizeof(data), pos+0x08);
447 ifpga_rdev->aer_old[0] = data;
448 /* save previout ECAP_AER+0x14 */
449 ret = pread(fd, &data, sizeof(data), pos+0x14);
452 ifpga_rdev->aer_old[1] = data;
454 /* set ECAP_AER+0x08 to 0xFFFFFFFF */
456 ret = pwrite(fd, &data, 4, pos+0x08);
459 /* set ECAP_AER+0x14 to 0xFFFFFFFF */
460 ret = pwrite(fd, &data, 4, pos+0x14);
464 /* read current ECAP_AER+0x08 */
465 ret = pread(fd, &data, sizeof(data), pos+0x08);
469 /* read current ECAP_AER+0x14 */
470 ret = pread(fd, &data, sizeof(data), pos+0x14);
478 printf(">>>>>>Set AER %x,%x %x,%x\n",
479 ifpga_rdev->aer_old[0], ifpga_rdev->aer_old[1],
492 ifpga_rawdev_gsd_handle(__rte_unused void *param)
494 struct ifpga_rawdev *ifpga_rdev;
501 for (i = 0; i < IFPGA_RAWDEV_NUM; i++) {
502 ifpga_rdev = &ifpga_rawdevices[i];
503 if (ifpga_rdev->rawdev) {
504 ret = set_surprise_link_check_aer(ifpga_rdev,
506 if (ret == 1 && !gsd_enable) {
514 printf(">>>>>>Pls Shutdown APP\n");
516 rte_delay_us(100 * MS);
523 ifpga_monitor_start_func(void)
527 if (ifpga_monitor_start == 0) {
528 ret = pthread_create(&ifpga_monitor_start_thread,
530 ifpga_rawdev_gsd_handle, NULL);
532 IFPGA_RAWDEV_PMD_ERR(
533 "Fail to create ifpga nonitor thread");
536 ifpga_monitor_start = 1;
542 ifpga_monitor_stop_func(void)
546 if (ifpga_monitor_start == 1) {
547 ret = pthread_cancel(ifpga_monitor_start_thread);
549 IFPGA_RAWDEV_PMD_ERR("Can't cancel the thread");
551 ret = pthread_join(ifpga_monitor_start_thread, NULL);
553 IFPGA_RAWDEV_PMD_ERR("Can't join the thread");
555 ifpga_monitor_start = 0;
564 ifpga_fill_afu_dev(struct opae_accelerator *acc,
565 struct rte_afu_device *afu_dev)
567 struct rte_mem_resource *res = afu_dev->mem_resource;
568 struct opae_acc_region_info region_info;
569 struct opae_acc_info info;
573 ret = opae_acc_get_info(acc, &info);
577 if (info.num_regions > PCI_MAX_RESOURCE)
580 afu_dev->num_region = info.num_regions;
582 for (i = 0; i < info.num_regions; i++) {
583 region_info.index = i;
584 ret = opae_acc_get_region_info(acc, ®ion_info);
588 if ((region_info.flags & ACC_REGION_MMIO) &&
589 (region_info.flags & ACC_REGION_READ) &&
590 (region_info.flags & ACC_REGION_WRITE)) {
591 res[i].phys_addr = region_info.phys_addr;
592 res[i].len = region_info.len;
593 res[i].addr = region_info.addr;
602 ifpga_rawdev_info_get(struct rte_rawdev *dev,
603 rte_rawdev_obj_t dev_info,
604 size_t dev_info_size)
606 struct opae_adapter *adapter;
607 struct opae_accelerator *acc;
608 struct rte_afu_device *afu_dev;
609 struct opae_manager *mgr = NULL;
610 struct opae_eth_group_region_info opae_lside_eth_info;
611 struct opae_eth_group_region_info opae_nside_eth_info;
612 int lside_bar_idx, nside_bar_idx;
614 IFPGA_RAWDEV_PMD_FUNC_TRACE();
616 if (!dev_info || dev_info_size != sizeof(*afu_dev)) {
617 IFPGA_RAWDEV_PMD_ERR("Invalid request");
621 adapter = ifpga_rawdev_get_priv(dev);
626 afu_dev->rawdev = dev;
628 /* find opae_accelerator and fill info into afu_device */
629 opae_adapter_for_each_acc(adapter, acc) {
630 if (acc->index != afu_dev->id.port)
633 if (ifpga_fill_afu_dev(acc, afu_dev)) {
634 IFPGA_RAWDEV_PMD_ERR("cannot get info\n");
639 /* get opae_manager to rawdev */
640 mgr = opae_adapter_get_mgr(adapter);
642 /* get LineSide BAR Index */
643 if (opae_manager_get_eth_group_region_info(mgr, 0,
644 &opae_lside_eth_info)) {
647 lside_bar_idx = opae_lside_eth_info.mem_idx;
649 /* get NICSide BAR Index */
650 if (opae_manager_get_eth_group_region_info(mgr, 1,
651 &opae_nside_eth_info)) {
654 nside_bar_idx = opae_nside_eth_info.mem_idx;
656 if (lside_bar_idx >= PCI_MAX_RESOURCE ||
657 nside_bar_idx >= PCI_MAX_RESOURCE ||
658 lside_bar_idx == nside_bar_idx)
661 /* fill LineSide BAR Index */
662 afu_dev->mem_resource[lside_bar_idx].phys_addr =
663 opae_lside_eth_info.phys_addr;
664 afu_dev->mem_resource[lside_bar_idx].len =
665 opae_lside_eth_info.len;
666 afu_dev->mem_resource[lside_bar_idx].addr =
667 opae_lside_eth_info.addr;
669 /* fill NICSide BAR Index */
670 afu_dev->mem_resource[nside_bar_idx].phys_addr =
671 opae_nside_eth_info.phys_addr;
672 afu_dev->mem_resource[nside_bar_idx].len =
673 opae_nside_eth_info.len;
674 afu_dev->mem_resource[nside_bar_idx].addr =
675 opae_nside_eth_info.addr;
681 ifpga_rawdev_configure(const struct rte_rawdev *dev,
682 rte_rawdev_obj_t config,
683 size_t config_size __rte_unused)
685 IFPGA_RAWDEV_PMD_FUNC_TRACE();
687 RTE_FUNC_PTR_OR_ERR_RET(dev, -EINVAL);
689 return config ? 0 : 1;
693 ifpga_rawdev_start(struct rte_rawdev *dev)
696 struct opae_adapter *adapter;
698 IFPGA_RAWDEV_PMD_FUNC_TRACE();
700 RTE_FUNC_PTR_OR_ERR_RET(dev, -EINVAL);
702 adapter = ifpga_rawdev_get_priv(dev);
710 ifpga_rawdev_stop(struct rte_rawdev *dev)
716 ifpga_rawdev_close(struct rte_rawdev *dev)
718 struct opae_adapter *adapter;
721 adapter = ifpga_rawdev_get_priv(dev);
723 opae_adapter_destroy(adapter);
724 opae_adapter_data_free(adapter->data);
732 ifpga_rawdev_reset(struct rte_rawdev *dev)
738 fpga_pr(struct rte_rawdev *raw_dev, u32 port_id, const char *buffer, u32 size,
742 struct opae_adapter *adapter;
743 struct opae_manager *mgr;
744 struct opae_accelerator *acc;
745 struct opae_bridge *br;
748 adapter = ifpga_rawdev_get_priv(raw_dev);
752 mgr = opae_adapter_get_mgr(adapter);
756 acc = opae_adapter_get_acc(adapter, port_id);
760 br = opae_acc_get_br(acc);
764 ret = opae_manager_flash(mgr, port_id, buffer, size, status);
766 IFPGA_RAWDEV_PMD_ERR("%s pr error %d\n", __func__, ret);
770 ret = opae_bridge_reset(br);
772 IFPGA_RAWDEV_PMD_ERR("%s reset port:%d error %d\n",
773 __func__, port_id, ret);
781 rte_fpga_do_pr(struct rte_rawdev *rawdev, int port_id,
782 const char *file_name)
784 struct stat file_stat;
794 file_fd = open(file_name, O_RDONLY);
796 IFPGA_RAWDEV_PMD_ERR("%s: open file error: %s\n",
797 __func__, file_name);
798 IFPGA_RAWDEV_PMD_ERR("Message : %s\n", strerror(errno));
801 ret = stat(file_name, &file_stat);
803 IFPGA_RAWDEV_PMD_ERR("stat on bitstream file failed: %s\n",
808 buffer_size = file_stat.st_size;
809 if (buffer_size <= 0) {
814 IFPGA_RAWDEV_PMD_INFO("bitstream file size: %zu\n", buffer_size);
815 buffer = rte_malloc(NULL, buffer_size, 0);
821 /*read the raw data*/
822 if (buffer_size != read(file_fd, (void *)buffer, buffer_size)) {
828 ret = fpga_pr(rawdev, port_id, buffer, buffer_size, &pr_error);
829 IFPGA_RAWDEV_PMD_INFO("downloading to device port %d....%s.\n", port_id,
830 ret ? "failed" : "success");
846 ifpga_rawdev_pr(struct rte_rawdev *dev,
847 rte_rawdev_obj_t pr_conf)
849 struct opae_adapter *adapter;
850 struct opae_manager *mgr;
851 struct opae_board_info *info;
852 struct rte_afu_pr_conf *afu_pr_conf;
855 struct opae_accelerator *acc;
857 IFPGA_RAWDEV_PMD_FUNC_TRACE();
859 adapter = ifpga_rawdev_get_priv(dev);
866 afu_pr_conf = pr_conf;
868 if (afu_pr_conf->pr_enable) {
869 ret = rte_fpga_do_pr(dev,
870 afu_pr_conf->afu_id.port,
871 afu_pr_conf->bs_path);
873 IFPGA_RAWDEV_PMD_ERR("do pr error %d\n", ret);
878 mgr = opae_adapter_get_mgr(adapter);
880 IFPGA_RAWDEV_PMD_ERR("opae_manager of opae_adapter is NULL");
884 if (ifpga_mgr_ops.get_board_info(mgr, &info)) {
885 IFPGA_RAWDEV_PMD_ERR("ifpga manager get_board_info fail!");
889 if (info->lightweight) {
890 /* set uuid to all 0, when fpga is lightweight image */
891 memset(&afu_pr_conf->afu_id.uuid.uuid_low, 0, sizeof(u64));
892 memset(&afu_pr_conf->afu_id.uuid.uuid_high, 0, sizeof(u64));
894 acc = opae_adapter_get_acc(adapter, afu_pr_conf->afu_id.port);
898 ret = opae_acc_get_uuid(acc, &uuid);
902 rte_memcpy(&afu_pr_conf->afu_id.uuid.uuid_low, uuid.b,
904 rte_memcpy(&afu_pr_conf->afu_id.uuid.uuid_high, uuid.b + 8,
907 IFPGA_RAWDEV_PMD_INFO("%s: uuid_l=0x%lx, uuid_h=0x%lx\n",
909 (unsigned long)afu_pr_conf->afu_id.uuid.uuid_low,
910 (unsigned long)afu_pr_conf->afu_id.uuid.uuid_high);
916 ifpga_rawdev_get_attr(struct rte_rawdev *dev,
917 const char *attr_name, uint64_t *attr_value)
919 struct opae_adapter *adapter;
920 struct opae_manager *mgr;
921 struct opae_retimer_info opae_rtm_info;
922 struct opae_retimer_status opae_rtm_status;
923 struct opae_eth_group_info opae_eth_grp_info;
924 struct opae_eth_group_region_info opae_eth_grp_reg_info;
925 int eth_group_num = 0;
926 uint64_t port_link_bitmap = 0, port_link_bit;
929 #define MAX_PORT_PER_RETIMER 4
931 IFPGA_RAWDEV_PMD_FUNC_TRACE();
933 if (!dev || !attr_name || !attr_value) {
934 IFPGA_RAWDEV_PMD_ERR("Invalid arguments for getting attributes");
938 adapter = ifpga_rawdev_get_priv(dev);
940 IFPGA_RAWDEV_PMD_ERR("Adapter of dev %s is NULL", dev->name);
944 mgr = opae_adapter_get_mgr(adapter);
946 IFPGA_RAWDEV_PMD_ERR("opae_manager of opae_adapter is NULL");
950 /* currently, eth_group_num is always 2 */
951 eth_group_num = opae_manager_get_eth_group_nums(mgr);
952 if (eth_group_num < 0)
955 if (!strcmp(attr_name, "LineSideBaseMAC")) {
956 /* Currently FPGA not implement, so just set all zeros*/
957 *attr_value = (uint64_t)0;
960 if (!strcmp(attr_name, "LineSideMACType")) {
961 /* eth_group 0 on FPGA connect to LineSide */
962 if (opae_manager_get_eth_group_info(mgr, 0,
965 switch (opae_eth_grp_info.speed) {
968 (uint64_t)(IFPGA_RAWDEV_RETIMER_MAC_TYPE_10GE_XFI);
972 (uint64_t)(IFPGA_RAWDEV_RETIMER_MAC_TYPE_25GE_25GAUI);
976 (uint64_t)(IFPGA_RAWDEV_RETIMER_MAC_TYPE_UNKNOWN);
981 if (!strcmp(attr_name, "LineSideLinkSpeed")) {
982 if (opae_manager_get_retimer_status(mgr, &opae_rtm_status))
984 switch (opae_rtm_status.speed) {
987 (uint64_t)(IFPGA_RAWDEV_LINK_SPEED_UNKNOWN);
991 (uint64_t)(IFPGA_RAWDEV_LINK_SPEED_UNKNOWN);
995 (uint64_t)(IFPGA_RAWDEV_LINK_SPEED_UNKNOWN);
999 (uint64_t)(IFPGA_RAWDEV_LINK_SPEED_10GB);
1003 (uint64_t)(IFPGA_RAWDEV_LINK_SPEED_25GB);
1007 (uint64_t)(IFPGA_RAWDEV_LINK_SPEED_40GB);
1011 (uint64_t)(IFPGA_RAWDEV_LINK_SPEED_UNKNOWN);
1013 case MXD_SPEED_UNKNOWN:
1015 (uint64_t)(IFPGA_RAWDEV_LINK_SPEED_UNKNOWN);
1019 (uint64_t)(IFPGA_RAWDEV_LINK_SPEED_UNKNOWN);
1024 if (!strcmp(attr_name, "LineSideLinkRetimerNum")) {
1025 if (opae_manager_get_retimer_info(mgr, &opae_rtm_info))
1027 *attr_value = (uint64_t)(opae_rtm_info.nums_retimer);
1030 if (!strcmp(attr_name, "LineSideLinkPortNum")) {
1031 if (opae_manager_get_retimer_info(mgr, &opae_rtm_info))
1033 uint64_t tmp = (uint64_t)opae_rtm_info.ports_per_retimer *
1034 (uint64_t)opae_rtm_info.nums_retimer;
1038 if (!strcmp(attr_name, "LineSideLinkStatus")) {
1039 if (opae_manager_get_retimer_info(mgr, &opae_rtm_info))
1041 if (opae_manager_get_retimer_status(mgr, &opae_rtm_status))
1045 port_link_bitmap = (uint64_t)(opae_rtm_status.line_link_bitmap);
1046 for (i = 0; i < opae_rtm_info.nums_retimer; i++) {
1047 p = i * MAX_PORT_PER_RETIMER;
1048 for (j = 0; j < opae_rtm_info.ports_per_retimer; j++) {
1050 IFPGA_BIT_SET(port_link_bit, (p+j));
1051 port_link_bit &= port_link_bitmap;
1053 IFPGA_BIT_SET((*attr_value), q);
1059 if (!strcmp(attr_name, "LineSideBARIndex")) {
1060 /* eth_group 0 on FPGA connect to LineSide */
1061 if (opae_manager_get_eth_group_region_info(mgr, 0,
1062 &opae_eth_grp_reg_info))
1064 *attr_value = (uint64_t)opae_eth_grp_reg_info.mem_idx;
1067 if (!strcmp(attr_name, "NICSideMACType")) {
1068 /* eth_group 1 on FPGA connect to NicSide */
1069 if (opae_manager_get_eth_group_info(mgr, 1,
1070 &opae_eth_grp_info))
1072 *attr_value = (uint64_t)(opae_eth_grp_info.speed);
1075 if (!strcmp(attr_name, "NICSideLinkSpeed")) {
1076 /* eth_group 1 on FPGA connect to NicSide */
1077 if (opae_manager_get_eth_group_info(mgr, 1,
1078 &opae_eth_grp_info))
1080 *attr_value = (uint64_t)(opae_eth_grp_info.speed);
1083 if (!strcmp(attr_name, "NICSideLinkPortNum")) {
1084 if (opae_manager_get_retimer_info(mgr, &opae_rtm_info))
1086 uint64_t tmp = (uint64_t)opae_rtm_info.nums_fvl *
1087 (uint64_t)opae_rtm_info.ports_per_fvl;
1091 if (!strcmp(attr_name, "NICSideLinkStatus"))
1093 if (!strcmp(attr_name, "NICSideBARIndex")) {
1094 /* eth_group 1 on FPGA connect to NicSide */
1095 if (opae_manager_get_eth_group_region_info(mgr, 1,
1096 &opae_eth_grp_reg_info))
1098 *attr_value = (uint64_t)opae_eth_grp_reg_info.mem_idx;
1102 IFPGA_RAWDEV_PMD_ERR("%s not support", attr_name);
1106 static const struct rte_rawdev_ops ifpga_rawdev_ops = {
1107 .dev_info_get = ifpga_rawdev_info_get,
1108 .dev_configure = ifpga_rawdev_configure,
1109 .dev_start = ifpga_rawdev_start,
1110 .dev_stop = ifpga_rawdev_stop,
1111 .dev_close = ifpga_rawdev_close,
1112 .dev_reset = ifpga_rawdev_reset,
1114 .queue_def_conf = NULL,
1115 .queue_setup = NULL,
1116 .queue_release = NULL,
1118 .attr_get = ifpga_rawdev_get_attr,
1121 .enqueue_bufs = NULL,
1122 .dequeue_bufs = NULL,
1127 .xstats_get_names = NULL,
1128 .xstats_get_by_name = NULL,
1129 .xstats_reset = NULL,
1131 .firmware_status_get = NULL,
1132 .firmware_version_get = NULL,
1133 .firmware_load = ifpga_rawdev_pr,
1134 .firmware_unload = NULL,
1136 .dev_selftest = NULL,
1140 ifpga_get_fme_error_prop(struct opae_manager *mgr,
1141 u64 prop_id, u64 *val)
1143 struct feature_prop prop;
1145 prop.feature_id = IFPGA_FME_FEATURE_ID_GLOBAL_ERR;
1146 prop.prop_id = prop_id;
1148 if (opae_manager_ifpga_get_prop(mgr, &prop))
1157 ifpga_set_fme_error_prop(struct opae_manager *mgr,
1158 u64 prop_id, u64 val)
1160 struct feature_prop prop;
1162 prop.feature_id = IFPGA_FME_FEATURE_ID_GLOBAL_ERR;
1163 prop.prop_id = prop_id;
1167 if (opae_manager_ifpga_set_prop(mgr, &prop))
1174 fme_err_read_seu_emr(struct opae_manager *mgr)
1179 ret = ifpga_get_fme_error_prop(mgr, FME_ERR_PROP_SEU_EMR_LOW, &val);
1183 IFPGA_RAWDEV_PMD_INFO("seu emr low: 0x%" PRIx64 "\n", val);
1185 ret = ifpga_get_fme_error_prop(mgr, FME_ERR_PROP_SEU_EMR_HIGH, &val);
1189 IFPGA_RAWDEV_PMD_INFO("seu emr high: 0x%" PRIx64 "\n", val);
1194 static int fme_clear_warning_intr(struct opae_manager *mgr)
1198 if (ifpga_set_fme_error_prop(mgr, FME_ERR_PROP_INJECT_ERRORS, 0))
1201 if (ifpga_get_fme_error_prop(mgr, FME_ERR_PROP_NONFATAL_ERRORS, &val))
1203 if ((val & 0x40) != 0)
1204 IFPGA_RAWDEV_PMD_INFO("clean not done\n");
1209 static int fme_clean_fme_error(struct opae_manager *mgr)
1213 if (ifpga_get_fme_error_prop(mgr, FME_ERR_PROP_ERRORS, &val))
1216 IFPGA_RAWDEV_PMD_DEBUG("before clean 0x%" PRIx64 "\n", val);
1218 ifpga_set_fme_error_prop(mgr, FME_ERR_PROP_CLEAR, val);
1220 if (ifpga_get_fme_error_prop(mgr, FME_ERR_PROP_ERRORS, &val))
1223 IFPGA_RAWDEV_PMD_DEBUG("after clean 0x%" PRIx64 "\n", val);
1229 fme_err_handle_error0(struct opae_manager *mgr)
1231 struct feature_fme_error0 fme_error0;
1234 if (ifpga_get_fme_error_prop(mgr, FME_ERR_PROP_ERRORS, &val))
1237 if (fme_clean_fme_error(mgr))
1240 fme_error0.csr = val;
1242 if (fme_error0.fabric_err)
1243 IFPGA_RAWDEV_PMD_ERR("Fabric error\n");
1244 else if (fme_error0.fabfifo_overflow)
1245 IFPGA_RAWDEV_PMD_ERR("Fabric fifo under/overflow error\n");
1246 else if (fme_error0.afu_acc_mode_err)
1247 IFPGA_RAWDEV_PMD_ERR("AFU PF/VF access mismatch detected\n");
1248 else if (fme_error0.pcie0cdc_parity_err)
1249 IFPGA_RAWDEV_PMD_ERR("PCIe0 CDC Parity Error\n");
1250 else if (fme_error0.cvlcdc_parity_err)
1251 IFPGA_RAWDEV_PMD_ERR("CVL CDC Parity Error\n");
1252 else if (fme_error0.fpgaseuerr)
1253 fme_err_read_seu_emr(mgr);
1255 /* clean the errors */
1256 if (ifpga_set_fme_error_prop(mgr, FME_ERR_PROP_ERRORS, val))
1263 fme_err_handle_catfatal_error(struct opae_manager *mgr)
1265 struct feature_fme_ras_catfaterror fme_catfatal;
1268 if (ifpga_get_fme_error_prop(mgr, FME_ERR_PROP_CATFATAL_ERRORS, &val))
1271 fme_catfatal.csr = val;
1273 if (fme_catfatal.cci_fatal_err)
1274 IFPGA_RAWDEV_PMD_ERR("CCI error detected\n");
1275 else if (fme_catfatal.fabric_fatal_err)
1276 IFPGA_RAWDEV_PMD_ERR("Fabric fatal error detected\n");
1277 else if (fme_catfatal.pcie_poison_err)
1278 IFPGA_RAWDEV_PMD_ERR("Poison error from PCIe ports\n");
1279 else if (fme_catfatal.inject_fata_err)
1280 IFPGA_RAWDEV_PMD_ERR("Injected Fatal Error\n");
1281 else if (fme_catfatal.crc_catast_err)
1282 IFPGA_RAWDEV_PMD_ERR("a catastrophic EDCRC error\n");
1283 else if (fme_catfatal.injected_catast_err)
1284 IFPGA_RAWDEV_PMD_ERR("Injected Catastrophic Error\n");
1285 else if (fme_catfatal.bmc_seu_catast_err)
1286 fme_err_read_seu_emr(mgr);
1292 fme_err_handle_nonfaterror(struct opae_manager *mgr)
1294 struct feature_fme_ras_nonfaterror nonfaterr;
1297 if (ifpga_get_fme_error_prop(mgr, FME_ERR_PROP_NONFATAL_ERRORS, &val))
1300 nonfaterr.csr = val;
1302 if (nonfaterr.temp_thresh_ap1)
1303 IFPGA_RAWDEV_PMD_INFO("Temperature threshold triggered AP1\n");
1304 else if (nonfaterr.temp_thresh_ap2)
1305 IFPGA_RAWDEV_PMD_INFO("Temperature threshold triggered AP2\n");
1306 else if (nonfaterr.pcie_error)
1307 IFPGA_RAWDEV_PMD_INFO("an error has occurred in pcie\n");
1308 else if (nonfaterr.portfatal_error)
1309 IFPGA_RAWDEV_PMD_INFO("fatal error occurred in AFU port.\n");
1310 else if (nonfaterr.proc_hot)
1311 IFPGA_RAWDEV_PMD_INFO("a ProcHot event\n");
1312 else if (nonfaterr.afu_acc_mode_err)
1313 IFPGA_RAWDEV_PMD_INFO("an AFU PF/VF access mismatch\n");
1314 else if (nonfaterr.injected_nonfata_err) {
1315 IFPGA_RAWDEV_PMD_INFO("Injected Warning Error\n");
1316 fme_clear_warning_intr(mgr);
1317 } else if (nonfaterr.temp_thresh_AP6)
1318 IFPGA_RAWDEV_PMD_INFO("Temperature threshold triggered AP6\n");
1319 else if (nonfaterr.power_thresh_AP1)
1320 IFPGA_RAWDEV_PMD_INFO("Power threshold triggered AP1\n");
1321 else if (nonfaterr.power_thresh_AP2)
1322 IFPGA_RAWDEV_PMD_INFO("Power threshold triggered AP2\n");
1323 else if (nonfaterr.mbp_err)
1324 IFPGA_RAWDEV_PMD_INFO("an MBP event\n");
1330 fme_interrupt_handler(void *param)
1332 struct opae_manager *mgr = (struct opae_manager *)param;
1334 IFPGA_RAWDEV_PMD_INFO("%s interrupt occurred\n", __func__);
1336 fme_err_handle_error0(mgr);
1337 fme_err_handle_nonfaterror(mgr);
1338 fme_err_handle_catfatal_error(mgr);
1342 ifpga_unregister_msix_irq(enum ifpga_irq_type type,
1343 int vec_start, rte_intr_callback_fn handler, void *arg)
1345 struct rte_intr_handle *intr_handle;
1347 if (type == IFPGA_FME_IRQ)
1348 intr_handle = &ifpga_irq_handle[0];
1349 else if (type == IFPGA_AFU_IRQ)
1350 intr_handle = &ifpga_irq_handle[vec_start + 1];
1354 rte_intr_efd_disable(intr_handle);
1356 return rte_intr_callback_unregister(intr_handle, handler, arg);
1360 ifpga_register_msix_irq(struct rte_rawdev *dev, int port_id,
1361 enum ifpga_irq_type type, int vec_start, int count,
1362 rte_intr_callback_fn handler, const char *name,
1366 struct rte_intr_handle *intr_handle;
1367 struct opae_adapter *adapter;
1368 struct opae_manager *mgr;
1369 struct opae_accelerator *acc;
1371 adapter = ifpga_rawdev_get_priv(dev);
1375 mgr = opae_adapter_get_mgr(adapter);
1379 if (type == IFPGA_FME_IRQ) {
1380 intr_handle = &ifpga_irq_handle[0];
1382 } else if (type == IFPGA_AFU_IRQ) {
1383 intr_handle = &ifpga_irq_handle[vec_start + 1];
1388 intr_handle->type = RTE_INTR_HANDLE_VFIO_MSIX;
1390 ret = rte_intr_efd_enable(intr_handle, count);
1394 intr_handle->fd = intr_handle->efds[0];
1396 IFPGA_RAWDEV_PMD_DEBUG("register %s irq, vfio_fd=%d, fd=%d\n",
1397 name, intr_handle->vfio_dev_fd,
1400 if (type == IFPGA_FME_IRQ) {
1401 struct fpga_fme_err_irq_set err_irq_set;
1402 err_irq_set.evtfd = intr_handle->efds[0];
1404 ret = opae_manager_ifpga_set_err_irq(mgr, &err_irq_set);
1407 } else if (type == IFPGA_AFU_IRQ) {
1408 acc = opae_adapter_get_acc(adapter, port_id);
1412 ret = opae_acc_set_irq(acc, vec_start, count,
1418 /* register interrupt handler using DPDK API */
1419 ret = rte_intr_callback_register(intr_handle,
1420 handler, (void *)arg);
1424 IFPGA_RAWDEV_PMD_INFO("success register %s interrupt\n", name);
1430 ifpga_rawdev_create(struct rte_pci_device *pci_dev,
1434 struct rte_rawdev *rawdev = NULL;
1435 struct ifpga_rawdev *dev = NULL;
1436 struct opae_adapter *adapter = NULL;
1437 struct opae_manager *mgr = NULL;
1438 struct opae_adapter_data_pci *data = NULL;
1439 char name[RTE_RAWDEV_NAME_MAX_LEN];
1443 IFPGA_RAWDEV_PMD_ERR("Invalid pci_dev of the device!");
1448 memset(name, 0, sizeof(name));
1449 snprintf(name, RTE_RAWDEV_NAME_MAX_LEN, "IFPGA:%02x:%02x.%x",
1450 pci_dev->addr.bus, pci_dev->addr.devid, pci_dev->addr.function);
1452 IFPGA_RAWDEV_PMD_INFO("Init %s on NUMA node %d", name, rte_socket_id());
1454 /* Allocate device structure */
1455 rawdev = rte_rawdev_pmd_allocate(name, sizeof(struct opae_adapter),
1457 if (rawdev == NULL) {
1458 IFPGA_RAWDEV_PMD_ERR("Unable to allocate rawdevice");
1463 ipn3ke_bridge_func.get_ifpga_rawdev = ifpga_rawdev_get;
1464 ipn3ke_bridge_func.set_i40e_sw_dev = rte_pmd_i40e_set_switch_dev;
1466 dev = ifpga_rawdev_allocate(rawdev);
1468 IFPGA_RAWDEV_PMD_ERR("Unable to allocate ifpga_rawdevice");
1472 dev->aer_enable = 0;
1474 /* alloc OPAE_FPGA_PCI data to register to OPAE hardware level API */
1475 data = opae_adapter_data_alloc(OPAE_FPGA_PCI);
1481 /* init opae_adapter_data_pci for device specific information */
1482 for (i = 0; i < PCI_MAX_RESOURCE; i++) {
1483 data->region[i].phys_addr = pci_dev->mem_resource[i].phys_addr;
1484 data->region[i].len = pci_dev->mem_resource[i].len;
1485 data->region[i].addr = pci_dev->mem_resource[i].addr;
1487 data->device_id = pci_dev->id.device_id;
1488 data->vendor_id = pci_dev->id.vendor_id;
1489 data->bus = pci_dev->addr.bus;
1490 data->devid = pci_dev->addr.devid;
1491 data->function = pci_dev->addr.function;
1492 data->vfio_dev_fd = pci_dev->intr_handle.vfio_dev_fd;
1494 adapter = rawdev->dev_private;
1495 /* create a opae_adapter based on above device data */
1496 ret = opae_adapter_init(adapter, pci_dev->device.name, data);
1499 goto free_adapter_data;
1502 rawdev->dev_ops = &ifpga_rawdev_ops;
1503 rawdev->device = &pci_dev->device;
1504 rawdev->driver_name = pci_dev->driver->driver.name;
1506 /* must enumerate the adapter before use it */
1507 ret = opae_adapter_enumerate(adapter);
1509 goto free_adapter_data;
1511 /* get opae_manager to rawdev */
1512 mgr = opae_adapter_get_mgr(adapter);
1515 IFPGA_RAWDEV_PMD_INFO("this is a PF function");
1518 ret = ifpga_register_msix_irq(rawdev, 0, IFPGA_FME_IRQ, 0, 0,
1519 fme_interrupt_handler, "fme_irq", mgr);
1521 goto free_adapter_data;
1527 opae_adapter_data_free(data);
1530 rte_rawdev_pmd_release(rawdev);
1536 ifpga_rawdev_destroy(struct rte_pci_device *pci_dev)
1539 struct rte_rawdev *rawdev;
1540 char name[RTE_RAWDEV_NAME_MAX_LEN];
1541 struct opae_adapter *adapter;
1542 struct opae_manager *mgr;
1543 struct ifpga_rawdev *dev;
1546 IFPGA_RAWDEV_PMD_ERR("Invalid pci_dev of the device!");
1551 memset(name, 0, sizeof(name));
1552 snprintf(name, RTE_RAWDEV_NAME_MAX_LEN, "IFPGA:%x:%02x.%x",
1553 pci_dev->addr.bus, pci_dev->addr.devid, pci_dev->addr.function);
1555 IFPGA_RAWDEV_PMD_INFO("Closing %s on NUMA node %d",
1556 name, rte_socket_id());
1558 rawdev = rte_rawdev_pmd_get_named_dev(name);
1560 IFPGA_RAWDEV_PMD_ERR("Invalid device name (%s)", name);
1563 dev = ifpga_rawdev_get(rawdev);
1567 adapter = ifpga_rawdev_get_priv(rawdev);
1571 mgr = opae_adapter_get_mgr(adapter);
1575 if (ifpga_unregister_msix_irq(IFPGA_FME_IRQ, 0,
1576 fme_interrupt_handler, mgr) < 0)
1579 /* rte_rawdev_close is called by pmd_release */
1580 ret = rte_rawdev_pmd_release(rawdev);
1582 IFPGA_RAWDEV_PMD_DEBUG("Device cleanup failed");
1588 ifpga_rawdev_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1589 struct rte_pci_device *pci_dev)
1591 IFPGA_RAWDEV_PMD_FUNC_TRACE();
1592 return ifpga_rawdev_create(pci_dev, rte_socket_id());
1596 ifpga_rawdev_pci_remove(struct rte_pci_device *pci_dev)
1598 ifpga_monitor_stop_func();
1599 return ifpga_rawdev_destroy(pci_dev);
1602 static struct rte_pci_driver rte_ifpga_rawdev_pmd = {
1603 .id_table = pci_ifpga_map,
1604 .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
1605 .probe = ifpga_rawdev_pci_probe,
1606 .remove = ifpga_rawdev_pci_remove,
1609 RTE_PMD_REGISTER_PCI(ifpga_rawdev_pci_driver, rte_ifpga_rawdev_pmd);
1610 RTE_PMD_REGISTER_PCI_TABLE(ifpga_rawdev_pci_driver, rte_ifpga_rawdev_pmd);
1611 RTE_PMD_REGISTER_KMOD_DEP(ifpga_rawdev_pci_driver, "* igb_uio | uio_pci_generic | vfio-pci");
1612 RTE_LOG_REGISTER(ifpga_rawdev_logtype, driver.raw.init, NOTICE);
1614 static const char * const valid_args[] = {
1615 #define IFPGA_ARG_NAME "ifpga"
1617 #define IFPGA_ARG_PORT "port"
1619 #define IFPGA_AFU_BTS "afu_bts"
1624 static int ifpga_rawdev_get_string_arg(const char *key __rte_unused,
1625 const char *value, void *extra_args)
1628 if (!value || !extra_args)
1631 size = strlen(value) + 1;
1632 *(char **)extra_args = rte_malloc(NULL, size, RTE_CACHE_LINE_SIZE);
1633 if (!*(char **)extra_args)
1636 strlcpy(*(char **)extra_args, value, size);
1641 ifpga_cfg_probe(struct rte_vdev_device *dev)
1643 struct rte_devargs *devargs;
1644 struct rte_kvargs *kvlist = NULL;
1645 struct rte_rawdev *rawdev = NULL;
1646 struct ifpga_rawdev *ifpga_dev;
1650 char dev_name[RTE_RAWDEV_NAME_MAX_LEN];
1653 devargs = dev->device.devargs;
1655 kvlist = rte_kvargs_parse(devargs->args, valid_args);
1657 IFPGA_RAWDEV_PMD_LOG(ERR, "error when parsing param");
1661 if (rte_kvargs_count(kvlist, IFPGA_ARG_NAME) == 1) {
1662 if (rte_kvargs_process(kvlist, IFPGA_ARG_NAME,
1663 &ifpga_rawdev_get_string_arg,
1665 IFPGA_RAWDEV_PMD_ERR("error to parse %s",
1670 IFPGA_RAWDEV_PMD_ERR("arg %s is mandatory for ifpga bus",
1675 if (rte_kvargs_count(kvlist, IFPGA_ARG_PORT) == 1) {
1676 if (rte_kvargs_process(kvlist,
1678 &rte_ifpga_get_integer32_arg,
1680 IFPGA_RAWDEV_PMD_ERR("error to parse %s",
1685 IFPGA_RAWDEV_PMD_ERR("arg %s is mandatory for ifpga bus",
1690 memset(dev_name, 0, sizeof(dev_name));
1691 snprintf(dev_name, RTE_RAWDEV_NAME_MAX_LEN, "IFPGA:%s", name);
1692 rawdev = rte_rawdev_pmd_get_named_dev(dev_name);
1695 ifpga_dev = ifpga_rawdev_get(rawdev);
1699 ifpga_rawdev_fill_info(ifpga_dev, bdf);
1701 ifpga_monitor_start_func();
1703 memset(dev_name, 0, sizeof(dev_name));
1704 snprintf(dev_name, RTE_RAWDEV_NAME_MAX_LEN, "%d|%s",
1707 ret = rte_eal_hotplug_add(RTE_STR(IFPGA_BUS_NAME),
1708 dev_name, devargs->args);
1711 rte_kvargs_free(kvlist);
1719 ifpga_cfg_remove(struct rte_vdev_device *vdev)
1721 IFPGA_RAWDEV_PMD_INFO("Remove ifpga_cfg %p",
1727 static struct rte_vdev_driver ifpga_cfg_driver = {
1728 .probe = ifpga_cfg_probe,
1729 .remove = ifpga_cfg_remove,
1732 RTE_PMD_REGISTER_VDEV(ifpga_rawdev_cfg, ifpga_cfg_driver);
1733 RTE_PMD_REGISTER_ALIAS(ifpga_rawdev_cfg, ifpga_cfg);
1734 RTE_PMD_REGISTER_PARAM_STRING(ifpga_rawdev_cfg,