drivers/raw/ifpga/ifpga_rawdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2010-2018 Intel Corporation
   3  */
   4
   5 #include <string.h>
   6 #include <dirent.h>
   7 #include <sys/stat.h>
   8 #include <unistd.h>
   9 #include <sys/types.h>
  10 #include <fcntl.h>
  11 #include <sys/ioctl.h>
  12 #include <sys/epoll.h>
  13 #include <rte_log.h>
  14 #include <rte_bus.h>
  15 #include <rte_malloc.h>
  16 #include <rte_devargs.h>
  17 #include <rte_memcpy.h>
  18 #include <rte_pci.h>
  19 #include <rte_bus_pci.h>
  20 #include <rte_kvargs.h>
  21 #include <rte_alarm.h>
  22 #include <rte_interrupts.h>
  23 #include <rte_errno.h>
  24 #include <rte_per_lcore.h>
  25 #include <rte_memory.h>
  26 #include <rte_memzone.h>
  27 #include <rte_eal.h>
  28 #include <rte_common.h>
  29 #include <rte_bus_vdev.h>
  30 #include <rte_string_fns.h>
  31 #include <rte_pmd_i40e.h>
  32
  33 #include "base/opae_hw_api.h"
  34 #include "base/opae_ifpga_hw_api.h"
  35 #include "base/ifpga_api.h"
  36 #include "rte_rawdev.h"
  37 #include "rte_rawdev_pmd.h"
  38 #include "rte_bus_ifpga.h"
  39 #include "ifpga_common.h"
  40 #include "ifpga_logs.h"
  41 #include "ifpga_rawdev.h"
  42 #include "ipn3ke_rawdev_api.h"
  43
  44 #define RTE_PCI_EXT_CAP_ID_ERR           0x01   /* Advanced Error Reporting */
  45 #define RTE_PCI_CFG_SPACE_SIZE           256
  46 #define RTE_PCI_CFG_SPACE_EXP_SIZE       4096
  47 #define RTE_PCI_EXT_CAP_ID(header)       (int)(header & 0x0000ffff)
  48 #define RTE_PCI_EXT_CAP_NEXT(header)     ((header >> 20) & 0xffc)
  49
  50 #define PCI_VENDOR_ID_INTEL          0x8086
  51 /* PCI Device ID */
  52 #define PCIE_DEVICE_ID_PF_INT_5_X    0xBCBD
  53 #define PCIE_DEVICE_ID_PF_INT_6_X    0xBCC0
  54 #define PCIE_DEVICE_ID_PF_DSC_1_X    0x09C4
  55 #define PCIE_DEVICE_ID_PAC_N3000     0x0B30
  56 /* VF Device */
  57 #define PCIE_DEVICE_ID_VF_INT_5_X    0xBCBF
  58 #define PCIE_DEVICE_ID_VF_INT_6_X    0xBCC1
  59 #define PCIE_DEVICE_ID_VF_DSC_1_X    0x09C5
  60 #define PCIE_DEVICE_ID_VF_PAC_N3000  0x0B31
  61 #define RTE_MAX_RAW_DEVICE           10
  62
  63 static const struct rte_pci_id pci_ifpga_map[] = {
  64         { RTE_PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_PF_INT_5_X) },
  65         { RTE_PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_VF_INT_5_X) },
  66         { RTE_PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_PF_INT_6_X) },
  67         { RTE_PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_VF_INT_6_X) },
  68         { RTE_PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_PF_DSC_1_X) },
  69         { RTE_PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_VF_DSC_1_X) },
  70         { RTE_PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_PAC_N3000),},
  71         { RTE_PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_VF_PAC_N3000),},
  72         { .vendor_id = 0, /* sentinel */ },
  73 };
  74
  75 static struct ifpga_rawdev ifpga_rawdevices[IFPGA_RAWDEV_NUM];
  76
  77 static int ifpga_monitor_start;
  78 static pthread_t ifpga_monitor_start_thread;
  79
  80 #define IFPGA_MAX_IRQ 12
  81 /* 0 for FME interrupt, others are reserved for AFU irq */
  82 static struct rte_intr_handle ifpga_irq_handle[IFPGA_MAX_IRQ];
  83
  84 static struct ifpga_rawdev *
  85 ifpga_rawdev_allocate(struct rte_rawdev *rawdev);
  86 static int set_surprise_link_check_aer(
  87                 struct ifpga_rawdev *ifpga_rdev, int force_disable);
  88 static int ifpga_pci_find_next_ext_capability(unsigned int fd,
  89                 int start, int cap);
  90 static int ifpga_pci_find_ext_capability(unsigned int fd, int cap);
  91
  92 struct ifpga_rawdev *
  93 ifpga_rawdev_get(const struct rte_rawdev *rawdev)
  94 {
  95         struct ifpga_rawdev *dev;
  96         unsigned int i;
  97
  98         if (rawdev == NULL)
  99                 return NULL;
 100
 101         for (i = 0; i < IFPGA_RAWDEV_NUM; i++) {
 102                 dev = &ifpga_rawdevices[i];
 103                 if (dev->rawdev == rawdev)
 104                         return dev;
 105         }
 106
 107         return NULL;
 108 }
 109
 110 static inline uint8_t
 111 ifpga_rawdev_find_free_device_index(void)
 112 {
 113         uint16_t dev_id;
 114
 115         for (dev_id = 0; dev_id < IFPGA_RAWDEV_NUM; dev_id++) {
 116                 if (ifpga_rawdevices[dev_id].rawdev == NULL)
 117                         return dev_id;
 118         }
 119
 120         return IFPGA_RAWDEV_NUM;
 121 }
 122 static struct ifpga_rawdev *
 123 ifpga_rawdev_allocate(struct rte_rawdev *rawdev)
 124 {
 125         struct ifpga_rawdev *dev;
 126         uint16_t dev_id;
 127
 128         dev = ifpga_rawdev_get(rawdev);
 129         if (dev != NULL) {
 130                 IFPGA_RAWDEV_PMD_ERR("Event device already allocated!");
 131                 return NULL;
 132         }
 133
 134         dev_id = ifpga_rawdev_find_free_device_index();
 135         if (dev_id == IFPGA_RAWDEV_NUM) {
 136                 IFPGA_RAWDEV_PMD_ERR("Reached maximum number of raw devices");
 137                 return NULL;
 138         }
 139
 140         dev = &ifpga_rawdevices[dev_id];
 141         dev->rawdev = rawdev;
 142         dev->dev_id = dev_id;
 143
 144         return dev;
 145 }
 146
 147 static int ifpga_pci_find_next_ext_capability(unsigned int fd,
 148 int start, int cap)
 149 {
 150         uint32_t header;
 151         int ttl;
 152         int pos = RTE_PCI_CFG_SPACE_SIZE;
 153         int ret;
 154
 155         /* minimum 8 bytes per capability */
 156         ttl = (RTE_PCI_CFG_SPACE_EXP_SIZE - RTE_PCI_CFG_SPACE_SIZE) / 8;
 157
 158         if (start)
 159                 pos = start;
 160         ret = pread(fd, &header, sizeof(header), pos);
 161         if (ret == -1)
 162                 return -1;
 163
 164         /*
 165          * If we have no capabilities, this is indicated by cap ID,
 166          * cap version and next pointer all being 0.
 167          */
 168         if (header == 0)
 169                 return 0;
 170
 171         while (ttl-- > 0) {
 172                 if (RTE_PCI_EXT_CAP_ID(header) == cap && pos != start)
 173                         return pos;
 174
 175                 pos = RTE_PCI_EXT_CAP_NEXT(header);
 176                 if (pos < RTE_PCI_CFG_SPACE_SIZE)
 177                         break;
 178                 ret = pread(fd, &header, sizeof(header), pos);
 179                 if (ret == -1)
 180                         return -1;
 181         }
 182
 183         return 0;
 184 }
 185
 186 static int ifpga_pci_find_ext_capability(unsigned int fd, int cap)
 187 {
 188         return ifpga_pci_find_next_ext_capability(fd, 0, cap);
 189 }
 190
 191 static int ifpga_get_dev_vendor_id(const char *bdf,
 192         uint32_t *dev_id, uint32_t *vendor_id)
 193 {
 194         int fd;
 195         char path[1024];
 196         int ret;
 197         uint32_t header;
 198
 199         strlcpy(path, "/sys/bus/pci/devices/", sizeof(path));
 200         strlcat(path, bdf, sizeof(path));
 201         strlcat(path, "/config", sizeof(path));
 202         fd = open(path, O_RDWR);
 203         if (fd < 0)
 204                 return -1;
 205         ret = pread(fd, &header, sizeof(header), 0);
 206         if (ret == -1) {
 207                 close(fd);
 208                 return -1;
 209         }
 210         (*vendor_id) = header & 0xffff;
 211         (*dev_id) = (header >> 16) & 0xffff;
 212         close(fd);
 213
 214         return 0;
 215 }
 216 static int ifpga_rawdev_fill_info(struct ifpga_rawdev *ifpga_dev,
 217         const char *bdf)
 218 {
 219         char path[1024] = "/sys/bus/pci/devices/0000:";
 220         char link[1024], link1[1024];
 221         char dir[1024] = "/sys/devices/";
 222         char *c;
 223         int ret;
 224         char sub_brg_bdf[4][16];
 225         int point;
 226         DIR *dp = NULL;
 227         struct dirent *entry;
 228         int i, j;
 229
 230         unsigned int dom, bus, dev;
 231         int func;
 232         uint32_t dev_id, vendor_id;
 233
 234         strlcat(path, bdf, sizeof(path));
 235         memset(link, 0, sizeof(link));
 236         memset(link1, 0, sizeof(link1));
 237         ret = readlink(path, link, (sizeof(link)-1));
 238         if (ret == -1)
 239                 return -1;
 240         strlcpy(link1, link, sizeof(link1));
 241         memset(ifpga_dev->parent_bdf, 0, 16);
 242         point = strlen(link);
 243         if (point < 39)
 244                 return -1;
 245         point -= 39;
 246         link[point] = 0;
 247         if (point < 12)
 248                 return -1;
 249         point -= 12;
 250         rte_memcpy(ifpga_dev->parent_bdf, &link[point], 12);
 251
 252         point = strlen(link1);
 253         if (point < 26)
 254                 return -1;
 255         point -= 26;
 256         link1[point] = 0;
 257         if (point < 12)
 258                 return -1;
 259         point -= 12;
 260         c = strchr(link1, 'p');
 261         if (!c)
 262                 return -1;
 263         strlcat(dir, c, sizeof(dir));
 264
 265         /* scan folder */
 266         dp = opendir(dir);
 267         if (dp == NULL)
 268                 return -1;
 269         i = 0;
 270         while ((entry = readdir(dp)) != NULL) {
 271                 if (i >= 4)
 272                         break;
 273                 if (entry->d_name[0] == '.')
 274                         continue;
 275                 if (strlen(entry->d_name) > 12)
 276                         continue;
 277                 if (sscanf(entry->d_name, "%x:%x:%x.%d",
 278                         &dom, &bus, &dev, &func) < 4)
 279                         continue;
 280                 else {
 281                         strlcpy(sub_brg_bdf[i],
 282                                 entry->d_name,
 283                                 sizeof(sub_brg_bdf[i]));
 284                         i++;
 285                 }
 286         }
 287         closedir(dp);
 288
 289         /* get fpga and fvl */
 290         j = 0;
 291         for (i = 0; i < 4; i++) {
 292                 strlcpy(link, dir, sizeof(link));
 293                 strlcat(link, "/", sizeof(link));
 294                 strlcat(link, sub_brg_bdf[i], sizeof(link));
 295                 dp = opendir(link);
 296                 if (dp == NULL)
 297                         return -1;
 298                 while ((entry = readdir(dp)) != NULL) {
 299                         if (j >= 8)
 300                                 break;
 301                         if (entry->d_name[0] == '.')
 302                                 continue;
 303
 304                         if (strlen(entry->d_name) > 12)
 305                                 continue;
 306                         if (sscanf(entry->d_name, "%x:%x:%x.%d",
 307                                 &dom, &bus, &dev, &func) < 4)
 308                                 continue;
 309                         else {
 310                                 if (ifpga_get_dev_vendor_id(entry->d_name,
 311                                         &dev_id, &vendor_id))
 312                                         continue;
 313                                 if (vendor_id == 0x8086 &&
 314                                         (dev_id == 0x0CF8 ||
 315                                         dev_id == 0x0D58 ||
 316                                         dev_id == 0x1580)) {
 317                                         strlcpy(ifpga_dev->fvl_bdf[j],
 318                                                 entry->d_name,
 319                                                 sizeof(ifpga_dev->fvl_bdf[j]));
 320                                         j++;
 321                                 }
 322                         }
 323                 }
 324                 closedir(dp);
 325         }
 326
 327         return 0;
 328 }
 329
 330 #define HIGH_FATAL(_sens, value)\
 331         (((_sens)->flags & OPAE_SENSOR_HIGH_FATAL_VALID) &&\
 332          (value > (_sens)->high_fatal))
 333
 334 #define HIGH_WARN(_sens, value)\
 335         (((_sens)->flags & OPAE_SENSOR_HIGH_WARN_VALID) &&\
 336          (value > (_sens)->high_warn))
 337
 338 #define LOW_FATAL(_sens, value)\
 339         (((_sens)->flags & OPAE_SENSOR_LOW_FATAL_VALID) &&\
 340          (value > (_sens)->low_fatal))
 341
 342 #define LOW_WARN(_sens, value)\
 343         (((_sens)->flags & OPAE_SENSOR_LOW_WARN_VALID) &&\
 344          (value > (_sens)->low_warn))
 345
 346 #define AUX_VOLTAGE_WARN 11400
 347
 348 static int
 349 ifpga_monitor_sensor(struct rte_rawdev *raw_dev,
 350                bool *gsd_start)
 351 {
 352         struct opae_adapter *adapter;
 353         struct opae_manager *mgr;
 354         struct opae_sensor_info *sensor;
 355         unsigned int value;
 356         int ret;
 357
 358         adapter = ifpga_rawdev_get_priv(raw_dev);
 359         if (!adapter)
 360                 return -ENODEV;
 361
 362         mgr = opae_adapter_get_mgr(adapter);
 363         if (!mgr)
 364                 return -ENODEV;
 365
 366         opae_mgr_for_each_sensor(mgr, sensor) {
 367                 if (!(sensor->flags & OPAE_SENSOR_VALID))
 368                         goto fail;
 369
 370                 ret = opae_mgr_get_sensor_value(mgr, sensor, &value);
 371                 if (ret)
 372                         goto fail;
 373
 374                 if (value == 0xdeadbeef) {
 375                         IFPGA_RAWDEV_PMD_ERR("dev_id %d sensor %s value %x\n",
 376                                         raw_dev->dev_id, sensor->name, value);
 377                         continue;
 378                 }
 379
 380                 /* monitor temperature sensors */
 381                 if (!strcmp(sensor->name, "Board Temperature") ||
 382                                 !strcmp(sensor->name, "FPGA Die Temperature")) {
 383                         IFPGA_RAWDEV_PMD_INFO("read sensor %s %d %d %d\n",
 384                                         sensor->name, value, sensor->high_warn,
 385                                         sensor->high_fatal);
 386
 387                         if (HIGH_WARN(sensor, value) ||
 388                                 LOW_WARN(sensor, value)) {
 389                                 IFPGA_RAWDEV_PMD_INFO("%s reach theshold %d\n",
 390                                         sensor->name, value);
 391                                 *gsd_start = true;
 392                                 break;
 393                         }
 394                 }
 395
 396                 /* monitor 12V AUX sensor */
 397                 if (!strcmp(sensor->name, "12V AUX Voltage")) {
 398                         if (value < AUX_VOLTAGE_WARN) {
 399                                 IFPGA_RAWDEV_PMD_INFO(
 400                                         "%s reach theshold %d mV\n",
 401                                         sensor->name, value);
 402                                 *gsd_start = true;
 403                                 break;
 404                         }
 405                 }
 406         }
 407
 408         return 0;
 409 fail:
 410         return -EFAULT;
 411 }
 412
 413 static int set_surprise_link_check_aer(
 414         struct ifpga_rawdev *ifpga_rdev, int force_disable)
 415 {
 416         struct rte_rawdev *rdev;
 417         int fd = -1;
 418         char path[1024];
 419         int pos;
 420         int ret;
 421         uint32_t data;
 422         bool enable = 0;
 423         uint32_t aer_new0, aer_new1;
 424
 425         if (!ifpga_rdev) {
 426                 printf("\n device does not exist\n");
 427                 return -EFAULT;
 428         }
 429
 430         rdev = ifpga_rdev->rawdev;
 431         if (ifpga_rdev->aer_enable)
 432                 return -EFAULT;
 433         if (ifpga_monitor_sensor(rdev, &enable))
 434                 return -EFAULT;
 435         if (enable || force_disable) {
 436                 IFPGA_RAWDEV_PMD_ERR("Set AER, pls graceful shutdown\n");
 437                 ifpga_rdev->aer_enable = 1;
 438                 /* get bridge fd */
 439                 strlcpy(path, "/sys/bus/pci/devices/", sizeof(path));
 440                 strlcat(path, ifpga_rdev->parent_bdf, sizeof(path));
 441                 strlcat(path, "/config", sizeof(path));
 442                 fd = open(path, O_RDWR);
 443                 if (fd < 0)
 444                         goto end;
 445                 pos = ifpga_pci_find_ext_capability(fd, RTE_PCI_EXT_CAP_ID_ERR);
 446                 if (!pos)
 447                         goto end;
 448                 /* save previout ECAP_AER+0x08 */
 449                 ret = pread(fd, &data, sizeof(data), pos+0x08);
 450                 if (ret == -1)
 451                         goto end;
 452                 ifpga_rdev->aer_old[0] = data;
 453                 /* save previout ECAP_AER+0x14 */
 454                 ret = pread(fd, &data, sizeof(data), pos+0x14);
 455                 if (ret == -1)
 456                         goto end;
 457                 ifpga_rdev->aer_old[1] = data;
 458
 459                 /* set ECAP_AER+0x08 to 0xFFFFFFFF */
 460                 data = 0xffffffff;
 461                 ret = pwrite(fd, &data, 4, pos+0x08);
 462                 if (ret == -1)
 463                         goto end;
 464                 /* set ECAP_AER+0x14 to 0xFFFFFFFF */
 465                 ret = pwrite(fd, &data, 4, pos+0x14);
 466                 if (ret == -1)
 467                         goto end;
 468
 469                 /* read current ECAP_AER+0x08 */
 470                 ret = pread(fd, &data, sizeof(data), pos+0x08);
 471                 if (ret == -1)
 472                         goto end;
 473                 aer_new0 = data;
 474                 /* read current ECAP_AER+0x14 */
 475                 ret = pread(fd, &data, sizeof(data), pos+0x14);
 476                 if (ret == -1)
 477                         goto end;
 478                 aer_new1 = data;
 479
 480                 if (fd != -1)
 481                         close(fd);
 482
 483                 printf(">>>>>>Set AER %x,%x %x,%x\n",
 484                         ifpga_rdev->aer_old[0], ifpga_rdev->aer_old[1],
 485                         aer_new0, aer_new1);
 486
 487                 return 1;
 488                 }
 489
 490 end:
 491         if (fd != -1)
 492                 close(fd);
 493         return -EFAULT;
 494 }
 495
 496 static void *
 497 ifpga_rawdev_gsd_handle(__rte_unused void *param)
 498 {
 499         struct ifpga_rawdev *ifpga_rdev;
 500         int i;
 501         int gsd_enable, ret;
 502 #define MS 1000
 503
 504         while (1) {
 505                 gsd_enable = 0;
 506                 for (i = 0; i < IFPGA_RAWDEV_NUM; i++) {
 507                         ifpga_rdev = &ifpga_rawdevices[i];
 508                         if (ifpga_rdev->rawdev) {
 509                                 ret = set_surprise_link_check_aer(ifpga_rdev,
 510                                         gsd_enable);
 511                                 if (ret == 1 && !gsd_enable) {
 512                                         gsd_enable = 1;
 513                                         i = -1;
 514                                 }
 515                         }
 516                 }
 517
 518                 if (gsd_enable)
 519                         printf(">>>>>>Pls Shutdown APP\n");
 520
 521                 rte_delay_us(100 * MS);
 522         }
 523
 524         return NULL;
 525 }
 526
 527 static int
 528 ifpga_monitor_start_func(void)
 529 {
 530         int ret;
 531
 532         if (ifpga_monitor_start == 0) {
 533                 ret = pthread_create(&ifpga_monitor_start_thread,
 534                         NULL,
 535                         ifpga_rawdev_gsd_handle, NULL);
 536                 if (ret) {
 537                         IFPGA_RAWDEV_PMD_ERR(
 538                                 "Fail to create ifpga nonitor thread");
 539                         return -1;
 540                 }
 541                 ifpga_monitor_start = 1;
 542         }
 543
 544         return 0;
 545 }
 546 static int
 547 ifpga_monitor_stop_func(void)
 548 {
 549         int ret;
 550
 551         if (ifpga_monitor_start == 1) {
 552                 ret = pthread_cancel(ifpga_monitor_start_thread);
 553                 if (ret)
 554                         IFPGA_RAWDEV_PMD_ERR("Can't cancel the thread");
 555
 556                 ret = pthread_join(ifpga_monitor_start_thread, NULL);
 557                 if (ret)
 558                         IFPGA_RAWDEV_PMD_ERR("Can't join the thread");
 559
 560                 ifpga_monitor_start = 0;
 561
 562                 return ret;
 563         }
 564
 565         return 0;
 566 }
 567
 568 static int
 569 ifpga_fill_afu_dev(struct opae_accelerator *acc,
 570                 struct rte_afu_device *afu_dev)
 571 {
 572         struct rte_mem_resource *res = afu_dev->mem_resource;
 573         struct opae_acc_region_info region_info;
 574         struct opae_acc_info info;
 575         unsigned long i;
 576         int ret;
 577
 578         ret = opae_acc_get_info(acc, &info);
 579         if (ret)
 580                 return ret;
 581
 582         if (info.num_regions > PCI_MAX_RESOURCE)
 583                 return -EFAULT;
 584
 585         afu_dev->num_region = info.num_regions;
 586
 587         for (i = 0; i < info.num_regions; i++) {
 588                 region_info.index = i;
 589                 ret = opae_acc_get_region_info(acc, &region_info);
 590                 if (ret)
 591                         return ret;
 592
 593                 if ((region_info.flags & ACC_REGION_MMIO) &&
 594                     (region_info.flags & ACC_REGION_READ) &&
 595                     (region_info.flags & ACC_REGION_WRITE)) {
 596                         res[i].phys_addr = region_info.phys_addr;
 597                         res[i].len = region_info.len;
 598                         res[i].addr = region_info.addr;
 599                 } else
 600                         return -EFAULT;
 601         }
 602
 603         return 0;
 604 }
 605
 606 static void
 607 ifpga_rawdev_info_get(struct rte_rawdev *dev,
 608                       rte_rawdev_obj_t dev_info,
 609                       size_t dev_info_size)
 610 {
 611         struct opae_adapter *adapter;
 612         struct opae_accelerator *acc;
 613         struct rte_afu_device *afu_dev;
 614         struct opae_manager *mgr = NULL;
 615         struct opae_eth_group_region_info opae_lside_eth_info;
 616         struct opae_eth_group_region_info opae_nside_eth_info;
 617         int lside_bar_idx, nside_bar_idx;
 618
 619         IFPGA_RAWDEV_PMD_FUNC_TRACE();
 620
 621         if (!dev_info || dev_info_size != sizeof(*afu_dev)) {
 622                 IFPGA_RAWDEV_PMD_ERR("Invalid request");
 623                 return;
 624         }
 625
 626         adapter = ifpga_rawdev_get_priv(dev);
 627         if (!adapter)
 628                 return;
 629
 630         afu_dev = dev_info;
 631         afu_dev->rawdev = dev;
 632
 633         /* find opae_accelerator and fill info into afu_device */
 634         opae_adapter_for_each_acc(adapter, acc) {
 635                 if (acc->index != afu_dev->id.port)
 636                         continue;
 637
 638                 if (ifpga_fill_afu_dev(acc, afu_dev)) {
 639                         IFPGA_RAWDEV_PMD_ERR("cannot get info\n");
 640                         return;
 641                 }
 642         }
 643
 644         /* get opae_manager to rawdev */
 645         mgr = opae_adapter_get_mgr(adapter);
 646         if (mgr) {
 647                 /* get LineSide BAR Index */
 648                 if (opae_manager_get_eth_group_region_info(mgr, 0,
 649                         &opae_lside_eth_info)) {
 650                         return;
 651                 }
 652                 lside_bar_idx = opae_lside_eth_info.mem_idx;
 653
 654                 /* get NICSide BAR Index */
 655                 if (opae_manager_get_eth_group_region_info(mgr, 1,
 656                         &opae_nside_eth_info)) {
 657                         return;
 658                 }
 659                 nside_bar_idx = opae_nside_eth_info.mem_idx;
 660
 661                 if (lside_bar_idx >= PCI_MAX_RESOURCE ||
 662                         nside_bar_idx >= PCI_MAX_RESOURCE ||
 663                         lside_bar_idx == nside_bar_idx)
 664                         return;
 665
 666                 /* fill LineSide BAR Index */
 667                 afu_dev->mem_resource[lside_bar_idx].phys_addr =
 668                         opae_lside_eth_info.phys_addr;
 669                 afu_dev->mem_resource[lside_bar_idx].len =
 670                         opae_lside_eth_info.len;
 671                 afu_dev->mem_resource[lside_bar_idx].addr =
 672                         opae_lside_eth_info.addr;
 673
 674                 /* fill NICSide BAR Index */
 675                 afu_dev->mem_resource[nside_bar_idx].phys_addr =
 676                         opae_nside_eth_info.phys_addr;
 677                 afu_dev->mem_resource[nside_bar_idx].len =
 678                         opae_nside_eth_info.len;
 679                 afu_dev->mem_resource[nside_bar_idx].addr =
 680                         opae_nside_eth_info.addr;
 681         }
 682 }
 683
 684 static int
 685 ifpga_rawdev_configure(const struct rte_rawdev *dev,
 686                 rte_rawdev_obj_t config)
 687 {
 688         IFPGA_RAWDEV_PMD_FUNC_TRACE();
 689
 690         RTE_FUNC_PTR_OR_ERR_RET(dev, -EINVAL);
 691
 692         return config ? 0 : 1;
 693 }
 694
 695 static int
 696 ifpga_rawdev_start(struct rte_rawdev *dev)
 697 {
 698         int ret = 0;
 699         struct opae_adapter *adapter;
 700
 701         IFPGA_RAWDEV_PMD_FUNC_TRACE();
 702
 703         RTE_FUNC_PTR_OR_ERR_RET(dev, -EINVAL);
 704
 705         adapter = ifpga_rawdev_get_priv(dev);
 706         if (!adapter)
 707                 return -ENODEV;
 708
 709         return ret;
 710 }
 711
 712 static void
 713 ifpga_rawdev_stop(struct rte_rawdev *dev)
 714 {
 715         dev->started = 0;
 716 }
 717
 718 static int
 719 ifpga_rawdev_close(struct rte_rawdev *dev)
 720 {
 721         return dev ? 0:1;
 722 }
 723
 724 static int
 725 ifpga_rawdev_reset(struct rte_rawdev *dev)
 726 {
 727         return dev ? 0:1;
 728 }
 729
 730 static int
 731 fpga_pr(struct rte_rawdev *raw_dev, u32 port_id, const char *buffer, u32 size,
 732                         u64 *status)
 733 {
 734
 735         struct opae_adapter *adapter;
 736         struct opae_manager *mgr;
 737         struct opae_accelerator *acc;
 738         struct opae_bridge *br;
 739         int ret;
 740
 741         adapter = ifpga_rawdev_get_priv(raw_dev);
 742         if (!adapter)
 743                 return -ENODEV;
 744
 745         mgr = opae_adapter_get_mgr(adapter);
 746         if (!mgr)
 747                 return -ENODEV;
 748
 749         acc = opae_adapter_get_acc(adapter, port_id);
 750         if (!acc)
 751                 return -ENODEV;
 752
 753         br = opae_acc_get_br(acc);
 754         if (!br)
 755                 return -ENODEV;
 756
 757         ret = opae_manager_flash(mgr, port_id, buffer, size, status);
 758         if (ret) {
 759                 IFPGA_RAWDEV_PMD_ERR("%s pr error %d\n", __func__, ret);
 760                 return ret;
 761         }
 762
 763         ret = opae_bridge_reset(br);
 764         if (ret) {
 765                 IFPGA_RAWDEV_PMD_ERR("%s reset port:%d error %d\n",
 766                                 __func__, port_id, ret);
 767                 return ret;
 768         }
 769
 770         return ret;
 771 }
 772
 773 static int
 774 rte_fpga_do_pr(struct rte_rawdev *rawdev, int port_id,
 775                 const char *file_name)
 776 {
 777         struct stat file_stat;
 778         int file_fd;
 779         int ret = 0;
 780         ssize_t buffer_size;
 781         void *buffer;
 782         u64 pr_error;
 783
 784         if (!file_name)
 785                 return -EINVAL;
 786
 787         file_fd = open(file_name, O_RDONLY);
 788         if (file_fd < 0) {
 789                 IFPGA_RAWDEV_PMD_ERR("%s: open file error: %s\n",
 790                                 __func__, file_name);
 791                 IFPGA_RAWDEV_PMD_ERR("Message : %s\n", strerror(errno));
 792                 return -EINVAL;
 793         }
 794         ret = stat(file_name, &file_stat);
 795         if (ret) {
 796                 IFPGA_RAWDEV_PMD_ERR("stat on bitstream file failed: %s\n",
 797                                 file_name);
 798                 ret = -EINVAL;
 799                 goto close_fd;
 800         }
 801         buffer_size = file_stat.st_size;
 802         if (buffer_size <= 0) {
 803                 ret = -EINVAL;
 804                 goto close_fd;
 805         }
 806
 807         IFPGA_RAWDEV_PMD_INFO("bitstream file size: %zu\n", buffer_size);
 808         buffer = rte_malloc(NULL, buffer_size, 0);
 809         if (!buffer) {
 810                 ret = -ENOMEM;
 811                 goto close_fd;
 812         }
 813
 814         /*read the raw data*/
 815         if (buffer_size != read(file_fd, (void *)buffer, buffer_size)) {
 816                 ret = -EINVAL;
 817                 goto free_buffer;
 818         }
 819
 820         /*do PR now*/
 821         ret = fpga_pr(rawdev, port_id, buffer, buffer_size, &pr_error);
 822         IFPGA_RAWDEV_PMD_INFO("downloading to device port %d....%s.\n", port_id,
 823                 ret ? "failed" : "success");
 824         if (ret) {
 825                 ret = -EINVAL;
 826                 goto free_buffer;
 827         }
 828
 829 free_buffer:
 830         if (buffer)
 831                 rte_free(buffer);
 832 close_fd:
 833         close(file_fd);
 834         file_fd = 0;
 835         return ret;
 836 }
 837
 838 static int
 839 ifpga_rawdev_pr(struct rte_rawdev *dev,
 840         rte_rawdev_obj_t pr_conf)
 841 {
 842         struct opae_adapter *adapter;
 843         struct opae_manager *mgr;
 844         struct opae_board_info *info;
 845         struct rte_afu_pr_conf *afu_pr_conf;
 846         int ret;
 847         struct uuid uuid;
 848         struct opae_accelerator *acc;
 849
 850         IFPGA_RAWDEV_PMD_FUNC_TRACE();
 851
 852         adapter = ifpga_rawdev_get_priv(dev);
 853         if (!adapter)
 854                 return -ENODEV;
 855
 856         if (!pr_conf)
 857                 return -EINVAL;
 858
 859         afu_pr_conf = pr_conf;
 860
 861         if (afu_pr_conf->pr_enable) {
 862                 ret = rte_fpga_do_pr(dev,
 863                                 afu_pr_conf->afu_id.port,
 864                                 afu_pr_conf->bs_path);
 865                 if (ret) {
 866                         IFPGA_RAWDEV_PMD_ERR("do pr error %d\n", ret);
 867                         return ret;
 868                 }
 869         }
 870
 871         mgr = opae_adapter_get_mgr(adapter);
 872         if (!mgr) {
 873                 IFPGA_RAWDEV_PMD_ERR("opae_manager of opae_adapter is NULL");
 874                 return -1;
 875         }
 876
 877         if (ifpga_mgr_ops.get_board_info(mgr, &info)) {
 878                 IFPGA_RAWDEV_PMD_ERR("ifpga manager get_board_info fail!");
 879                 return -1;
 880         }
 881
 882         if (info->lightweight) {
 883                 /* set uuid to all 0, when fpga is lightweight image */
 884                 memset(&afu_pr_conf->afu_id.uuid.uuid_low, 0, sizeof(u64));
 885                 memset(&afu_pr_conf->afu_id.uuid.uuid_high, 0, sizeof(u64));
 886         } else {
 887                 acc = opae_adapter_get_acc(adapter, afu_pr_conf->afu_id.port);
 888                 if (!acc)
 889                         return -ENODEV;
 890
 891                 ret = opae_acc_get_uuid(acc, &uuid);
 892                 if (ret)
 893                         return ret;
 894
 895                 rte_memcpy(&afu_pr_conf->afu_id.uuid.uuid_low, uuid.b,
 896                         sizeof(u64));
 897                 rte_memcpy(&afu_pr_conf->afu_id.uuid.uuid_high, uuid.b + 8,
 898                         sizeof(u64));
 899
 900                 IFPGA_RAWDEV_PMD_INFO("%s: uuid_l=0x%lx, uuid_h=0x%lx\n",
 901                         __func__,
 902                         (unsigned long)afu_pr_conf->afu_id.uuid.uuid_low,
 903                         (unsigned long)afu_pr_conf->afu_id.uuid.uuid_high);
 904                 }
 905         return 0;
 906 }
 907
 908 static int
 909 ifpga_rawdev_get_attr(struct rte_rawdev *dev,
 910         const char *attr_name, uint64_t *attr_value)
 911 {
 912         struct opae_adapter *adapter;
 913         struct opae_manager *mgr;
 914         struct opae_retimer_info opae_rtm_info;
 915         struct opae_retimer_status opae_rtm_status;
 916         struct opae_eth_group_info opae_eth_grp_info;
 917         struct opae_eth_group_region_info opae_eth_grp_reg_info;
 918         int eth_group_num = 0;
 919         uint64_t port_link_bitmap = 0, port_link_bit;
 920         uint32_t i, j, p, q;
 921
 922 #define MAX_PORT_PER_RETIMER    4
 923
 924         IFPGA_RAWDEV_PMD_FUNC_TRACE();
 925
 926         if (!dev || !attr_name || !attr_value) {
 927                 IFPGA_RAWDEV_PMD_ERR("Invalid arguments for getting attributes");
 928                 return -1;
 929         }
 930
 931         adapter = ifpga_rawdev_get_priv(dev);
 932         if (!adapter) {
 933                 IFPGA_RAWDEV_PMD_ERR("Adapter of dev %s is NULL", dev->name);
 934                 return -1;
 935         }
 936
 937         mgr = opae_adapter_get_mgr(adapter);
 938         if (!mgr) {
 939                 IFPGA_RAWDEV_PMD_ERR("opae_manager of opae_adapter is NULL");
 940                 return -1;
 941         }
 942
 943         /* currently, eth_group_num is always 2 */
 944         eth_group_num = opae_manager_get_eth_group_nums(mgr);
 945         if (eth_group_num < 0)
 946                 return -1;
 947
 948         if (!strcmp(attr_name, "LineSideBaseMAC")) {
 949                 /* Currently FPGA not implement, so just set all zeros*/
 950                 *attr_value = (uint64_t)0;
 951                 return 0;
 952         }
 953         if (!strcmp(attr_name, "LineSideMACType")) {
 954                 /* eth_group 0 on FPGA connect to LineSide */
 955                 if (opae_manager_get_eth_group_info(mgr, 0,
 956                         &opae_eth_grp_info))
 957                         return -1;
 958                 switch (opae_eth_grp_info.speed) {
 959                 case ETH_SPEED_10G:
 960                         *attr_value =
 961                         (uint64_t)(IFPGA_RAWDEV_RETIMER_MAC_TYPE_10GE_XFI);
 962                         break;
 963                 case ETH_SPEED_25G:
 964                         *attr_value =
 965                         (uint64_t)(IFPGA_RAWDEV_RETIMER_MAC_TYPE_25GE_25GAUI);
 966                         break;
 967                 default:
 968                         *attr_value =
 969                         (uint64_t)(IFPGA_RAWDEV_RETIMER_MAC_TYPE_UNKNOWN);
 970                         break;
 971                 }
 972                 return 0;
 973         }
 974         if (!strcmp(attr_name, "LineSideLinkSpeed")) {
 975                 if (opae_manager_get_retimer_status(mgr, &opae_rtm_status))
 976                         return -1;
 977                 switch (opae_rtm_status.speed) {
 978                 case MXD_1GB:
 979                         *attr_value =
 980                                 (uint64_t)(IFPGA_RAWDEV_LINK_SPEED_UNKNOWN);
 981                         break;
 982                 case MXD_2_5GB:
 983                         *attr_value =
 984                                 (uint64_t)(IFPGA_RAWDEV_LINK_SPEED_UNKNOWN);
 985                         break;
 986                 case MXD_5GB:
 987                         *attr_value =
 988                                 (uint64_t)(IFPGA_RAWDEV_LINK_SPEED_UNKNOWN);
 989                         break;
 990                 case MXD_10GB:
 991                         *attr_value =
 992                                 (uint64_t)(IFPGA_RAWDEV_LINK_SPEED_10GB);
 993                         break;
 994                 case MXD_25GB:
 995                         *attr_value =
 996                                 (uint64_t)(IFPGA_RAWDEV_LINK_SPEED_25GB);
 997                         break;
 998                 case MXD_40GB:
 999                         *attr_value =
1000                                 (uint64_t)(IFPGA_RAWDEV_LINK_SPEED_40GB);
1001                         break;
1002                 case MXD_100GB:
1003                         *attr_value =
1004                                 (uint64_t)(IFPGA_RAWDEV_LINK_SPEED_UNKNOWN);
1005                         break;
1006                 case MXD_SPEED_UNKNOWN:
1007                         *attr_value =
1008                                 (uint64_t)(IFPGA_RAWDEV_LINK_SPEED_UNKNOWN);
1009                         break;
1010                 default:
1011                         *attr_value =
1012                                 (uint64_t)(IFPGA_RAWDEV_LINK_SPEED_UNKNOWN);
1013                         break;
1014                 }
1015                 return 0;
1016         }
1017         if (!strcmp(attr_name, "LineSideLinkRetimerNum")) {
1018                 if (opae_manager_get_retimer_info(mgr, &opae_rtm_info))
1019                         return -1;
1020                 *attr_value = (uint64_t)(opae_rtm_info.nums_retimer);
1021                 return 0;
1022         }
1023         if (!strcmp(attr_name, "LineSideLinkPortNum")) {
1024                 if (opae_manager_get_retimer_info(mgr, &opae_rtm_info))
1025                         return -1;
1026                 uint64_t tmp = (uint64_t)opae_rtm_info.ports_per_retimer *
1027                                         (uint64_t)opae_rtm_info.nums_retimer;
1028                 *attr_value = tmp;
1029                 return 0;
1030         }
1031         if (!strcmp(attr_name, "LineSideLinkStatus")) {
1032                 if (opae_manager_get_retimer_info(mgr, &opae_rtm_info))
1033                         return -1;
1034                 if (opae_manager_get_retimer_status(mgr, &opae_rtm_status))
1035                         return -1;
1036                 (*attr_value) = 0;
1037                 q = 0;
1038                 port_link_bitmap = (uint64_t)(opae_rtm_status.line_link_bitmap);
1039                 for (i = 0; i < opae_rtm_info.nums_retimer; i++) {
1040                         p = i * MAX_PORT_PER_RETIMER;
1041                         for (j = 0; j < opae_rtm_info.ports_per_retimer; j++) {
1042                                 port_link_bit = 0;
1043                                 IFPGA_BIT_SET(port_link_bit, (p+j));
1044                                 port_link_bit &= port_link_bitmap;
1045                                 if (port_link_bit)
1046                                         IFPGA_BIT_SET((*attr_value), q);
1047                                 q++;
1048                         }
1049                 }
1050                 return 0;
1051         }
1052         if (!strcmp(attr_name, "LineSideBARIndex")) {
1053                 /* eth_group 0 on FPGA connect to LineSide */
1054                 if (opae_manager_get_eth_group_region_info(mgr, 0,
1055                         &opae_eth_grp_reg_info))
1056                         return -1;
1057                 *attr_value = (uint64_t)opae_eth_grp_reg_info.mem_idx;
1058                 return 0;
1059         }
1060         if (!strcmp(attr_name, "NICSideMACType")) {
1061                 /* eth_group 1 on FPGA connect to NicSide */
1062                 if (opae_manager_get_eth_group_info(mgr, 1,
1063                         &opae_eth_grp_info))
1064                         return -1;
1065                 *attr_value = (uint64_t)(opae_eth_grp_info.speed);
1066                 return 0;
1067         }
1068         if (!strcmp(attr_name, "NICSideLinkSpeed")) {
1069                 /* eth_group 1 on FPGA connect to NicSide */
1070                 if (opae_manager_get_eth_group_info(mgr, 1,
1071                         &opae_eth_grp_info))
1072                         return -1;
1073                 *attr_value = (uint64_t)(opae_eth_grp_info.speed);
1074                 return 0;
1075         }
1076         if (!strcmp(attr_name, "NICSideLinkPortNum")) {
1077                 if (opae_manager_get_retimer_info(mgr, &opae_rtm_info))
1078                         return -1;
1079                 uint64_t tmp = (uint64_t)opae_rtm_info.nums_fvl *
1080                                         (uint64_t)opae_rtm_info.ports_per_fvl;
1081                 *attr_value = tmp;
1082                 return 0;
1083         }
1084         if (!strcmp(attr_name, "NICSideLinkStatus"))
1085                 return 0;
1086         if (!strcmp(attr_name, "NICSideBARIndex")) {
1087                 /* eth_group 1 on FPGA connect to NicSide */
1088                 if (opae_manager_get_eth_group_region_info(mgr, 1,
1089                         &opae_eth_grp_reg_info))
1090                         return -1;
1091                 *attr_value = (uint64_t)opae_eth_grp_reg_info.mem_idx;
1092                 return 0;
1093         }
1094
1095         IFPGA_RAWDEV_PMD_ERR("%s not support", attr_name);
1096         return -1;
1097 }
1098
1099 static const struct rte_rawdev_ops ifpga_rawdev_ops = {
1100         .dev_info_get = ifpga_rawdev_info_get,
1101         .dev_configure = ifpga_rawdev_configure,
1102         .dev_start = ifpga_rawdev_start,
1103         .dev_stop = ifpga_rawdev_stop,
1104         .dev_close = ifpga_rawdev_close,
1105         .dev_reset = ifpga_rawdev_reset,
1106
1107         .queue_def_conf = NULL,
1108         .queue_setup = NULL,
1109         .queue_release = NULL,
1110
1111         .attr_get = ifpga_rawdev_get_attr,
1112         .attr_set = NULL,
1113
1114         .enqueue_bufs = NULL,
1115         .dequeue_bufs = NULL,
1116
1117         .dump = NULL,
1118
1119         .xstats_get = NULL,
1120         .xstats_get_names = NULL,
1121         .xstats_get_by_name = NULL,
1122         .xstats_reset = NULL,
1123
1124         .firmware_status_get = NULL,
1125         .firmware_version_get = NULL,
1126         .firmware_load = ifpga_rawdev_pr,
1127         .firmware_unload = NULL,
1128
1129         .dev_selftest = NULL,
1130 };
1131
1132 static int
1133 ifpga_get_fme_error_prop(struct opae_manager *mgr,
1134                 u64 prop_id, u64 *val)
1135 {
1136         struct feature_prop prop;
1137
1138         prop.feature_id = IFPGA_FME_FEATURE_ID_GLOBAL_ERR;
1139         prop.prop_id = prop_id;
1140
1141         if (opae_manager_ifpga_get_prop(mgr, &prop))
1142                 return -EINVAL;
1143
1144         *val = prop.data;
1145
1146         return 0;
1147 }
1148
1149 static int
1150 ifpga_set_fme_error_prop(struct opae_manager *mgr,
1151                 u64 prop_id, u64 val)
1152 {
1153         struct feature_prop prop;
1154
1155         prop.feature_id = IFPGA_FME_FEATURE_ID_GLOBAL_ERR;
1156         prop.prop_id = prop_id;
1157
1158         prop.data = val;
1159
1160         if (opae_manager_ifpga_set_prop(mgr, &prop))
1161                 return -EINVAL;
1162
1163         return 0;
1164 }
1165
1166 static int
1167 fme_err_read_seu_emr(struct opae_manager *mgr)
1168 {
1169         u64 val;
1170         int ret;
1171
1172         ret = ifpga_get_fme_error_prop(mgr, FME_ERR_PROP_SEU_EMR_LOW, &val);
1173         if (ret)
1174                 return -EINVAL;
1175
1176         IFPGA_RAWDEV_PMD_INFO("seu emr low: 0x%" PRIx64 "\n", val);
1177
1178         ret = ifpga_get_fme_error_prop(mgr, FME_ERR_PROP_SEU_EMR_HIGH, &val);
1179         if (ret)
1180                 return -EINVAL;
1181
1182         IFPGA_RAWDEV_PMD_INFO("seu emr high: 0x%" PRIx64 "\n", val);
1183
1184         return 0;
1185 }
1186
1187 static int fme_clear_warning_intr(struct opae_manager *mgr)
1188 {
1189         u64 val;
1190
1191         if (ifpga_set_fme_error_prop(mgr, FME_ERR_PROP_INJECT_ERRORS, 0))
1192                 return -EINVAL;
1193
1194         if (ifpga_get_fme_error_prop(mgr, FME_ERR_PROP_NONFATAL_ERRORS, &val))
1195                 return -EINVAL;
1196         if ((val & 0x40) != 0)
1197                 IFPGA_RAWDEV_PMD_INFO("clean not done\n");
1198
1199         return 0;
1200 }
1201
1202 static int fme_clean_fme_error(struct opae_manager *mgr)
1203 {
1204         u64 val;
1205
1206         if (ifpga_get_fme_error_prop(mgr, FME_ERR_PROP_ERRORS, &val))
1207                 return -EINVAL;
1208
1209         IFPGA_RAWDEV_PMD_DEBUG("before clean 0x%" PRIx64 "\n", val);
1210
1211         ifpga_set_fme_error_prop(mgr, FME_ERR_PROP_CLEAR, val);
1212
1213         if (ifpga_get_fme_error_prop(mgr, FME_ERR_PROP_ERRORS, &val))
1214                 return -EINVAL;
1215
1216         IFPGA_RAWDEV_PMD_DEBUG("after clean 0x%" PRIx64 "\n", val);
1217
1218         return 0;
1219 }
1220
1221 static int
1222 fme_err_handle_error0(struct opae_manager *mgr)
1223 {
1224         struct feature_fme_error0 fme_error0;
1225         u64 val;
1226
1227         if (ifpga_get_fme_error_prop(mgr, FME_ERR_PROP_ERRORS, &val))
1228                 return -EINVAL;
1229
1230         if (fme_clean_fme_error(mgr))
1231                 return -EINVAL;
1232
1233         fme_error0.csr = val;
1234
1235         if (fme_error0.fabric_err)
1236                 IFPGA_RAWDEV_PMD_ERR("Fabric error\n");
1237         else if (fme_error0.fabfifo_overflow)
1238                 IFPGA_RAWDEV_PMD_ERR("Fabric fifo under/overflow error\n");
1239         else if (fme_error0.afu_acc_mode_err)
1240                 IFPGA_RAWDEV_PMD_ERR("AFU PF/VF access mismatch detected\n");
1241         else if (fme_error0.pcie0cdc_parity_err)
1242                 IFPGA_RAWDEV_PMD_ERR("PCIe0 CDC Parity Error\n");
1243         else if (fme_error0.cvlcdc_parity_err)
1244                 IFPGA_RAWDEV_PMD_ERR("CVL CDC Parity Error\n");
1245         else if (fme_error0.fpgaseuerr)
1246                 fme_err_read_seu_emr(mgr);
1247
1248         /* clean the errors */
1249         if (ifpga_set_fme_error_prop(mgr, FME_ERR_PROP_ERRORS, val))
1250                 return -EINVAL;
1251
1252         return 0;
1253 }
1254
1255 static int
1256 fme_err_handle_catfatal_error(struct opae_manager *mgr)
1257 {
1258         struct feature_fme_ras_catfaterror fme_catfatal;
1259         u64 val;
1260
1261         if (ifpga_get_fme_error_prop(mgr, FME_ERR_PROP_CATFATAL_ERRORS, &val))
1262                 return -EINVAL;
1263
1264         fme_catfatal.csr = val;
1265
1266         if (fme_catfatal.cci_fatal_err)
1267                 IFPGA_RAWDEV_PMD_ERR("CCI error detected\n");
1268         else if (fme_catfatal.fabric_fatal_err)
1269                 IFPGA_RAWDEV_PMD_ERR("Fabric fatal error detected\n");
1270         else if (fme_catfatal.pcie_poison_err)
1271                 IFPGA_RAWDEV_PMD_ERR("Poison error from PCIe ports\n");
1272         else if (fme_catfatal.inject_fata_err)
1273                 IFPGA_RAWDEV_PMD_ERR("Injected Fatal Error\n");
1274         else if (fme_catfatal.crc_catast_err)
1275                 IFPGA_RAWDEV_PMD_ERR("a catastrophic EDCRC error\n");
1276         else if (fme_catfatal.injected_catast_err)
1277                 IFPGA_RAWDEV_PMD_ERR("Injected Catastrophic Error\n");
1278         else if (fme_catfatal.bmc_seu_catast_err)
1279                 fme_err_read_seu_emr(mgr);
1280
1281         return 0;
1282 }
1283
1284 static int
1285 fme_err_handle_nonfaterror(struct opae_manager *mgr)
1286 {
1287         struct feature_fme_ras_nonfaterror nonfaterr;
1288         u64 val;
1289
1290         if (ifpga_get_fme_error_prop(mgr, FME_ERR_PROP_NONFATAL_ERRORS, &val))
1291                 return -EINVAL;
1292
1293         nonfaterr.csr = val;
1294
1295         if (nonfaterr.temp_thresh_ap1)
1296                 IFPGA_RAWDEV_PMD_INFO("Temperature threshold triggered AP1\n");
1297         else if (nonfaterr.temp_thresh_ap2)
1298                 IFPGA_RAWDEV_PMD_INFO("Temperature threshold triggered AP2\n");
1299         else if (nonfaterr.pcie_error)
1300                 IFPGA_RAWDEV_PMD_INFO("an error has occurred in pcie\n");
1301         else if (nonfaterr.portfatal_error)
1302                 IFPGA_RAWDEV_PMD_INFO("fatal error occurred in AFU port.\n");
1303         else if (nonfaterr.proc_hot)
1304                 IFPGA_RAWDEV_PMD_INFO("a ProcHot event\n");
1305         else if (nonfaterr.afu_acc_mode_err)
1306                 IFPGA_RAWDEV_PMD_INFO("an AFU PF/VF access mismatch\n");
1307         else if (nonfaterr.injected_nonfata_err) {
1308                 IFPGA_RAWDEV_PMD_INFO("Injected Warning Error\n");
1309                 fme_clear_warning_intr(mgr);
1310         } else if (nonfaterr.temp_thresh_AP6)
1311                 IFPGA_RAWDEV_PMD_INFO("Temperature threshold triggered AP6\n");
1312         else if (nonfaterr.power_thresh_AP1)
1313                 IFPGA_RAWDEV_PMD_INFO("Power threshold triggered AP1\n");
1314         else if (nonfaterr.power_thresh_AP2)
1315                 IFPGA_RAWDEV_PMD_INFO("Power threshold triggered AP2\n");
1316         else if (nonfaterr.mbp_err)
1317                 IFPGA_RAWDEV_PMD_INFO("an MBP event\n");
1318
1319         return 0;
1320 }
1321
1322 static void
1323 fme_interrupt_handler(void *param)
1324 {
1325         struct opae_manager *mgr = (struct opae_manager *)param;
1326
1327         IFPGA_RAWDEV_PMD_INFO("%s interrupt occurred\n", __func__);
1328
1329         fme_err_handle_error0(mgr);
1330         fme_err_handle_nonfaterror(mgr);
1331         fme_err_handle_catfatal_error(mgr);
1332 }
1333
1334 int
1335 ifpga_unregister_msix_irq(enum ifpga_irq_type type,
1336                 int vec_start, rte_intr_callback_fn handler, void *arg)
1337 {
1338         struct rte_intr_handle intr_handle;
1339
1340         if (type == IFPGA_FME_IRQ)
1341                 intr_handle = ifpga_irq_handle[0];
1342         else if (type == IFPGA_AFU_IRQ)
1343                 intr_handle = ifpga_irq_handle[vec_start + 1];
1344
1345         rte_intr_efd_disable(&intr_handle);
1346
1347         return rte_intr_callback_unregister(&intr_handle,
1348                         handler, arg);
1349 }
1350
1351 int
1352 ifpga_register_msix_irq(struct rte_rawdev *dev, int port_id,
1353                 enum ifpga_irq_type type, int vec_start, int count,
1354                 rte_intr_callback_fn handler, const char *name,
1355                 void *arg)
1356 {
1357         int ret;
1358         struct rte_intr_handle intr_handle;
1359         struct opae_adapter *adapter;
1360         struct opae_manager *mgr;
1361         struct opae_accelerator *acc;
1362
1363         adapter = ifpga_rawdev_get_priv(dev);
1364         if (!adapter)
1365                 return -ENODEV;
1366
1367         mgr = opae_adapter_get_mgr(adapter);
1368         if (!mgr)
1369                 return -ENODEV;
1370
1371         if (type == IFPGA_FME_IRQ) {
1372                 intr_handle = ifpga_irq_handle[0];
1373                 count = 1;
1374         } else if (type == IFPGA_AFU_IRQ)
1375                 intr_handle = ifpga_irq_handle[vec_start + 1];
1376
1377         intr_handle.type = RTE_INTR_HANDLE_VFIO_MSIX;
1378
1379         ret = rte_intr_efd_enable(&intr_handle, count);
1380         if (ret)
1381                 return -ENODEV;
1382
1383         intr_handle.fd = intr_handle.efds[0];
1384
1385         IFPGA_RAWDEV_PMD_DEBUG("register %s irq, vfio_fd=%d, fd=%d\n",
1386                         name, intr_handle.vfio_dev_fd,
1387                         intr_handle.fd);
1388
1389         if (type == IFPGA_FME_IRQ) {
1390                 struct fpga_fme_err_irq_set err_irq_set;
1391                 err_irq_set.evtfd = intr_handle.efds[0];
1392
1393                 ret = opae_manager_ifpga_set_err_irq(mgr, &err_irq_set);
1394                 if (ret)
1395                         return -EINVAL;
1396         } else if (type == IFPGA_AFU_IRQ) {
1397                 acc = opae_adapter_get_acc(adapter, port_id);
1398                 if (!acc)
1399                         return -EINVAL;
1400
1401                 ret = opae_acc_set_irq(acc, vec_start, count, intr_handle.efds);
1402                 if (ret)
1403                         return -EINVAL;
1404         }
1405
1406         /* register interrupt handler using DPDK API */
1407         ret = rte_intr_callback_register(&intr_handle,
1408                         handler, (void *)arg);
1409         if (ret)
1410                 return -EINVAL;
1411
1412         IFPGA_RAWDEV_PMD_INFO("success register %s interrupt\n", name);
1413
1414         return 0;
1415 }
1416
1417 static int
1418 ifpga_rawdev_create(struct rte_pci_device *pci_dev,
1419                         int socket_id)
1420 {
1421         int ret = 0;
1422         struct rte_rawdev *rawdev = NULL;
1423         struct ifpga_rawdev *dev = NULL;
1424         struct opae_adapter *adapter = NULL;
1425         struct opae_manager *mgr = NULL;
1426         struct opae_adapter_data_pci *data = NULL;
1427         char name[RTE_RAWDEV_NAME_MAX_LEN];
1428         int i;
1429
1430         if (!pci_dev) {
1431                 IFPGA_RAWDEV_PMD_ERR("Invalid pci_dev of the device!");
1432                 ret = -EINVAL;
1433                 goto cleanup;
1434         }
1435
1436         memset(name, 0, sizeof(name));
1437         snprintf(name, RTE_RAWDEV_NAME_MAX_LEN, "IFPGA:%02x:%02x.%x",
1438                 pci_dev->addr.bus, pci_dev->addr.devid, pci_dev->addr.function);
1439
1440         IFPGA_RAWDEV_PMD_INFO("Init %s on NUMA node %d", name, rte_socket_id());
1441
1442         /* Allocate device structure */
1443         rawdev = rte_rawdev_pmd_allocate(name, sizeof(struct opae_adapter),
1444                                          socket_id);
1445         if (rawdev == NULL) {
1446                 IFPGA_RAWDEV_PMD_ERR("Unable to allocate rawdevice");
1447                 ret = -EINVAL;
1448                 goto cleanup;
1449         }
1450
1451         ipn3ke_bridge_func.get_ifpga_rawdev = ifpga_rawdev_get;
1452         ipn3ke_bridge_func.set_i40e_sw_dev = rte_pmd_i40e_set_switch_dev;
1453
1454         dev = ifpga_rawdev_allocate(rawdev);
1455         if (dev == NULL) {
1456                 IFPGA_RAWDEV_PMD_ERR("Unable to allocate ifpga_rawdevice");
1457                 ret = -EINVAL;
1458                 goto cleanup;
1459         }
1460         dev->aer_enable = 0;
1461
1462         /* alloc OPAE_FPGA_PCI data to register to OPAE hardware level API */
1463         data = opae_adapter_data_alloc(OPAE_FPGA_PCI);
1464         if (!data) {
1465                 ret = -ENOMEM;
1466                 goto cleanup;
1467         }
1468
1469         /* init opae_adapter_data_pci for device specific information */
1470         for (i = 0; i < PCI_MAX_RESOURCE; i++) {
1471                 data->region[i].phys_addr = pci_dev->mem_resource[i].phys_addr;
1472                 data->region[i].len = pci_dev->mem_resource[i].len;
1473                 data->region[i].addr = pci_dev->mem_resource[i].addr;
1474         }
1475         data->device_id = pci_dev->id.device_id;
1476         data->vendor_id = pci_dev->id.vendor_id;
1477         data->bus = pci_dev->addr.bus;
1478         data->devid = pci_dev->addr.devid;
1479         data->function = pci_dev->addr.function;
1480         data->vfio_dev_fd = pci_dev->intr_handle.vfio_dev_fd;
1481
1482         adapter = rawdev->dev_private;
1483         /* create a opae_adapter based on above device data */
1484         ret = opae_adapter_init(adapter, pci_dev->device.name, data);
1485         if (ret) {
1486                 ret = -ENOMEM;
1487                 goto free_adapter_data;
1488         }
1489
1490         rawdev->dev_ops = &ifpga_rawdev_ops;
1491         rawdev->device = &pci_dev->device;
1492         rawdev->driver_name = pci_dev->driver->driver.name;
1493
1494         /* must enumerate the adapter before use it */
1495         ret = opae_adapter_enumerate(adapter);
1496         if (ret)
1497                 goto free_adapter_data;
1498
1499         /* get opae_manager to rawdev */
1500         mgr = opae_adapter_get_mgr(adapter);
1501         if (mgr) {
1502                 /* PF function */
1503                 IFPGA_RAWDEV_PMD_INFO("this is a PF function");
1504         }
1505
1506         ret = ifpga_register_msix_irq(rawdev, 0, IFPGA_FME_IRQ, 0, 0,
1507                         fme_interrupt_handler, "fme_irq", mgr);
1508         if (ret)
1509                 goto free_adapter_data;
1510
1511         return ret;
1512
1513 free_adapter_data:
1514         if (data)
1515                 opae_adapter_data_free(data);
1516 cleanup:
1517         if (rawdev)
1518                 rte_rawdev_pmd_release(rawdev);
1519
1520         return ret;
1521 }
1522
1523 static int
1524 ifpga_rawdev_destroy(struct rte_pci_device *pci_dev)
1525 {
1526         int ret;
1527         struct rte_rawdev *rawdev;
1528         char name[RTE_RAWDEV_NAME_MAX_LEN];
1529         struct opae_adapter *adapter;
1530         struct opae_manager *mgr;
1531
1532         if (!pci_dev) {
1533                 IFPGA_RAWDEV_PMD_ERR("Invalid pci_dev of the device!");
1534                 ret = -EINVAL;
1535                 return ret;
1536         }
1537
1538         memset(name, 0, sizeof(name));
1539         snprintf(name, RTE_RAWDEV_NAME_MAX_LEN, "IFPGA:%x:%02x.%x",
1540                 pci_dev->addr.bus, pci_dev->addr.devid, pci_dev->addr.function);
1541
1542         IFPGA_RAWDEV_PMD_INFO("Closing %s on NUMA node %d",
1543                 name, rte_socket_id());
1544
1545         rawdev = rte_rawdev_pmd_get_named_dev(name);
1546         if (!rawdev) {
1547                 IFPGA_RAWDEV_PMD_ERR("Invalid device name (%s)", name);
1548                 return -EINVAL;
1549         }
1550
1551         adapter = ifpga_rawdev_get_priv(rawdev);
1552         if (!adapter)
1553                 return -ENODEV;
1554
1555         mgr = opae_adapter_get_mgr(adapter);
1556         if (!mgr)
1557                 return -ENODEV;
1558
1559         if (ifpga_unregister_msix_irq(IFPGA_FME_IRQ, 0,
1560                                 fme_interrupt_handler, mgr))
1561                 return -EINVAL;
1562
1563         opae_adapter_data_free(adapter->data);
1564         opae_adapter_free(adapter);
1565
1566         /* rte_rawdev_close is called by pmd_release */
1567         ret = rte_rawdev_pmd_release(rawdev);
1568         if (ret)
1569                 IFPGA_RAWDEV_PMD_DEBUG("Device cleanup failed");
1570
1571         return ret;
1572 }
1573
1574 static int
1575 ifpga_rawdev_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1576         struct rte_pci_device *pci_dev)
1577 {
1578         IFPGA_RAWDEV_PMD_FUNC_TRACE();
1579         return ifpga_rawdev_create(pci_dev, rte_socket_id());
1580 }
1581
1582 static int
1583 ifpga_rawdev_pci_remove(struct rte_pci_device *pci_dev)
1584 {
1585         ifpga_monitor_stop_func();
1586         return ifpga_rawdev_destroy(pci_dev);
1587 }
1588
1589 static struct rte_pci_driver rte_ifpga_rawdev_pmd = {
1590         .id_table  = pci_ifpga_map,
1591         .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
1592         .probe     = ifpga_rawdev_pci_probe,
1593         .remove    = ifpga_rawdev_pci_remove,
1594 };
1595
1596 RTE_PMD_REGISTER_PCI(ifpga_rawdev_pci_driver, rte_ifpga_rawdev_pmd);
1597 RTE_PMD_REGISTER_PCI_TABLE(ifpga_rawdev_pci_driver, rte_ifpga_rawdev_pmd);
1598 RTE_PMD_REGISTER_KMOD_DEP(ifpga_rawdev_pci_driver, "* igb_uio | uio_pci_generic | vfio-pci");
1599 RTE_LOG_REGISTER(ifpga_rawdev_logtype, driver.raw.init, NOTICE);
1600
1601 static const char * const valid_args[] = {
1602 #define IFPGA_ARG_NAME         "ifpga"
1603         IFPGA_ARG_NAME,
1604 #define IFPGA_ARG_PORT         "port"
1605         IFPGA_ARG_PORT,
1606 #define IFPGA_AFU_BTS          "afu_bts"
1607         IFPGA_AFU_BTS,
1608         NULL
1609 };
1610
1611 static int ifpga_rawdev_get_string_arg(const char *key __rte_unused,
1612         const char *value, void *extra_args)
1613 {
1614         int size;
1615         if (!value || !extra_args)
1616                 return -EINVAL;
1617
1618         size = strlen(value) + 1;
1619         *(char **)extra_args = rte_malloc(NULL, size, RTE_CACHE_LINE_SIZE);
1620         if (!*(char **)extra_args)
1621                 return -ENOMEM;
1622
1623         strlcpy(*(char **)extra_args, value, size);
1624
1625         return 0;
1626 }
1627 static int
1628 ifpga_cfg_probe(struct rte_vdev_device *dev)
1629 {
1630         struct rte_devargs *devargs;
1631         struct rte_kvargs *kvlist = NULL;
1632         struct rte_rawdev *rawdev = NULL;
1633         struct ifpga_rawdev *ifpga_dev;
1634         int port;
1635         char *name = NULL;
1636         const char *bdf;
1637         char dev_name[RTE_RAWDEV_NAME_MAX_LEN];
1638         int ret = -1;
1639
1640         devargs = dev->device.devargs;
1641
1642         kvlist = rte_kvargs_parse(devargs->args, valid_args);
1643         if (!kvlist) {
1644                 IFPGA_RAWDEV_PMD_LOG(ERR, "error when parsing param");
1645                 goto end;
1646         }
1647
1648         if (rte_kvargs_count(kvlist, IFPGA_ARG_NAME) == 1) {
1649                 if (rte_kvargs_process(kvlist, IFPGA_ARG_NAME,
1650                                        &ifpga_rawdev_get_string_arg,
1651                                        &name) < 0) {
1652                         IFPGA_RAWDEV_PMD_ERR("error to parse %s",
1653                                      IFPGA_ARG_NAME);
1654                         goto end;
1655                 }
1656         } else {
1657                 IFPGA_RAWDEV_PMD_ERR("arg %s is mandatory for ifpga bus",
1658                           IFPGA_ARG_NAME);
1659                 goto end;
1660         }
1661
1662         if (rte_kvargs_count(kvlist, IFPGA_ARG_PORT) == 1) {
1663                 if (rte_kvargs_process(kvlist,
1664                         IFPGA_ARG_PORT,
1665                         &rte_ifpga_get_integer32_arg,
1666                         &port) < 0) {
1667                         IFPGA_RAWDEV_PMD_ERR("error to parse %s",
1668                                 IFPGA_ARG_PORT);
1669                         goto end;
1670                 }
1671         } else {
1672                 IFPGA_RAWDEV_PMD_ERR("arg %s is mandatory for ifpga bus",
1673                           IFPGA_ARG_PORT);
1674                 goto end;
1675         }
1676
1677         memset(dev_name, 0, sizeof(dev_name));
1678         snprintf(dev_name, RTE_RAWDEV_NAME_MAX_LEN, "IFPGA:%s", name);
1679         rawdev = rte_rawdev_pmd_get_named_dev(dev_name);
1680         if (!rawdev)
1681                 goto end;
1682         ifpga_dev = ifpga_rawdev_get(rawdev);
1683         if (!ifpga_dev)
1684                 goto end;
1685         bdf = name;
1686         ifpga_rawdev_fill_info(ifpga_dev, bdf);
1687
1688         ifpga_monitor_start_func();
1689
1690         memset(dev_name, 0, sizeof(dev_name));
1691         snprintf(dev_name, RTE_RAWDEV_NAME_MAX_LEN, "%d|%s",
1692         port, name);
1693
1694         ret = rte_eal_hotplug_add(RTE_STR(IFPGA_BUS_NAME),
1695                         dev_name, devargs->args);
1696 end:
1697         if (kvlist)
1698                 rte_kvargs_free(kvlist);
1699         if (name)
1700                 free(name);
1701
1702         return ret;
1703 }
1704
1705 static int
1706 ifpga_cfg_remove(struct rte_vdev_device *vdev)
1707 {
1708         IFPGA_RAWDEV_PMD_INFO("Remove ifpga_cfg %p",
1709                 vdev);
1710
1711         return 0;
1712 }
1713
1714 static struct rte_vdev_driver ifpga_cfg_driver = {
1715         .probe = ifpga_cfg_probe,
1716         .remove = ifpga_cfg_remove,
1717 };
1718
1719 RTE_PMD_REGISTER_VDEV(ifpga_rawdev_cfg, ifpga_cfg_driver);
1720 RTE_PMD_REGISTER_ALIAS(ifpga_rawdev_cfg, ifpga_cfg);
1721 RTE_PMD_REGISTER_PARAM_STRING(ifpga_rawdev_cfg,
1722         "ifpga=<string> "
1723         "port=<int> "
1724         "afu_bts=<path>");