drivers/raw/ifpga/ifpga_rawdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2010-2018 Intel Corporation
   3  */
   4
   5 #include <string.h>
   6 #include <dirent.h>
   7 #include <sys/stat.h>
   8 #include <unistd.h>
   9 #include <sys/types.h>
  10 #include <fcntl.h>
  11 #include <sys/ioctl.h>
  12 #include <sys/epoll.h>
  13 #include <rte_log.h>
  14 #include <rte_bus.h>
  15 #include <rte_malloc.h>
  16 #include <rte_devargs.h>
  17 #include <rte_memcpy.h>
  18 #include <rte_pci.h>
  19 #include <rte_bus_pci.h>
  20 #include <rte_kvargs.h>
  21 #include <rte_alarm.h>
  22 #include <rte_interrupts.h>
  23 #include <rte_errno.h>
  24 #include <rte_per_lcore.h>
  25 #include <rte_memory.h>
  26 #include <rte_memzone.h>
  27 #include <rte_eal.h>
  28 #include <rte_common.h>
  29 #include <rte_bus_vdev.h>
  30 #include <rte_string_fns.h>
  31 #include <rte_pmd_i40e.h>
  32
  33 #include "base/opae_hw_api.h"
  34 #include "base/opae_ifpga_hw_api.h"
  35 #include "base/ifpga_api.h"
  36 #include "rte_rawdev.h"
  37 #include "rte_rawdev_pmd.h"
  38 #include "rte_bus_ifpga.h"
  39 #include "ifpga_common.h"
  40 #include "ifpga_logs.h"
  41 #include "ifpga_rawdev.h"
  42 #include "ipn3ke_rawdev_api.h"
  43
  44 #define RTE_PCI_EXT_CAP_ID_ERR           0x01   /* Advanced Error Reporting */
  45 #define RTE_PCI_CFG_SPACE_SIZE           256
  46 #define RTE_PCI_CFG_SPACE_EXP_SIZE       4096
  47 #define RTE_PCI_EXT_CAP_ID(header)       (int)(header & 0x0000ffff)
  48 #define RTE_PCI_EXT_CAP_NEXT(header)     ((header >> 20) & 0xffc)
  49
  50 int ifpga_rawdev_logtype;
  51
  52 #define PCI_VENDOR_ID_INTEL          0x8086
  53 /* PCI Device ID */
  54 #define PCIE_DEVICE_ID_PF_INT_5_X    0xBCBD
  55 #define PCIE_DEVICE_ID_PF_INT_6_X    0xBCC0
  56 #define PCIE_DEVICE_ID_PF_DSC_1_X    0x09C4
  57 #define PCIE_DEVICE_ID_PAC_N3000     0x0B30
  58 /* VF Device */
  59 #define PCIE_DEVICE_ID_VF_INT_5_X    0xBCBF
  60 #define PCIE_DEVICE_ID_VF_INT_6_X    0xBCC1
  61 #define PCIE_DEVICE_ID_VF_DSC_1_X    0x09C5
  62 #define PCIE_DEVICE_ID_VF_PAC_N3000  0x0B31
  63 #define RTE_MAX_RAW_DEVICE           10
  64
  65 static const struct rte_pci_id pci_ifpga_map[] = {
  66         { RTE_PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_PF_INT_5_X) },
  67         { RTE_PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_VF_INT_5_X) },
  68         { RTE_PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_PF_INT_6_X) },
  69         { RTE_PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_VF_INT_6_X) },
  70         { RTE_PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_PF_DSC_1_X) },
  71         { RTE_PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_VF_DSC_1_X) },
  72         { RTE_PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_PAC_N3000),},
  73         { RTE_PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_VF_PAC_N3000),},
  74         { .vendor_id = 0, /* sentinel */ },
  75 };
  76
  77 static struct ifpga_rawdev ifpga_rawdevices[IFPGA_RAWDEV_NUM];
  78
  79 static int ifpga_monitor_start;
  80 static pthread_t ifpga_monitor_start_thread;
  81
  82 static struct ifpga_rawdev *
  83 ifpga_rawdev_allocate(struct rte_rawdev *rawdev);
  84 static int set_surprise_link_check_aer(
  85                 struct ifpga_rawdev *ifpga_rdev, int force_disable);
  86 static int ifpga_pci_find_next_ext_capability(unsigned int fd,
  87                 int start, int cap);
  88 static int ifpga_pci_find_ext_capability(unsigned int fd, int cap);
  89
  90 struct ifpga_rawdev *
  91 ifpga_rawdev_get(const struct rte_rawdev *rawdev)
  92 {
  93         struct ifpga_rawdev *dev;
  94         unsigned int i;
  95
  96         if (rawdev == NULL)
  97                 return NULL;
  98
  99         for (i = 0; i < IFPGA_RAWDEV_NUM; i++) {
 100                 dev = &ifpga_rawdevices[i];
 101                 if (dev->rawdev == rawdev)
 102                         return dev;
 103         }
 104
 105         return NULL;
 106 }
 107
 108 static inline uint8_t
 109 ifpga_rawdev_find_free_device_index(void)
 110 {
 111         uint16_t dev_id;
 112
 113         for (dev_id = 0; dev_id < IFPGA_RAWDEV_NUM; dev_id++) {
 114                 if (ifpga_rawdevices[dev_id].rawdev == NULL)
 115                         return dev_id;
 116         }
 117
 118         return IFPGA_RAWDEV_NUM;
 119 }
 120 static struct ifpga_rawdev *
 121 ifpga_rawdev_allocate(struct rte_rawdev *rawdev)
 122 {
 123         struct ifpga_rawdev *dev;
 124         uint16_t dev_id;
 125
 126         dev = ifpga_rawdev_get(rawdev);
 127         if (dev != NULL) {
 128                 IFPGA_RAWDEV_PMD_ERR("Event device already allocated!");
 129                 return NULL;
 130         }
 131
 132         dev_id = ifpga_rawdev_find_free_device_index();
 133         if (dev_id == IFPGA_RAWDEV_NUM) {
 134                 IFPGA_RAWDEV_PMD_ERR("Reached maximum number of raw devices");
 135                 return NULL;
 136         }
 137
 138         dev = &ifpga_rawdevices[dev_id];
 139         dev->rawdev = rawdev;
 140         dev->dev_id = dev_id;
 141
 142         return dev;
 143 }
 144
 145 static int ifpga_pci_find_next_ext_capability(unsigned int fd,
 146 int start, int cap)
 147 {
 148         uint32_t header;
 149         int ttl;
 150         int pos = RTE_PCI_CFG_SPACE_SIZE;
 151         int ret;
 152
 153         /* minimum 8 bytes per capability */
 154         ttl = (RTE_PCI_CFG_SPACE_EXP_SIZE - RTE_PCI_CFG_SPACE_SIZE) / 8;
 155
 156         if (start)
 157                 pos = start;
 158         ret = pread(fd, &header, sizeof(header), pos);
 159         if (ret == -1)
 160                 return -1;
 161
 162         /*
 163          * If we have no capabilities, this is indicated by cap ID,
 164          * cap version and next pointer all being 0.
 165          */
 166         if (header == 0)
 167                 return 0;
 168
 169         while (ttl-- > 0) {
 170                 if (RTE_PCI_EXT_CAP_ID(header) == cap && pos != start)
 171                         return pos;
 172
 173                 pos = RTE_PCI_EXT_CAP_NEXT(header);
 174                 if (pos < RTE_PCI_CFG_SPACE_SIZE)
 175                         break;
 176                 ret = pread(fd, &header, sizeof(header), pos);
 177                 if (ret == -1)
 178                         return -1;
 179         }
 180
 181         return 0;
 182 }
 183
 184 static int ifpga_pci_find_ext_capability(unsigned int fd, int cap)
 185 {
 186         return ifpga_pci_find_next_ext_capability(fd, 0, cap);
 187 }
 188
 189 static int ifpga_get_dev_vendor_id(const char *bdf,
 190         uint32_t *dev_id, uint32_t *vendor_id)
 191 {
 192         int fd;
 193         char path[1024];
 194         int ret;
 195         uint32_t header;
 196
 197         strlcpy(path, "/sys/bus/pci/devices/", sizeof(path));
 198         strlcat(path, bdf, sizeof(path));
 199         strlcat(path, "/config", sizeof(path));
 200         fd = open(path, O_RDWR);
 201         if (fd < 0)
 202                 return -1;
 203         ret = pread(fd, &header, sizeof(header), 0);
 204         if (ret == -1) {
 205                 close(fd);
 206                 return -1;
 207         }
 208         (*vendor_id) = header & 0xffff;
 209         (*dev_id) = (header >> 16) & 0xffff;
 210         close(fd);
 211
 212         return 0;
 213 }
 214 static int ifpga_rawdev_fill_info(struct ifpga_rawdev *ifpga_dev,
 215         const char *bdf)
 216 {
 217         char path[1024] = "/sys/bus/pci/devices/0000:";
 218         char link[1024], link1[1024];
 219         char dir[1024] = "/sys/devices/";
 220         char *c;
 221         int ret;
 222         char sub_brg_bdf[4][16];
 223         int point;
 224         DIR *dp = NULL;
 225         struct dirent *entry;
 226         int i, j;
 227
 228         unsigned int dom, bus, dev;
 229         int func;
 230         uint32_t dev_id, vendor_id;
 231
 232         strlcat(path, bdf, sizeof(path));
 233         memset(link, 0, sizeof(link));
 234         memset(link1, 0, sizeof(link1));
 235         ret = readlink(path, link, (sizeof(link)-1));
 236         if (ret == -1)
 237                 return -1;
 238         strlcpy(link1, link, sizeof(link1));
 239         memset(ifpga_dev->parent_bdf, 0, 16);
 240         point = strlen(link);
 241         if (point < 39)
 242                 return -1;
 243         point -= 39;
 244         link[point] = 0;
 245         if (point < 12)
 246                 return -1;
 247         point -= 12;
 248         rte_memcpy(ifpga_dev->parent_bdf, &link[point], 12);
 249
 250         point = strlen(link1);
 251         if (point < 26)
 252                 return -1;
 253         point -= 26;
 254         link1[point] = 0;
 255         if (point < 12)
 256                 return -1;
 257         point -= 12;
 258         c = strchr(link1, 'p');
 259         if (!c)
 260                 return -1;
 261         strlcat(dir, c, sizeof(dir));
 262
 263         /* scan folder */
 264         dp = opendir(dir);
 265         if (dp == NULL)
 266                 return -1;
 267         i = 0;
 268         while ((entry = readdir(dp)) != NULL) {
 269                 if (i >= 4)
 270                         break;
 271                 if (entry->d_name[0] == '.')
 272                         continue;
 273                 if (strlen(entry->d_name) > 12)
 274                         continue;
 275                 if (sscanf(entry->d_name, "%x:%x:%x.%d",
 276                         &dom, &bus, &dev, &func) < 4)
 277                         continue;
 278                 else {
 279                         strlcpy(sub_brg_bdf[i],
 280                                 entry->d_name,
 281                                 sizeof(sub_brg_bdf[i]));
 282                         i++;
 283                 }
 284         }
 285         closedir(dp);
 286
 287         /* get fpga and fvl */
 288         j = 0;
 289         for (i = 0; i < 4; i++) {
 290                 strlcpy(link, dir, sizeof(link));
 291                 strlcat(link, "/", sizeof(link));
 292                 strlcat(link, sub_brg_bdf[i], sizeof(link));
 293                 dp = opendir(link);
 294                 if (dp == NULL)
 295                         return -1;
 296                 while ((entry = readdir(dp)) != NULL) {
 297                         if (j >= 8)
 298                                 break;
 299                         if (entry->d_name[0] == '.')
 300                                 continue;
 301
 302                         if (strlen(entry->d_name) > 12)
 303                                 continue;
 304                         if (sscanf(entry->d_name, "%x:%x:%x.%d",
 305                                 &dom, &bus, &dev, &func) < 4)
 306                                 continue;
 307                         else {
 308                                 if (ifpga_get_dev_vendor_id(entry->d_name,
 309                                         &dev_id, &vendor_id))
 310                                         continue;
 311                                 if (vendor_id == 0x8086 &&
 312                                         (dev_id == 0x0CF8 ||
 313                                         dev_id == 0x0D58 ||
 314                                         dev_id == 0x1580)) {
 315                                         strlcpy(ifpga_dev->fvl_bdf[j],
 316                                                 entry->d_name,
 317                                                 sizeof(ifpga_dev->fvl_bdf[j]));
 318                                         j++;
 319                                 }
 320                         }
 321                 }
 322                 closedir(dp);
 323         }
 324
 325         return 0;
 326 }
 327
 328 #define HIGH_FATAL(_sens, value)\
 329         (((_sens)->flags & OPAE_SENSOR_HIGH_FATAL_VALID) &&\
 330          (value > (_sens)->high_fatal))
 331
 332 #define HIGH_WARN(_sens, value)\
 333         (((_sens)->flags & OPAE_SENSOR_HIGH_WARN_VALID) &&\
 334          (value > (_sens)->high_warn))
 335
 336 #define LOW_FATAL(_sens, value)\
 337         (((_sens)->flags & OPAE_SENSOR_LOW_FATAL_VALID) &&\
 338          (value > (_sens)->low_fatal))
 339
 340 #define LOW_WARN(_sens, value)\
 341         (((_sens)->flags & OPAE_SENSOR_LOW_WARN_VALID) &&\
 342          (value > (_sens)->low_warn))
 343
 344 #define AUX_VOLTAGE_WARN 11400
 345
 346 static int
 347 ifpga_monitor_sensor(struct rte_rawdev *raw_dev,
 348                bool *gsd_start)
 349 {
 350         struct opae_adapter *adapter;
 351         struct opae_manager *mgr;
 352         struct opae_sensor_info *sensor;
 353         unsigned int value;
 354         int ret;
 355
 356         adapter = ifpga_rawdev_get_priv(raw_dev);
 357         if (!adapter)
 358                 return -ENODEV;
 359
 360         mgr = opae_adapter_get_mgr(adapter);
 361         if (!mgr)
 362                 return -ENODEV;
 363
 364         opae_mgr_for_each_sensor(mgr, sensor) {
 365                 if (!(sensor->flags & OPAE_SENSOR_VALID))
 366                         goto fail;
 367
 368                 ret = opae_mgr_get_sensor_value(mgr, sensor, &value);
 369                 if (ret)
 370                         goto fail;
 371
 372                 if (value == 0xdeadbeef) {
 373                         IFPGA_RAWDEV_PMD_ERR("dev_id %d sensor %s value %x\n",
 374                                         raw_dev->dev_id, sensor->name, value);
 375                         continue;
 376                 }
 377
 378                 /* monitor temperature sensors */
 379                 if (!strcmp(sensor->name, "Board Temperature") ||
 380                                 !strcmp(sensor->name, "FPGA Die Temperature")) {
 381                         IFPGA_RAWDEV_PMD_INFO("read sensor %s %d %d %d\n",
 382                                         sensor->name, value, sensor->high_warn,
 383                                         sensor->high_fatal);
 384
 385                         if (HIGH_WARN(sensor, value) ||
 386                                 LOW_WARN(sensor, value)) {
 387                                 IFPGA_RAWDEV_PMD_INFO("%s reach theshold %d\n",
 388                                         sensor->name, value);
 389                                 *gsd_start = true;
 390                                 break;
 391                         }
 392                 }
 393
 394                 /* monitor 12V AUX sensor */
 395                 if (!strcmp(sensor->name, "12V AUX Voltage")) {
 396                         if (value < AUX_VOLTAGE_WARN) {
 397                                 IFPGA_RAWDEV_PMD_INFO(
 398                                         "%s reach theshold %d mV\n",
 399                                         sensor->name, value);
 400                                 *gsd_start = true;
 401                                 break;
 402                         }
 403                 }
 404         }
 405
 406         return 0;
 407 fail:
 408         return -EFAULT;
 409 }
 410
 411 static int set_surprise_link_check_aer(
 412         struct ifpga_rawdev *ifpga_rdev, int force_disable)
 413 {
 414         struct rte_rawdev *rdev;
 415         int fd = -1;
 416         char path[1024];
 417         int pos;
 418         int ret;
 419         uint32_t data;
 420         bool enable = 0;
 421         uint32_t aer_new0, aer_new1;
 422
 423         if (!ifpga_rdev) {
 424                 printf("\n device does not exist\n");
 425                 return -EFAULT;
 426         }
 427
 428         rdev = ifpga_rdev->rawdev;
 429         if (ifpga_rdev->aer_enable)
 430                 return -EFAULT;
 431         if (ifpga_monitor_sensor(rdev, &enable))
 432                 return -EFAULT;
 433         if (enable || force_disable) {
 434                 IFPGA_RAWDEV_PMD_ERR("Set AER, pls graceful shutdown\n");
 435                 ifpga_rdev->aer_enable = 1;
 436                 /* get bridge fd */
 437                 strlcpy(path, "/sys/bus/pci/devices/", sizeof(path));
 438                 strlcat(path, ifpga_rdev->parent_bdf, sizeof(path));
 439                 strlcat(path, "/config", sizeof(path));
 440                 fd = open(path, O_RDWR);
 441                 if (fd < 0)
 442                         goto end;
 443                 pos = ifpga_pci_find_ext_capability(fd, RTE_PCI_EXT_CAP_ID_ERR);
 444                 if (!pos)
 445                         goto end;
 446                 /* save previout ECAP_AER+0x08 */
 447                 ret = pread(fd, &data, sizeof(data), pos+0x08);
 448                 if (ret == -1)
 449                         goto end;
 450                 ifpga_rdev->aer_old[0] = data;
 451                 /* save previout ECAP_AER+0x14 */
 452                 ret = pread(fd, &data, sizeof(data), pos+0x14);
 453                 if (ret == -1)
 454                         goto end;
 455                 ifpga_rdev->aer_old[1] = data;
 456
 457                 /* set ECAP_AER+0x08 to 0xFFFFFFFF */
 458                 data = 0xffffffff;
 459                 ret = pwrite(fd, &data, 4, pos+0x08);
 460                 if (ret == -1)
 461                         goto end;
 462                 /* set ECAP_AER+0x14 to 0xFFFFFFFF */
 463                 ret = pwrite(fd, &data, 4, pos+0x14);
 464                 if (ret == -1)
 465                         goto end;
 466
 467                 /* read current ECAP_AER+0x08 */
 468                 ret = pread(fd, &data, sizeof(data), pos+0x08);
 469                 if (ret == -1)
 470                         goto end;
 471                 aer_new0 = data;
 472                 /* read current ECAP_AER+0x14 */
 473                 ret = pread(fd, &data, sizeof(data), pos+0x14);
 474                 if (ret == -1)
 475                         goto end;
 476                 aer_new1 = data;
 477
 478                 if (fd != -1)
 479                         close(fd);
 480
 481                 printf(">>>>>>Set AER %x,%x %x,%x\n",
 482                         ifpga_rdev->aer_old[0], ifpga_rdev->aer_old[1],
 483                         aer_new0, aer_new1);
 484
 485                 return 1;
 486                 }
 487
 488 end:
 489         if (fd != -1)
 490                 close(fd);
 491         return -EFAULT;
 492 }
 493
 494 static void *
 495 ifpga_rawdev_gsd_handle(__rte_unused void *param)
 496 {
 497         struct ifpga_rawdev *ifpga_rdev;
 498         int i;
 499         int gsd_enable, ret;
 500 #define MS 1000
 501
 502         while (1) {
 503                 gsd_enable = 0;
 504                 for (i = 0; i < IFPGA_RAWDEV_NUM; i++) {
 505                         ifpga_rdev = &ifpga_rawdevices[i];
 506                         if (ifpga_rdev->rawdev) {
 507                                 ret = set_surprise_link_check_aer(ifpga_rdev,
 508                                         gsd_enable);
 509                                 if (ret == 1 && !gsd_enable) {
 510                                         gsd_enable = 1;
 511                                         i = -1;
 512                                 }
 513                         }
 514                 }
 515
 516                 if (gsd_enable)
 517                         printf(">>>>>>Pls Shutdown APP\n");
 518
 519                 rte_delay_us(100 * MS);
 520         }
 521
 522         return NULL;
 523 }
 524
 525 static int
 526 ifpga_monitor_start_func(void)
 527 {
 528         int ret;
 529
 530         if (ifpga_monitor_start == 0) {
 531                 ret = pthread_create(&ifpga_monitor_start_thread,
 532                         NULL,
 533                         ifpga_rawdev_gsd_handle, NULL);
 534                 if (ret) {
 535                         IFPGA_RAWDEV_PMD_ERR(
 536                                 "Fail to create ifpga nonitor thread");
 537                         return -1;
 538                 }
 539                 ifpga_monitor_start = 1;
 540         }
 541
 542         return 0;
 543 }
 544 static int
 545 ifpga_monitor_stop_func(void)
 546 {
 547         int ret;
 548
 549         if (ifpga_monitor_start == 1) {
 550                 ret = pthread_cancel(ifpga_monitor_start_thread);
 551                 if (ret)
 552                         IFPGA_RAWDEV_PMD_ERR("Can't cancel the thread");
 553
 554                 ret = pthread_join(ifpga_monitor_start_thread, NULL);
 555                 if (ret)
 556                         IFPGA_RAWDEV_PMD_ERR("Can't join the thread");
 557
 558                 ifpga_monitor_start = 0;
 559
 560                 return ret;
 561         }
 562
 563         return 0;
 564 }
 565
 566 static int
 567 ifpga_fill_afu_dev(struct opae_accelerator *acc,
 568                 struct rte_afu_device *afu_dev)
 569 {
 570         struct rte_mem_resource *res = afu_dev->mem_resource;
 571         struct opae_acc_region_info region_info;
 572         struct opae_acc_info info;
 573         unsigned long i;
 574         int ret;
 575
 576         ret = opae_acc_get_info(acc, &info);
 577         if (ret)
 578                 return ret;
 579
 580         if (info.num_regions > PCI_MAX_RESOURCE)
 581                 return -EFAULT;
 582
 583         afu_dev->num_region = info.num_regions;
 584
 585         for (i = 0; i < info.num_regions; i++) {
 586                 region_info.index = i;
 587                 ret = opae_acc_get_region_info(acc, &region_info);
 588                 if (ret)
 589                         return ret;
 590
 591                 if ((region_info.flags & ACC_REGION_MMIO) &&
 592                     (region_info.flags & ACC_REGION_READ) &&
 593                     (region_info.flags & ACC_REGION_WRITE)) {
 594                         res[i].phys_addr = region_info.phys_addr;
 595                         res[i].len = region_info.len;
 596                         res[i].addr = region_info.addr;
 597                 } else
 598                         return -EFAULT;
 599         }
 600
 601         return 0;
 602 }
 603
 604 static void
 605 ifpga_rawdev_info_get(struct rte_rawdev *dev,
 606                                      rte_rawdev_obj_t dev_info)
 607 {
 608         struct opae_adapter *adapter;
 609         struct opae_accelerator *acc;
 610         struct rte_afu_device *afu_dev;
 611         struct opae_manager *mgr = NULL;
 612         struct opae_eth_group_region_info opae_lside_eth_info;
 613         struct opae_eth_group_region_info opae_nside_eth_info;
 614         int lside_bar_idx, nside_bar_idx;
 615
 616         IFPGA_RAWDEV_PMD_FUNC_TRACE();
 617
 618         if (!dev_info) {
 619                 IFPGA_RAWDEV_PMD_ERR("Invalid request");
 620                 return;
 621         }
 622
 623         adapter = ifpga_rawdev_get_priv(dev);
 624         if (!adapter)
 625                 return;
 626
 627         afu_dev = dev_info;
 628         afu_dev->rawdev = dev;
 629
 630         /* find opae_accelerator and fill info into afu_device */
 631         opae_adapter_for_each_acc(adapter, acc) {
 632                 if (acc->index != afu_dev->id.port)
 633                         continue;
 634
 635                 if (ifpga_fill_afu_dev(acc, afu_dev)) {
 636                         IFPGA_RAWDEV_PMD_ERR("cannot get info\n");
 637                         return;
 638                 }
 639         }
 640
 641         /* get opae_manager to rawdev */
 642         mgr = opae_adapter_get_mgr(adapter);
 643         if (mgr) {
 644                 /* get LineSide BAR Index */
 645                 if (opae_manager_get_eth_group_region_info(mgr, 0,
 646                         &opae_lside_eth_info)) {
 647                         return;
 648                 }
 649                 lside_bar_idx = opae_lside_eth_info.mem_idx;
 650
 651                 /* get NICSide BAR Index */
 652                 if (opae_manager_get_eth_group_region_info(mgr, 1,
 653                         &opae_nside_eth_info)) {
 654                         return;
 655                 }
 656                 nside_bar_idx = opae_nside_eth_info.mem_idx;
 657
 658                 if (lside_bar_idx >= PCI_MAX_RESOURCE ||
 659                         nside_bar_idx >= PCI_MAX_RESOURCE ||
 660                         lside_bar_idx == nside_bar_idx)
 661                         return;
 662
 663                 /* fill LineSide BAR Index */
 664                 afu_dev->mem_resource[lside_bar_idx].phys_addr =
 665                         opae_lside_eth_info.phys_addr;
 666                 afu_dev->mem_resource[lside_bar_idx].len =
 667                         opae_lside_eth_info.len;
 668                 afu_dev->mem_resource[lside_bar_idx].addr =
 669                         opae_lside_eth_info.addr;
 670
 671                 /* fill NICSide BAR Index */
 672                 afu_dev->mem_resource[nside_bar_idx].phys_addr =
 673                         opae_nside_eth_info.phys_addr;
 674                 afu_dev->mem_resource[nside_bar_idx].len =
 675                         opae_nside_eth_info.len;
 676                 afu_dev->mem_resource[nside_bar_idx].addr =
 677                         opae_nside_eth_info.addr;
 678         }
 679 }
 680
 681 static int
 682 ifpga_rawdev_configure(const struct rte_rawdev *dev,
 683                 rte_rawdev_obj_t config)
 684 {
 685         IFPGA_RAWDEV_PMD_FUNC_TRACE();
 686
 687         RTE_FUNC_PTR_OR_ERR_RET(dev, -EINVAL);
 688
 689         return config ? 0 : 1;
 690 }
 691
 692 static int
 693 ifpga_rawdev_start(struct rte_rawdev *dev)
 694 {
 695         int ret = 0;
 696         struct opae_adapter *adapter;
 697
 698         IFPGA_RAWDEV_PMD_FUNC_TRACE();
 699
 700         RTE_FUNC_PTR_OR_ERR_RET(dev, -EINVAL);
 701
 702         adapter = ifpga_rawdev_get_priv(dev);
 703         if (!adapter)
 704                 return -ENODEV;
 705
 706         return ret;
 707 }
 708
 709 static void
 710 ifpga_rawdev_stop(struct rte_rawdev *dev)
 711 {
 712         dev->started = 0;
 713 }
 714
 715 static int
 716 ifpga_rawdev_close(struct rte_rawdev *dev)
 717 {
 718         return dev ? 0:1;
 719 }
 720
 721 static int
 722 ifpga_rawdev_reset(struct rte_rawdev *dev)
 723 {
 724         return dev ? 0:1;
 725 }
 726
 727 static int
 728 fpga_pr(struct rte_rawdev *raw_dev, u32 port_id, const char *buffer, u32 size,
 729                         u64 *status)
 730 {
 731
 732         struct opae_adapter *adapter;
 733         struct opae_manager *mgr;
 734         struct opae_accelerator *acc;
 735         struct opae_bridge *br;
 736         int ret;
 737
 738         adapter = ifpga_rawdev_get_priv(raw_dev);
 739         if (!adapter)
 740                 return -ENODEV;
 741
 742         mgr = opae_adapter_get_mgr(adapter);
 743         if (!mgr)
 744                 return -ENODEV;
 745
 746         acc = opae_adapter_get_acc(adapter, port_id);
 747         if (!acc)
 748                 return -ENODEV;
 749
 750         br = opae_acc_get_br(acc);
 751         if (!br)
 752                 return -ENODEV;
 753
 754         ret = opae_manager_flash(mgr, port_id, buffer, size, status);
 755         if (ret) {
 756                 IFPGA_RAWDEV_PMD_ERR("%s pr error %d\n", __func__, ret);
 757                 return ret;
 758         }
 759
 760         ret = opae_bridge_reset(br);
 761         if (ret) {
 762                 IFPGA_RAWDEV_PMD_ERR("%s reset port:%d error %d\n",
 763                                 __func__, port_id, ret);
 764                 return ret;
 765         }
 766
 767         return ret;
 768 }
 769
 770 static int
 771 rte_fpga_do_pr(struct rte_rawdev *rawdev, int port_id,
 772                 const char *file_name)
 773 {
 774         struct stat file_stat;
 775         int file_fd;
 776         int ret = 0;
 777         ssize_t buffer_size;
 778         void *buffer;
 779         u64 pr_error;
 780
 781         if (!file_name)
 782                 return -EINVAL;
 783
 784         file_fd = open(file_name, O_RDONLY);
 785         if (file_fd < 0) {
 786                 IFPGA_RAWDEV_PMD_ERR("%s: open file error: %s\n",
 787                                 __func__, file_name);
 788                 IFPGA_RAWDEV_PMD_ERR("Message : %s\n", strerror(errno));
 789                 return -EINVAL;
 790         }
 791         ret = stat(file_name, &file_stat);
 792         if (ret) {
 793                 IFPGA_RAWDEV_PMD_ERR("stat on bitstream file failed: %s\n",
 794                                 file_name);
 795                 ret = -EINVAL;
 796                 goto close_fd;
 797         }
 798         buffer_size = file_stat.st_size;
 799         if (buffer_size <= 0) {
 800                 ret = -EINVAL;
 801                 goto close_fd;
 802         }
 803
 804         IFPGA_RAWDEV_PMD_INFO("bitstream file size: %zu\n", buffer_size);
 805         buffer = rte_malloc(NULL, buffer_size, 0);
 806         if (!buffer) {
 807                 ret = -ENOMEM;
 808                 goto close_fd;
 809         }
 810
 811         /*read the raw data*/
 812         if (buffer_size != read(file_fd, (void *)buffer, buffer_size)) {
 813                 ret = -EINVAL;
 814                 goto free_buffer;
 815         }
 816
 817         /*do PR now*/
 818         ret = fpga_pr(rawdev, port_id, buffer, buffer_size, &pr_error);
 819         IFPGA_RAWDEV_PMD_INFO("downloading to device port %d....%s.\n", port_id,
 820                 ret ? "failed" : "success");
 821         if (ret) {
 822                 ret = -EINVAL;
 823                 goto free_buffer;
 824         }
 825
 826 free_buffer:
 827         if (buffer)
 828                 rte_free(buffer);
 829 close_fd:
 830         close(file_fd);
 831         file_fd = 0;
 832         return ret;
 833 }
 834
 835 static int
 836 ifpga_rawdev_pr(struct rte_rawdev *dev,
 837         rte_rawdev_obj_t pr_conf)
 838 {
 839         struct opae_adapter *adapter;
 840         struct opae_manager *mgr;
 841         struct opae_board_info *info;
 842         struct rte_afu_pr_conf *afu_pr_conf;
 843         int ret;
 844         struct uuid uuid;
 845         struct opae_accelerator *acc;
 846
 847         IFPGA_RAWDEV_PMD_FUNC_TRACE();
 848
 849         adapter = ifpga_rawdev_get_priv(dev);
 850         if (!adapter)
 851                 return -ENODEV;
 852
 853         if (!pr_conf)
 854                 return -EINVAL;
 855
 856         afu_pr_conf = pr_conf;
 857
 858         if (afu_pr_conf->pr_enable) {
 859                 ret = rte_fpga_do_pr(dev,
 860                                 afu_pr_conf->afu_id.port,
 861                                 afu_pr_conf->bs_path);
 862                 if (ret) {
 863                         IFPGA_RAWDEV_PMD_ERR("do pr error %d\n", ret);
 864                         return ret;
 865                 }
 866         }
 867
 868         mgr = opae_adapter_get_mgr(adapter);
 869         if (!mgr) {
 870                 IFPGA_RAWDEV_PMD_ERR("opae_manager of opae_adapter is NULL");
 871                 return -1;
 872         }
 873
 874         if (ifpga_mgr_ops.get_board_info(mgr, &info)) {
 875                 IFPGA_RAWDEV_PMD_ERR("ifpga manager get_board_info fail!");
 876                 return -1;
 877         }
 878
 879         if (info->lightweight) {
 880                 /* set uuid to all 0, when fpga is lightweight image */
 881                 memset(&afu_pr_conf->afu_id.uuid.uuid_low, 0, sizeof(u64));
 882                 memset(&afu_pr_conf->afu_id.uuid.uuid_high, 0, sizeof(u64));
 883         } else {
 884                 acc = opae_adapter_get_acc(adapter, afu_pr_conf->afu_id.port);
 885                 if (!acc)
 886                         return -ENODEV;
 887
 888                 ret = opae_acc_get_uuid(acc, &uuid);
 889                 if (ret)
 890                         return ret;
 891
 892                 rte_memcpy(&afu_pr_conf->afu_id.uuid.uuid_low, uuid.b,
 893                         sizeof(u64));
 894                 rte_memcpy(&afu_pr_conf->afu_id.uuid.uuid_high, uuid.b + 8,
 895                         sizeof(u64));
 896
 897                 IFPGA_RAWDEV_PMD_INFO("%s: uuid_l=0x%lx, uuid_h=0x%lx\n",
 898                         __func__,
 899                         (unsigned long)afu_pr_conf->afu_id.uuid.uuid_low,
 900                         (unsigned long)afu_pr_conf->afu_id.uuid.uuid_high);
 901                 }
 902         return 0;
 903 }
 904
 905 static int
 906 ifpga_rawdev_get_attr(struct rte_rawdev *dev,
 907         const char *attr_name, uint64_t *attr_value)
 908 {
 909         struct opae_adapter *adapter;
 910         struct opae_manager *mgr;
 911         struct opae_retimer_info opae_rtm_info;
 912         struct opae_retimer_status opae_rtm_status;
 913         struct opae_eth_group_info opae_eth_grp_info;
 914         struct opae_eth_group_region_info opae_eth_grp_reg_info;
 915         int eth_group_num = 0;
 916         uint64_t port_link_bitmap = 0, port_link_bit;
 917         uint32_t i, j, p, q;
 918
 919 #define MAX_PORT_PER_RETIMER    4
 920
 921         IFPGA_RAWDEV_PMD_FUNC_TRACE();
 922
 923         if (!dev || !attr_name || !attr_value) {
 924                 IFPGA_RAWDEV_PMD_ERR("Invalid arguments for getting attributes");
 925                 return -1;
 926         }
 927
 928         adapter = ifpga_rawdev_get_priv(dev);
 929         if (!adapter) {
 930                 IFPGA_RAWDEV_PMD_ERR("Adapter of dev %s is NULL", dev->name);
 931                 return -1;
 932         }
 933
 934         mgr = opae_adapter_get_mgr(adapter);
 935         if (!mgr) {
 936                 IFPGA_RAWDEV_PMD_ERR("opae_manager of opae_adapter is NULL");
 937                 return -1;
 938         }
 939
 940         /* currently, eth_group_num is always 2 */
 941         eth_group_num = opae_manager_get_eth_group_nums(mgr);
 942         if (eth_group_num < 0)
 943                 return -1;
 944
 945         if (!strcmp(attr_name, "LineSideBaseMAC")) {
 946                 /* Currently FPGA not implement, so just set all zeros*/
 947                 *attr_value = (uint64_t)0;
 948                 return 0;
 949         }
 950         if (!strcmp(attr_name, "LineSideMACType")) {
 951                 /* eth_group 0 on FPGA connect to LineSide */
 952                 if (opae_manager_get_eth_group_info(mgr, 0,
 953                         &opae_eth_grp_info))
 954                         return -1;
 955                 switch (opae_eth_grp_info.speed) {
 956                 case ETH_SPEED_10G:
 957                         *attr_value =
 958                         (uint64_t)(IFPGA_RAWDEV_RETIMER_MAC_TYPE_10GE_XFI);
 959                         break;
 960                 case ETH_SPEED_25G:
 961                         *attr_value =
 962                         (uint64_t)(IFPGA_RAWDEV_RETIMER_MAC_TYPE_25GE_25GAUI);
 963                         break;
 964                 default:
 965                         *attr_value =
 966                         (uint64_t)(IFPGA_RAWDEV_RETIMER_MAC_TYPE_UNKNOWN);
 967                         break;
 968                 }
 969                 return 0;
 970         }
 971         if (!strcmp(attr_name, "LineSideLinkSpeed")) {
 972                 if (opae_manager_get_retimer_status(mgr, &opae_rtm_status))
 973                         return -1;
 974                 switch (opae_rtm_status.speed) {
 975                 case MXD_1GB:
 976                         *attr_value =
 977                                 (uint64_t)(IFPGA_RAWDEV_LINK_SPEED_UNKNOWN);
 978                         break;
 979                 case MXD_2_5GB:
 980                         *attr_value =
 981                                 (uint64_t)(IFPGA_RAWDEV_LINK_SPEED_UNKNOWN);
 982                         break;
 983                 case MXD_5GB:
 984                         *attr_value =
 985                                 (uint64_t)(IFPGA_RAWDEV_LINK_SPEED_UNKNOWN);
 986                         break;
 987                 case MXD_10GB:
 988                         *attr_value =
 989                                 (uint64_t)(IFPGA_RAWDEV_LINK_SPEED_10GB);
 990                         break;
 991                 case MXD_25GB:
 992                         *attr_value =
 993                                 (uint64_t)(IFPGA_RAWDEV_LINK_SPEED_25GB);
 994                         break;
 995                 case MXD_40GB:
 996                         *attr_value =
 997                                 (uint64_t)(IFPGA_RAWDEV_LINK_SPEED_40GB);
 998                         break;
 999                 case MXD_100GB:
1000                         *attr_value =
1001                                 (uint64_t)(IFPGA_RAWDEV_LINK_SPEED_UNKNOWN);
1002                         break;
1003                 case MXD_SPEED_UNKNOWN:
1004                         *attr_value =
1005                                 (uint64_t)(IFPGA_RAWDEV_LINK_SPEED_UNKNOWN);
1006                         break;
1007                 default:
1008                         *attr_value =
1009                                 (uint64_t)(IFPGA_RAWDEV_LINK_SPEED_UNKNOWN);
1010                         break;
1011                 }
1012                 return 0;
1013         }
1014         if (!strcmp(attr_name, "LineSideLinkRetimerNum")) {
1015                 if (opae_manager_get_retimer_info(mgr, &opae_rtm_info))
1016                         return -1;
1017                 *attr_value = (uint64_t)(opae_rtm_info.nums_retimer);
1018                 return 0;
1019         }
1020         if (!strcmp(attr_name, "LineSideLinkPortNum")) {
1021                 if (opae_manager_get_retimer_info(mgr, &opae_rtm_info))
1022                         return -1;
1023                 uint64_t tmp = (uint64_t)opae_rtm_info.ports_per_retimer *
1024                                         (uint64_t)opae_rtm_info.nums_retimer;
1025                 *attr_value = tmp;
1026                 return 0;
1027         }
1028         if (!strcmp(attr_name, "LineSideLinkStatus")) {
1029                 if (opae_manager_get_retimer_info(mgr, &opae_rtm_info))
1030                         return -1;
1031                 if (opae_manager_get_retimer_status(mgr, &opae_rtm_status))
1032                         return -1;
1033                 (*attr_value) = 0;
1034                 q = 0;
1035                 port_link_bitmap = (uint64_t)(opae_rtm_status.line_link_bitmap);
1036                 for (i = 0; i < opae_rtm_info.nums_retimer; i++) {
1037                         p = i * MAX_PORT_PER_RETIMER;
1038                         for (j = 0; j < opae_rtm_info.ports_per_retimer; j++) {
1039                                 port_link_bit = 0;
1040                                 IFPGA_BIT_SET(port_link_bit, (p+j));
1041                                 port_link_bit &= port_link_bitmap;
1042                                 if (port_link_bit)
1043                                         IFPGA_BIT_SET((*attr_value), q);
1044                                 q++;
1045                         }
1046                 }
1047                 return 0;
1048         }
1049         if (!strcmp(attr_name, "LineSideBARIndex")) {
1050                 /* eth_group 0 on FPGA connect to LineSide */
1051                 if (opae_manager_get_eth_group_region_info(mgr, 0,
1052                         &opae_eth_grp_reg_info))
1053                         return -1;
1054                 *attr_value = (uint64_t)opae_eth_grp_reg_info.mem_idx;
1055                 return 0;
1056         }
1057         if (!strcmp(attr_name, "NICSideMACType")) {
1058                 /* eth_group 1 on FPGA connect to NicSide */
1059                 if (opae_manager_get_eth_group_info(mgr, 1,
1060                         &opae_eth_grp_info))
1061                         return -1;
1062                 *attr_value = (uint64_t)(opae_eth_grp_info.speed);
1063                 return 0;
1064         }
1065         if (!strcmp(attr_name, "NICSideLinkSpeed")) {
1066                 /* eth_group 1 on FPGA connect to NicSide */
1067                 if (opae_manager_get_eth_group_info(mgr, 1,
1068                         &opae_eth_grp_info))
1069                         return -1;
1070                 *attr_value = (uint64_t)(opae_eth_grp_info.speed);
1071                 return 0;
1072         }
1073         if (!strcmp(attr_name, "NICSideLinkPortNum")) {
1074                 if (opae_manager_get_retimer_info(mgr, &opae_rtm_info))
1075                         return -1;
1076                 uint64_t tmp = (uint64_t)opae_rtm_info.nums_fvl *
1077                                         (uint64_t)opae_rtm_info.ports_per_fvl;
1078                 *attr_value = tmp;
1079                 return 0;
1080         }
1081         if (!strcmp(attr_name, "NICSideLinkStatus"))
1082                 return 0;
1083         if (!strcmp(attr_name, "NICSideBARIndex")) {
1084                 /* eth_group 1 on FPGA connect to NicSide */
1085                 if (opae_manager_get_eth_group_region_info(mgr, 1,
1086                         &opae_eth_grp_reg_info))
1087                         return -1;
1088                 *attr_value = (uint64_t)opae_eth_grp_reg_info.mem_idx;
1089                 return 0;
1090         }
1091
1092         IFPGA_RAWDEV_PMD_ERR("%s not support", attr_name);
1093         return -1;
1094 }
1095
1096 static const struct rte_rawdev_ops ifpga_rawdev_ops = {
1097         .dev_info_get = ifpga_rawdev_info_get,
1098         .dev_configure = ifpga_rawdev_configure,
1099         .dev_start = ifpga_rawdev_start,
1100         .dev_stop = ifpga_rawdev_stop,
1101         .dev_close = ifpga_rawdev_close,
1102         .dev_reset = ifpga_rawdev_reset,
1103
1104         .queue_def_conf = NULL,
1105         .queue_setup = NULL,
1106         .queue_release = NULL,
1107
1108         .attr_get = ifpga_rawdev_get_attr,
1109         .attr_set = NULL,
1110
1111         .enqueue_bufs = NULL,
1112         .dequeue_bufs = NULL,
1113
1114         .dump = NULL,
1115
1116         .xstats_get = NULL,
1117         .xstats_get_names = NULL,
1118         .xstats_get_by_name = NULL,
1119         .xstats_reset = NULL,
1120
1121         .firmware_status_get = NULL,
1122         .firmware_version_get = NULL,
1123         .firmware_load = ifpga_rawdev_pr,
1124         .firmware_unload = NULL,
1125
1126         .dev_selftest = NULL,
1127 };
1128
1129 static int
1130 ifpga_get_fme_error_prop(struct opae_manager *mgr,
1131                 u64 prop_id, u64 *val)
1132 {
1133         struct feature_prop prop;
1134
1135         prop.feature_id = IFPGA_FME_FEATURE_ID_GLOBAL_ERR;
1136         prop.prop_id = prop_id;
1137
1138         if (opae_manager_ifpga_get_prop(mgr, &prop))
1139                 return -EINVAL;
1140
1141         *val = prop.data;
1142
1143         return 0;
1144 }
1145
1146 static int
1147 ifpga_set_fme_error_prop(struct opae_manager *mgr,
1148                 u64 prop_id, u64 val)
1149 {
1150         struct feature_prop prop;
1151
1152         prop.feature_id = IFPGA_FME_FEATURE_ID_GLOBAL_ERR;
1153         prop.prop_id = prop_id;
1154
1155         prop.data = val;
1156
1157         if (opae_manager_ifpga_set_prop(mgr, &prop))
1158                 return -EINVAL;
1159
1160         return 0;
1161 }
1162
1163 static int
1164 fme_err_read_seu_emr(struct opae_manager *mgr)
1165 {
1166         u64 val;
1167         int ret;
1168
1169         ret = ifpga_get_fme_error_prop(mgr, FME_ERR_PROP_SEU_EMR_LOW, &val);
1170         if (ret)
1171                 return -EINVAL;
1172
1173         IFPGA_RAWDEV_PMD_INFO("seu emr low: 0x%" PRIx64 "\n", val);
1174
1175         ret = ifpga_get_fme_error_prop(mgr, FME_ERR_PROP_SEU_EMR_HIGH, &val);
1176         if (ret)
1177                 return -EINVAL;
1178
1179         IFPGA_RAWDEV_PMD_INFO("seu emr high: 0x%" PRIx64 "\n", val);
1180
1181         return 0;
1182 }
1183
1184 static int fme_clear_warning_intr(struct opae_manager *mgr)
1185 {
1186         u64 val;
1187
1188         if (ifpga_set_fme_error_prop(mgr, FME_ERR_PROP_INJECT_ERRORS, 0))
1189                 return -EINVAL;
1190
1191         if (ifpga_get_fme_error_prop(mgr, FME_ERR_PROP_NONFATAL_ERRORS, &val))
1192                 return -EINVAL;
1193         if ((val & 0x40) != 0)
1194                 IFPGA_RAWDEV_PMD_INFO("clean not done\n");
1195
1196         return 0;
1197 }
1198
1199 static int fme_clean_fme_error(struct opae_manager *mgr)
1200 {
1201         u64 val;
1202
1203         if (ifpga_get_fme_error_prop(mgr, FME_ERR_PROP_ERRORS, &val))
1204                 return -EINVAL;
1205
1206         IFPGA_RAWDEV_PMD_DEBUG("before clean 0x%" PRIx64 "\n", val);
1207
1208         ifpga_set_fme_error_prop(mgr, FME_ERR_PROP_CLEAR, val);
1209
1210         if (ifpga_get_fme_error_prop(mgr, FME_ERR_PROP_ERRORS, &val))
1211                 return -EINVAL;
1212
1213         IFPGA_RAWDEV_PMD_DEBUG("after clean 0x%" PRIx64 "\n", val);
1214
1215         return 0;
1216 }
1217
1218 static int
1219 fme_err_handle_error0(struct opae_manager *mgr)
1220 {
1221         struct feature_fme_error0 fme_error0;
1222         u64 val;
1223
1224         if (ifpga_get_fme_error_prop(mgr, FME_ERR_PROP_ERRORS, &val))
1225                 return -EINVAL;
1226
1227         if (fme_clean_fme_error(mgr))
1228                 return -EINVAL;
1229
1230         fme_error0.csr = val;
1231
1232         if (fme_error0.fabric_err)
1233                 IFPGA_RAWDEV_PMD_ERR("Fabric error\n");
1234         else if (fme_error0.fabfifo_overflow)
1235                 IFPGA_RAWDEV_PMD_ERR("Fabric fifo under/overflow error\n");
1236         else if (fme_error0.afu_acc_mode_err)
1237                 IFPGA_RAWDEV_PMD_ERR("AFU PF/VF access mismatch detected\n");
1238         else if (fme_error0.pcie0cdc_parity_err)
1239                 IFPGA_RAWDEV_PMD_ERR("PCIe0 CDC Parity Error\n");
1240         else if (fme_error0.cvlcdc_parity_err)
1241                 IFPGA_RAWDEV_PMD_ERR("CVL CDC Parity Error\n");
1242         else if (fme_error0.fpgaseuerr)
1243                 fme_err_read_seu_emr(mgr);
1244
1245         /* clean the errors */
1246         if (ifpga_set_fme_error_prop(mgr, FME_ERR_PROP_ERRORS, val))
1247                 return -EINVAL;
1248
1249         return 0;
1250 }
1251
1252 static int
1253 fme_err_handle_catfatal_error(struct opae_manager *mgr)
1254 {
1255         struct feature_fme_ras_catfaterror fme_catfatal;
1256         u64 val;
1257
1258         if (ifpga_get_fme_error_prop(mgr, FME_ERR_PROP_CATFATAL_ERRORS, &val))
1259                 return -EINVAL;
1260
1261         fme_catfatal.csr = val;
1262
1263         if (fme_catfatal.cci_fatal_err)
1264                 IFPGA_RAWDEV_PMD_ERR("CCI error detected\n");
1265         else if (fme_catfatal.fabric_fatal_err)
1266                 IFPGA_RAWDEV_PMD_ERR("Fabric fatal error detected\n");
1267         else if (fme_catfatal.pcie_poison_err)
1268                 IFPGA_RAWDEV_PMD_ERR("Poison error from PCIe ports\n");
1269         else if (fme_catfatal.inject_fata_err)
1270                 IFPGA_RAWDEV_PMD_ERR("Injected Fatal Error\n");
1271         else if (fme_catfatal.crc_catast_err)
1272                 IFPGA_RAWDEV_PMD_ERR("a catastrophic EDCRC error\n");
1273         else if (fme_catfatal.injected_catast_err)
1274                 IFPGA_RAWDEV_PMD_ERR("Injected Catastrophic Error\n");
1275         else if (fme_catfatal.bmc_seu_catast_err)
1276                 fme_err_read_seu_emr(mgr);
1277
1278         return 0;
1279 }
1280
1281 static int
1282 fme_err_handle_nonfaterror(struct opae_manager *mgr)
1283 {
1284         struct feature_fme_ras_nonfaterror nonfaterr;
1285         u64 val;
1286
1287         if (ifpga_get_fme_error_prop(mgr, FME_ERR_PROP_NONFATAL_ERRORS, &val))
1288                 return -EINVAL;
1289
1290         nonfaterr.csr = val;
1291
1292         if (nonfaterr.temp_thresh_ap1)
1293                 IFPGA_RAWDEV_PMD_INFO("Temperature threshold triggered AP1\n");
1294         else if (nonfaterr.temp_thresh_ap2)
1295                 IFPGA_RAWDEV_PMD_INFO("Temperature threshold triggered AP2\n");
1296         else if (nonfaterr.pcie_error)
1297                 IFPGA_RAWDEV_PMD_INFO("an error has occurred in pcie\n");
1298         else if (nonfaterr.portfatal_error)
1299                 IFPGA_RAWDEV_PMD_INFO("fatal error occurred in AFU port.\n");
1300         else if (nonfaterr.proc_hot)
1301                 IFPGA_RAWDEV_PMD_INFO("a ProcHot event\n");
1302         else if (nonfaterr.afu_acc_mode_err)
1303                 IFPGA_RAWDEV_PMD_INFO("an AFU PF/VF access mismatch\n");
1304         else if (nonfaterr.injected_nonfata_err) {
1305                 IFPGA_RAWDEV_PMD_INFO("Injected Warning Error\n");
1306                 fme_clear_warning_intr(mgr);
1307         } else if (nonfaterr.temp_thresh_AP6)
1308                 IFPGA_RAWDEV_PMD_INFO("Temperature threshold triggered AP6\n");
1309         else if (nonfaterr.power_thresh_AP1)
1310                 IFPGA_RAWDEV_PMD_INFO("Power threshold triggered AP1\n");
1311         else if (nonfaterr.power_thresh_AP2)
1312                 IFPGA_RAWDEV_PMD_INFO("Power threshold triggered AP2\n");
1313         else if (nonfaterr.mbp_err)
1314                 IFPGA_RAWDEV_PMD_INFO("an MBP event\n");
1315
1316         return 0;
1317 }
1318
1319 static void
1320 fme_interrupt_handler(void *param)
1321 {
1322         struct opae_manager *mgr = (struct opae_manager *)param;
1323
1324         IFPGA_RAWDEV_PMD_INFO("%s interrupt occurred\n", __func__);
1325
1326         fme_err_handle_error0(mgr);
1327         fme_err_handle_nonfaterror(mgr);
1328         fme_err_handle_catfatal_error(mgr);
1329 }
1330
1331 static struct rte_intr_handle fme_intr_handle;
1332
1333 static int ifpga_register_fme_interrupt(struct opae_manager *mgr)
1334 {
1335         int ret;
1336         struct fpga_fme_err_irq_set err_irq_set;
1337
1338         fme_intr_handle.type = RTE_INTR_HANDLE_VFIO_MSIX;
1339
1340         ret = rte_intr_efd_enable(&fme_intr_handle, 1);
1341         if (ret)
1342                 return -EINVAL;
1343
1344         fme_intr_handle.fd = fme_intr_handle.efds[0];
1345
1346         IFPGA_RAWDEV_PMD_DEBUG("vfio_dev_fd=%d, efd=%d, fd=%d\n",
1347                         fme_intr_handle.vfio_dev_fd,
1348                         fme_intr_handle.efds[0], fme_intr_handle.fd);
1349
1350         err_irq_set.evtfd = fme_intr_handle.efds[0];
1351         ret = opae_manager_ifpga_set_err_irq(mgr, &err_irq_set);
1352         if (ret)
1353                 return -EINVAL;
1354
1355         /* register FME interrupt using DPDK API */
1356         ret = rte_intr_callback_register(&fme_intr_handle,
1357                         fme_interrupt_handler,
1358                         (void *)mgr);
1359         if (ret)
1360                 return -EINVAL;
1361
1362         IFPGA_RAWDEV_PMD_INFO("success register fme interrupt\n");
1363
1364         return 0;
1365 }
1366
1367 static int
1368 ifpga_unregister_fme_interrupt(struct opae_manager *mgr)
1369 {
1370         rte_intr_efd_disable(&fme_intr_handle);
1371
1372         return rte_intr_callback_unregister(&fme_intr_handle,
1373                         fme_interrupt_handler,
1374                         (void *)mgr);
1375 }
1376
1377 static int
1378 ifpga_rawdev_create(struct rte_pci_device *pci_dev,
1379                         int socket_id)
1380 {
1381         int ret = 0;
1382         struct rte_rawdev *rawdev = NULL;
1383         struct ifpga_rawdev *dev = NULL;
1384         struct opae_adapter *adapter = NULL;
1385         struct opae_manager *mgr = NULL;
1386         struct opae_adapter_data_pci *data = NULL;
1387         char name[RTE_RAWDEV_NAME_MAX_LEN];
1388         int i;
1389
1390         if (!pci_dev) {
1391                 IFPGA_RAWDEV_PMD_ERR("Invalid pci_dev of the device!");
1392                 ret = -EINVAL;
1393                 goto cleanup;
1394         }
1395
1396         memset(name, 0, sizeof(name));
1397         snprintf(name, RTE_RAWDEV_NAME_MAX_LEN, "IFPGA:%02x:%02x.%x",
1398                 pci_dev->addr.bus, pci_dev->addr.devid, pci_dev->addr.function);
1399
1400         IFPGA_RAWDEV_PMD_INFO("Init %s on NUMA node %d", name, rte_socket_id());
1401
1402         /* Allocate device structure */
1403         rawdev = rte_rawdev_pmd_allocate(name, sizeof(struct opae_adapter),
1404                                          socket_id);
1405         if (rawdev == NULL) {
1406                 IFPGA_RAWDEV_PMD_ERR("Unable to allocate rawdevice");
1407                 ret = -EINVAL;
1408                 goto cleanup;
1409         }
1410
1411         ipn3ke_bridge_func.get_ifpga_rawdev = ifpga_rawdev_get;
1412         ipn3ke_bridge_func.set_i40e_sw_dev = rte_pmd_i40e_set_switch_dev;
1413
1414         dev = ifpga_rawdev_allocate(rawdev);
1415         if (dev == NULL) {
1416                 IFPGA_RAWDEV_PMD_ERR("Unable to allocate ifpga_rawdevice");
1417                 ret = -EINVAL;
1418                 goto cleanup;
1419         }
1420         dev->aer_enable = 0;
1421
1422         /* alloc OPAE_FPGA_PCI data to register to OPAE hardware level API */
1423         data = opae_adapter_data_alloc(OPAE_FPGA_PCI);
1424         if (!data) {
1425                 ret = -ENOMEM;
1426                 goto cleanup;
1427         }
1428
1429         /* init opae_adapter_data_pci for device specific information */
1430         for (i = 0; i < PCI_MAX_RESOURCE; i++) {
1431                 data->region[i].phys_addr = pci_dev->mem_resource[i].phys_addr;
1432                 data->region[i].len = pci_dev->mem_resource[i].len;
1433                 data->region[i].addr = pci_dev->mem_resource[i].addr;
1434         }
1435         data->device_id = pci_dev->id.device_id;
1436         data->vendor_id = pci_dev->id.vendor_id;
1437         data->bus = pci_dev->addr.bus;
1438         data->devid = pci_dev->addr.devid;
1439         data->function = pci_dev->addr.function;
1440         data->vfio_dev_fd = pci_dev->intr_handle.vfio_dev_fd;
1441
1442         adapter = rawdev->dev_private;
1443         /* create a opae_adapter based on above device data */
1444         ret = opae_adapter_init(adapter, pci_dev->device.name, data);
1445         if (ret) {
1446                 ret = -ENOMEM;
1447                 goto free_adapter_data;
1448         }
1449
1450         rawdev->dev_ops = &ifpga_rawdev_ops;
1451         rawdev->device = &pci_dev->device;
1452         rawdev->driver_name = pci_dev->driver->driver.name;
1453
1454         /* must enumerate the adapter before use it */
1455         ret = opae_adapter_enumerate(adapter);
1456         if (ret)
1457                 goto free_adapter_data;
1458
1459         /* get opae_manager to rawdev */
1460         mgr = opae_adapter_get_mgr(adapter);
1461         if (mgr) {
1462                 /* PF function */
1463                 IFPGA_RAWDEV_PMD_INFO("this is a PF function");
1464         }
1465
1466         ret = ifpga_register_fme_interrupt(mgr);
1467         if (ret)
1468                 goto free_adapter_data;
1469
1470         return ret;
1471
1472 free_adapter_data:
1473         if (data)
1474                 opae_adapter_data_free(data);
1475 cleanup:
1476         if (rawdev)
1477                 rte_rawdev_pmd_release(rawdev);
1478
1479         return ret;
1480 }
1481
1482 static int
1483 ifpga_rawdev_destroy(struct rte_pci_device *pci_dev)
1484 {
1485         int ret;
1486         struct rte_rawdev *rawdev;
1487         char name[RTE_RAWDEV_NAME_MAX_LEN];
1488         struct opae_adapter *adapter;
1489         struct opae_manager *mgr;
1490
1491         if (!pci_dev) {
1492                 IFPGA_RAWDEV_PMD_ERR("Invalid pci_dev of the device!");
1493                 ret = -EINVAL;
1494                 return ret;
1495         }
1496
1497         memset(name, 0, sizeof(name));
1498         snprintf(name, RTE_RAWDEV_NAME_MAX_LEN, "IFPGA:%x:%02x.%x",
1499                 pci_dev->addr.bus, pci_dev->addr.devid, pci_dev->addr.function);
1500
1501         IFPGA_RAWDEV_PMD_INFO("Closing %s on NUMA node %d",
1502                 name, rte_socket_id());
1503
1504         rawdev = rte_rawdev_pmd_get_named_dev(name);
1505         if (!rawdev) {
1506                 IFPGA_RAWDEV_PMD_ERR("Invalid device name (%s)", name);
1507                 return -EINVAL;
1508         }
1509
1510         adapter = ifpga_rawdev_get_priv(rawdev);
1511         if (!adapter)
1512                 return -ENODEV;
1513
1514         mgr = opae_adapter_get_mgr(adapter);
1515         if (!mgr)
1516                 return -ENODEV;
1517
1518         if (ifpga_unregister_fme_interrupt(mgr))
1519                 return -EINVAL;
1520
1521         opae_adapter_data_free(adapter->data);
1522         opae_adapter_free(adapter);
1523
1524         /* rte_rawdev_close is called by pmd_release */
1525         ret = rte_rawdev_pmd_release(rawdev);
1526         if (ret)
1527                 IFPGA_RAWDEV_PMD_DEBUG("Device cleanup failed");
1528
1529         return ret;
1530 }
1531
1532 static int
1533 ifpga_rawdev_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1534         struct rte_pci_device *pci_dev)
1535 {
1536         IFPGA_RAWDEV_PMD_FUNC_TRACE();
1537         return ifpga_rawdev_create(pci_dev, rte_socket_id());
1538 }
1539
1540 static int
1541 ifpga_rawdev_pci_remove(struct rte_pci_device *pci_dev)
1542 {
1543         ifpga_monitor_stop_func();
1544         return ifpga_rawdev_destroy(pci_dev);
1545 }
1546
1547 static struct rte_pci_driver rte_ifpga_rawdev_pmd = {
1548         .id_table  = pci_ifpga_map,
1549         .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
1550         .probe     = ifpga_rawdev_pci_probe,
1551         .remove    = ifpga_rawdev_pci_remove,
1552 };
1553
1554 RTE_PMD_REGISTER_PCI(ifpga_rawdev_pci_driver, rte_ifpga_rawdev_pmd);
1555 RTE_PMD_REGISTER_PCI_TABLE(ifpga_rawdev_pci_driver, rte_ifpga_rawdev_pmd);
1556 RTE_PMD_REGISTER_KMOD_DEP(ifpga_rawdev_pci_driver, "* igb_uio | uio_pci_generic | vfio-pci");
1557
1558 RTE_INIT(ifpga_rawdev_init_log)
1559 {
1560         ifpga_rawdev_logtype = rte_log_register("driver.raw.init");
1561         if (ifpga_rawdev_logtype >= 0)
1562                 rte_log_set_level(ifpga_rawdev_logtype, RTE_LOG_NOTICE);
1563 }
1564
1565 static const char * const valid_args[] = {
1566 #define IFPGA_ARG_NAME         "ifpga"
1567         IFPGA_ARG_NAME,
1568 #define IFPGA_ARG_PORT         "port"
1569         IFPGA_ARG_PORT,
1570 #define IFPGA_AFU_BTS          "afu_bts"
1571         IFPGA_AFU_BTS,
1572         NULL
1573 };
1574
1575 static int ifpga_rawdev_get_string_arg(const char *key __rte_unused,
1576         const char *value, void *extra_args)
1577 {
1578         int size;
1579         if (!value || !extra_args)
1580                 return -EINVAL;
1581
1582         size = strlen(value) + 1;
1583         *(char **)extra_args = rte_malloc(NULL, size, RTE_CACHE_LINE_SIZE);
1584         if (!*(char **)extra_args)
1585                 return -ENOMEM;
1586
1587         strlcpy(*(char **)extra_args, value, size);
1588
1589         return 0;
1590 }
1591 static int
1592 ifpga_cfg_probe(struct rte_vdev_device *dev)
1593 {
1594         struct rte_devargs *devargs;
1595         struct rte_kvargs *kvlist = NULL;
1596         struct rte_rawdev *rawdev = NULL;
1597         struct ifpga_rawdev *ifpga_dev;
1598         int port;
1599         char *name = NULL;
1600         const char *bdf;
1601         char dev_name[RTE_RAWDEV_NAME_MAX_LEN];
1602         int ret = -1;
1603
1604         devargs = dev->device.devargs;
1605
1606         kvlist = rte_kvargs_parse(devargs->args, valid_args);
1607         if (!kvlist) {
1608                 IFPGA_RAWDEV_PMD_LOG(ERR, "error when parsing param");
1609                 goto end;
1610         }
1611
1612         if (rte_kvargs_count(kvlist, IFPGA_ARG_NAME) == 1) {
1613                 if (rte_kvargs_process(kvlist, IFPGA_ARG_NAME,
1614                                        &ifpga_rawdev_get_string_arg,
1615                                        &name) < 0) {
1616                         IFPGA_RAWDEV_PMD_ERR("error to parse %s",
1617                                      IFPGA_ARG_NAME);
1618                         goto end;
1619                 }
1620         } else {
1621                 IFPGA_RAWDEV_PMD_ERR("arg %s is mandatory for ifpga bus",
1622                           IFPGA_ARG_NAME);
1623                 goto end;
1624         }
1625
1626         if (rte_kvargs_count(kvlist, IFPGA_ARG_PORT) == 1) {
1627                 if (rte_kvargs_process(kvlist,
1628                         IFPGA_ARG_PORT,
1629                         &rte_ifpga_get_integer32_arg,
1630                         &port) < 0) {
1631                         IFPGA_RAWDEV_PMD_ERR("error to parse %s",
1632                                 IFPGA_ARG_PORT);
1633                         goto end;
1634                 }
1635         } else {
1636                 IFPGA_RAWDEV_PMD_ERR("arg %s is mandatory for ifpga bus",
1637                           IFPGA_ARG_PORT);
1638                 goto end;
1639         }
1640
1641         memset(dev_name, 0, sizeof(dev_name));
1642         snprintf(dev_name, RTE_RAWDEV_NAME_MAX_LEN, "IFPGA:%s", name);
1643         rawdev = rte_rawdev_pmd_get_named_dev(dev_name);
1644         if (!rawdev)
1645                 goto end;
1646         ifpga_dev = ifpga_rawdev_get(rawdev);
1647         if (!ifpga_dev)
1648                 goto end;
1649         bdf = name;
1650         ifpga_rawdev_fill_info(ifpga_dev, bdf);
1651
1652         ifpga_monitor_start_func();
1653
1654         memset(dev_name, 0, sizeof(dev_name));
1655         snprintf(dev_name, RTE_RAWDEV_NAME_MAX_LEN, "%d|%s",
1656         port, name);
1657
1658         ret = rte_eal_hotplug_add(RTE_STR(IFPGA_BUS_NAME),
1659                         dev_name, devargs->args);
1660 end:
1661         if (kvlist)
1662                 rte_kvargs_free(kvlist);
1663         if (name)
1664                 free(name);
1665
1666         return ret;
1667 }
1668
1669 static int
1670 ifpga_cfg_remove(struct rte_vdev_device *vdev)
1671 {
1672         IFPGA_RAWDEV_PMD_INFO("Remove ifpga_cfg %p",
1673                 vdev);
1674
1675         return 0;
1676 }
1677
1678 static struct rte_vdev_driver ifpga_cfg_driver = {
1679         .probe = ifpga_cfg_probe,
1680         .remove = ifpga_cfg_remove,
1681 };
1682
1683 RTE_PMD_REGISTER_VDEV(ifpga_rawdev_cfg, ifpga_cfg_driver);
1684 RTE_PMD_REGISTER_ALIAS(ifpga_rawdev_cfg, ifpga_cfg);
1685 RTE_PMD_REGISTER_PARAM_STRING(ifpga_rawdev_cfg,
1686         "ifpga=<string> "
1687         "port=<int> "
1688         "afu_bts=<path>");