1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2010-2018 Intel Corporation
11 #include <sys/ioctl.h>
12 #include <sys/epoll.h>
15 #include <rte_malloc.h>
16 #include <rte_devargs.h>
17 #include <rte_memcpy.h>
19 #include <rte_bus_pci.h>
20 #include <rte_kvargs.h>
21 #include <rte_alarm.h>
22 #include <rte_interrupts.h>
23 #include <rte_errno.h>
24 #include <rte_per_lcore.h>
25 #include <rte_memory.h>
26 #include <rte_memzone.h>
28 #include <rte_common.h>
29 #include <rte_bus_vdev.h>
30 #include <rte_string_fns.h>
31 #include <rte_pmd_i40e.h>
33 #include "base/opae_hw_api.h"
34 #include "base/opae_ifpga_hw_api.h"
35 #include "base/ifpga_api.h"
36 #include "rte_rawdev.h"
37 #include "rte_rawdev_pmd.h"
38 #include "rte_bus_ifpga.h"
39 #include "ifpga_common.h"
40 #include "ifpga_logs.h"
41 #include "ifpga_rawdev.h"
42 #include "ipn3ke_rawdev_api.h"
44 #define PCI_VENDOR_ID_INTEL 0x8086
46 #define PCIE_DEVICE_ID_PF_INT_5_X 0xBCBD
47 #define PCIE_DEVICE_ID_PF_INT_6_X 0xBCC0
48 #define PCIE_DEVICE_ID_PF_DSC_1_X 0x09C4
49 #define PCIE_DEVICE_ID_PAC_N3000 0x0B30
51 #define PCIE_DEVICE_ID_VF_INT_5_X 0xBCBF
52 #define PCIE_DEVICE_ID_VF_INT_6_X 0xBCC1
53 #define PCIE_DEVICE_ID_VF_DSC_1_X 0x09C5
54 #define PCIE_DEVICE_ID_VF_PAC_N3000 0x0B31
55 #define RTE_MAX_RAW_DEVICE 10
57 static const struct rte_pci_id pci_ifpga_map[] = {
58 { RTE_PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_PF_INT_5_X) },
59 { RTE_PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_VF_INT_5_X) },
60 { RTE_PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_PF_INT_6_X) },
61 { RTE_PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_VF_INT_6_X) },
62 { RTE_PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_PF_DSC_1_X) },
63 { RTE_PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_VF_DSC_1_X) },
64 { RTE_PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_PAC_N3000),},
65 { RTE_PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_VF_PAC_N3000),},
66 { .vendor_id = 0, /* sentinel */ },
69 static struct ifpga_rawdev ifpga_rawdevices[IFPGA_RAWDEV_NUM];
71 static int ifpga_monitor_refcnt;
72 static pthread_t ifpga_monitor_start_thread;
74 static struct ifpga_rawdev *
75 ifpga_rawdev_allocate(struct rte_rawdev *rawdev);
76 static int set_surprise_link_check_aer(
77 struct ifpga_rawdev *ifpga_rdev, int force_disable);
78 static int ifpga_pci_find_next_ext_capability(unsigned int fd,
79 int start, uint32_t cap);
80 static int ifpga_pci_find_ext_capability(unsigned int fd, uint32_t cap);
83 ifpga_rawdev_get(const struct rte_rawdev *rawdev)
85 struct ifpga_rawdev *dev;
91 for (i = 0; i < IFPGA_RAWDEV_NUM; i++) {
92 dev = &ifpga_rawdevices[i];
93 if (dev->rawdev == rawdev)
100 static inline uint8_t
101 ifpga_rawdev_find_free_device_index(void)
105 for (dev_id = 0; dev_id < IFPGA_RAWDEV_NUM; dev_id++) {
106 if (ifpga_rawdevices[dev_id].rawdev == NULL)
110 return IFPGA_RAWDEV_NUM;
112 static struct ifpga_rawdev *
113 ifpga_rawdev_allocate(struct rte_rawdev *rawdev)
115 struct ifpga_rawdev *dev;
119 dev = ifpga_rawdev_get(rawdev);
121 IFPGA_RAWDEV_PMD_ERR("Event device already allocated!");
125 dev_id = ifpga_rawdev_find_free_device_index();
126 if (dev_id == IFPGA_RAWDEV_NUM) {
127 IFPGA_RAWDEV_PMD_ERR("Reached maximum number of raw devices");
131 dev = &ifpga_rawdevices[dev_id];
132 dev->rawdev = rawdev;
133 dev->dev_id = dev_id;
134 for (i = 0; i < IFPGA_MAX_IRQ; i++)
135 dev->intr_handle[i] = NULL;
136 dev->poll_enabled = 0;
142 ifpga_pci_find_next_ext_capability(unsigned int fd, int start, uint32_t cap)
146 int pos = RTE_PCI_CFG_SPACE_SIZE;
149 /* minimum 8 bytes per capability */
150 ttl = (RTE_PCI_CFG_SPACE_EXP_SIZE - RTE_PCI_CFG_SPACE_SIZE) / 8;
154 ret = pread(fd, &header, sizeof(header), pos);
159 * If we have no capabilities, this is indicated by cap ID,
160 * cap version and next pointer all being 0.
166 if (RTE_PCI_EXT_CAP_ID(header) == cap && pos != start)
169 pos = RTE_PCI_EXT_CAP_NEXT(header);
170 if (pos < RTE_PCI_CFG_SPACE_SIZE)
172 ret = pread(fd, &header, sizeof(header), pos);
181 ifpga_pci_find_ext_capability(unsigned int fd, uint32_t cap)
183 return ifpga_pci_find_next_ext_capability(fd, 0, cap);
186 static int ifpga_get_dev_vendor_id(const char *bdf,
187 uint32_t *dev_id, uint32_t *vendor_id)
194 strlcpy(path, "/sys/bus/pci/devices/", sizeof(path));
195 strlcat(path, bdf, sizeof(path));
196 strlcat(path, "/config", sizeof(path));
197 fd = open(path, O_RDWR);
200 ret = pread(fd, &header, sizeof(header), 0);
205 (*vendor_id) = header & 0xffff;
206 (*dev_id) = (header >> 16) & 0xffff;
212 static int ifpga_rawdev_fill_info(struct ifpga_rawdev *ifpga_dev)
214 struct opae_adapter *adapter = NULL;
215 char path[1024] = "/sys/bus/pci/devices/";
216 char link[1024], link1[1024];
217 char dir[1024] = "/sys/devices/";
220 char sub_brg_bdf[4][16] = {{0}};
223 struct dirent *entry;
226 unsigned int dom, bus, dev;
229 uint32_t vendor_id = 0;
231 adapter = ifpga_dev ? ifpga_rawdev_get_priv(ifpga_dev->rawdev) : NULL;
235 strlcat(path, adapter->name, sizeof(path));
236 memset(link, 0, sizeof(link));
237 memset(link1, 0, sizeof(link1));
238 ret = readlink(path, link, (sizeof(link)-1));
239 if ((ret < 0) || ((unsigned int)ret > (sizeof(link)-1)))
241 link[ret] = 0; /* terminate string with null character */
242 strlcpy(link1, link, sizeof(link1));
243 memset(ifpga_dev->parent_bdf, 0, 16);
244 point = strlen(link);
252 rte_memcpy(ifpga_dev->parent_bdf, &link[point], 12);
254 point = strlen(link1);
262 c = strchr(link1, 'p');
265 strlcat(dir, c, sizeof(dir));
272 while ((entry = readdir(dp)) != NULL) {
275 if (entry->d_name[0] == '.')
277 if (strlen(entry->d_name) > 12)
279 if (sscanf(entry->d_name, "%x:%x:%x.%d",
280 &dom, &bus, &dev, &func) < 4)
283 strlcpy(sub_brg_bdf[i],
285 sizeof(sub_brg_bdf[i]));
291 /* get fpga and fvl */
293 for (i = 0; i < 4; i++) {
294 strlcpy(link, dir, sizeof(link));
295 strlcat(link, "/", sizeof(link));
296 strlcat(link, sub_brg_bdf[i], sizeof(link));
300 while ((entry = readdir(dp)) != NULL) {
303 if (entry->d_name[0] == '.')
306 if (strlen(entry->d_name) > 12)
308 if (sscanf(entry->d_name, "%x:%x:%x.%d",
309 &dom, &bus, &dev, &func) < 4)
312 if (ifpga_get_dev_vendor_id(entry->d_name,
313 &dev_id, &vendor_id))
315 if (vendor_id == 0x8086 &&
319 strlcpy(ifpga_dev->fvl_bdf[j],
321 sizeof(ifpga_dev->fvl_bdf[j]));
332 #define HIGH_FATAL(_sens, value)\
333 (((_sens)->flags & OPAE_SENSOR_HIGH_FATAL_VALID) &&\
334 (value > (_sens)->high_fatal))
336 #define HIGH_WARN(_sens, value)\
337 (((_sens)->flags & OPAE_SENSOR_HIGH_WARN_VALID) &&\
338 (value > (_sens)->high_warn))
340 #define LOW_FATAL(_sens, value)\
341 (((_sens)->flags & OPAE_SENSOR_LOW_FATAL_VALID) &&\
342 (value > (_sens)->low_fatal))
344 #define LOW_WARN(_sens, value)\
345 (((_sens)->flags & OPAE_SENSOR_LOW_WARN_VALID) &&\
346 (value > (_sens)->low_warn))
348 #define AUX_VOLTAGE_WARN 11400
351 ifpga_monitor_sensor(struct rte_rawdev *raw_dev,
354 struct opae_adapter *adapter;
355 struct opae_manager *mgr;
356 struct opae_sensor_info *sensor;
360 adapter = ifpga_rawdev_get_priv(raw_dev);
364 mgr = opae_adapter_get_mgr(adapter);
368 opae_mgr_for_each_sensor(mgr, sensor) {
369 if (!(sensor->flags & OPAE_SENSOR_VALID))
372 ret = opae_mgr_get_sensor_value(mgr, sensor, &value);
376 if (value == 0xdeadbeef) {
377 IFPGA_RAWDEV_PMD_ERR("dev_id %d sensor %s value %x\n",
378 raw_dev->dev_id, sensor->name, value);
382 /* monitor temperature sensors */
383 if (!strcmp(sensor->name, "Board Temperature") ||
384 !strcmp(sensor->name, "FPGA Die Temperature")) {
385 IFPGA_RAWDEV_PMD_DEBUG("read sensor %s %d %d %d\n",
386 sensor->name, value, sensor->high_warn,
389 if (HIGH_WARN(sensor, value) ||
390 LOW_WARN(sensor, value)) {
391 IFPGA_RAWDEV_PMD_INFO("%s reach threshold %d\n",
392 sensor->name, value);
398 /* monitor 12V AUX sensor */
399 if (!strcmp(sensor->name, "12V AUX Voltage")) {
400 if (value < AUX_VOLTAGE_WARN) {
401 IFPGA_RAWDEV_PMD_INFO(
402 "%s reach threshold %d mV\n",
403 sensor->name, value);
415 static int set_surprise_link_check_aer(
416 struct ifpga_rawdev *ifpga_rdev, int force_disable)
418 struct rte_rawdev *rdev;
425 uint32_t aer_new0, aer_new1;
427 if (!ifpga_rdev || !ifpga_rdev->rawdev) {
428 printf("\n device does not exist\n");
432 rdev = ifpga_rdev->rawdev;
433 if (ifpga_rdev->aer_enable)
435 if (ifpga_monitor_sensor(rdev, &enable))
437 if (enable || force_disable) {
438 IFPGA_RAWDEV_PMD_ERR("Set AER, pls graceful shutdown\n");
439 ifpga_rdev->aer_enable = 1;
441 strlcpy(path, "/sys/bus/pci/devices/", sizeof(path));
442 strlcat(path, ifpga_rdev->parent_bdf, sizeof(path));
443 strlcat(path, "/config", sizeof(path));
444 fd = open(path, O_RDWR);
447 pos = ifpga_pci_find_ext_capability(fd, RTE_PCI_EXT_CAP_ID_ERR);
450 /* save previous ECAP_AER+0x08 */
451 ret = pread(fd, &data, sizeof(data), pos+0x08);
454 ifpga_rdev->aer_old[0] = data;
455 /* save previous ECAP_AER+0x14 */
456 ret = pread(fd, &data, sizeof(data), pos+0x14);
459 ifpga_rdev->aer_old[1] = data;
461 /* set ECAP_AER+0x08 to 0xFFFFFFFF */
463 ret = pwrite(fd, &data, 4, pos+0x08);
466 /* set ECAP_AER+0x14 to 0xFFFFFFFF */
467 ret = pwrite(fd, &data, 4, pos+0x14);
471 /* read current ECAP_AER+0x08 */
472 ret = pread(fd, &data, sizeof(data), pos+0x08);
476 /* read current ECAP_AER+0x14 */
477 ret = pread(fd, &data, sizeof(data), pos+0x14);
485 printf(">>>>>>Set AER %x,%x %x,%x\n",
486 ifpga_rdev->aer_old[0], ifpga_rdev->aer_old[1],
499 ifpga_rawdev_gsd_handle(__rte_unused void *param)
501 struct ifpga_rawdev *ifpga_rdev;
506 while (__atomic_load_n(&ifpga_monitor_refcnt, __ATOMIC_RELAXED)) {
508 for (i = 0; i < IFPGA_RAWDEV_NUM; i++) {
509 ifpga_rdev = &ifpga_rawdevices[i];
510 if (ifpga_rdev->poll_enabled) {
511 ret = set_surprise_link_check_aer(ifpga_rdev,
513 if (ret == 1 && !gsd_enable) {
521 printf(">>>>>>Pls Shutdown APP\n");
523 rte_delay_us(100 * MS);
530 ifpga_monitor_start_func(struct ifpga_rawdev *dev)
537 ret = ifpga_rawdev_fill_info(dev);
541 dev->poll_enabled = 1;
543 if (!__atomic_fetch_add(&ifpga_monitor_refcnt, 1, __ATOMIC_RELAXED)) {
544 ret = rte_ctrl_thread_create(&ifpga_monitor_start_thread,
545 "ifpga-monitor", NULL,
546 ifpga_rawdev_gsd_handle, NULL);
548 ifpga_monitor_start_thread = 0;
549 IFPGA_RAWDEV_PMD_ERR(
550 "Fail to create ifpga monitor thread");
559 ifpga_monitor_stop_func(struct ifpga_rawdev *dev)
563 if (!dev || !dev->poll_enabled)
566 dev->poll_enabled = 0;
568 if (!__atomic_sub_fetch(&ifpga_monitor_refcnt, 1, __ATOMIC_RELAXED) &&
569 ifpga_monitor_start_thread) {
570 ret = pthread_cancel(ifpga_monitor_start_thread);
572 IFPGA_RAWDEV_PMD_ERR("Can't cancel the thread");
574 ret = pthread_join(ifpga_monitor_start_thread, NULL);
576 IFPGA_RAWDEV_PMD_ERR("Can't join the thread");
585 ifpga_fill_afu_dev(struct opae_accelerator *acc,
586 struct rte_afu_device *afu_dev)
588 struct rte_mem_resource *res = afu_dev->mem_resource;
589 struct opae_acc_region_info region_info;
590 struct opae_acc_info info;
594 ret = opae_acc_get_info(acc, &info);
598 if (info.num_regions > PCI_MAX_RESOURCE)
601 afu_dev->num_region = info.num_regions;
603 for (i = 0; i < info.num_regions; i++) {
604 region_info.index = i;
605 ret = opae_acc_get_region_info(acc, ®ion_info);
609 if ((region_info.flags & ACC_REGION_MMIO) &&
610 (region_info.flags & ACC_REGION_READ) &&
611 (region_info.flags & ACC_REGION_WRITE)) {
612 res[i].phys_addr = region_info.phys_addr;
613 res[i].len = region_info.len;
614 res[i].addr = region_info.addr;
623 ifpga_rawdev_info_get(struct rte_rawdev *dev,
624 rte_rawdev_obj_t dev_info,
625 size_t dev_info_size)
627 struct opae_adapter *adapter;
628 struct opae_accelerator *acc;
629 struct rte_afu_device *afu_dev;
630 struct opae_manager *mgr = NULL;
631 struct opae_eth_group_region_info opae_lside_eth_info;
632 struct opae_eth_group_region_info opae_nside_eth_info;
633 int lside_bar_idx, nside_bar_idx;
635 IFPGA_RAWDEV_PMD_FUNC_TRACE();
637 if (!dev_info || dev_info_size != sizeof(*afu_dev)) {
638 IFPGA_RAWDEV_PMD_ERR("Invalid request");
642 adapter = ifpga_rawdev_get_priv(dev);
647 afu_dev->rawdev = dev;
649 /* find opae_accelerator and fill info into afu_device */
650 opae_adapter_for_each_acc(adapter, acc) {
651 if (acc->index != afu_dev->id.port)
654 if (ifpga_fill_afu_dev(acc, afu_dev)) {
655 IFPGA_RAWDEV_PMD_ERR("cannot get info\n");
660 /* get opae_manager to rawdev */
661 mgr = opae_adapter_get_mgr(adapter);
663 /* get LineSide BAR Index */
664 if (opae_manager_get_eth_group_region_info(mgr, 0,
665 &opae_lside_eth_info)) {
668 lside_bar_idx = opae_lside_eth_info.mem_idx;
670 /* get NICSide BAR Index */
671 if (opae_manager_get_eth_group_region_info(mgr, 1,
672 &opae_nside_eth_info)) {
675 nside_bar_idx = opae_nside_eth_info.mem_idx;
677 if (lside_bar_idx >= PCI_MAX_RESOURCE ||
678 nside_bar_idx >= PCI_MAX_RESOURCE ||
679 lside_bar_idx == nside_bar_idx)
682 /* fill LineSide BAR Index */
683 afu_dev->mem_resource[lside_bar_idx].phys_addr =
684 opae_lside_eth_info.phys_addr;
685 afu_dev->mem_resource[lside_bar_idx].len =
686 opae_lside_eth_info.len;
687 afu_dev->mem_resource[lside_bar_idx].addr =
688 opae_lside_eth_info.addr;
690 /* fill NICSide BAR Index */
691 afu_dev->mem_resource[nside_bar_idx].phys_addr =
692 opae_nside_eth_info.phys_addr;
693 afu_dev->mem_resource[nside_bar_idx].len =
694 opae_nside_eth_info.len;
695 afu_dev->mem_resource[nside_bar_idx].addr =
696 opae_nside_eth_info.addr;
702 ifpga_rawdev_configure(const struct rte_rawdev *dev,
703 rte_rawdev_obj_t config,
704 size_t config_size __rte_unused)
706 IFPGA_RAWDEV_PMD_FUNC_TRACE();
708 RTE_FUNC_PTR_OR_ERR_RET(dev, -EINVAL);
710 return config ? 0 : 1;
714 ifpga_rawdev_start(struct rte_rawdev *dev)
717 struct opae_adapter *adapter;
719 IFPGA_RAWDEV_PMD_FUNC_TRACE();
721 RTE_FUNC_PTR_OR_ERR_RET(dev, -EINVAL);
723 adapter = ifpga_rawdev_get_priv(dev);
731 ifpga_rawdev_stop(struct rte_rawdev *dev)
737 ifpga_rawdev_close(struct rte_rawdev *dev)
739 struct opae_adapter *adapter;
742 ifpga_monitor_stop_func(ifpga_rawdev_get(dev));
743 adapter = ifpga_rawdev_get_priv(dev);
745 opae_adapter_destroy(adapter);
746 opae_adapter_data_free(adapter->data);
754 ifpga_rawdev_reset(struct rte_rawdev *dev)
760 fpga_pr(struct rte_rawdev *raw_dev, u32 port_id, const char *buffer, u32 size,
764 struct opae_adapter *adapter;
765 struct opae_manager *mgr;
766 struct opae_accelerator *acc;
767 struct opae_bridge *br;
770 adapter = ifpga_rawdev_get_priv(raw_dev);
774 mgr = opae_adapter_get_mgr(adapter);
778 acc = opae_adapter_get_acc(adapter, port_id);
782 br = opae_acc_get_br(acc);
786 ret = opae_manager_flash(mgr, port_id, buffer, size, status);
788 IFPGA_RAWDEV_PMD_ERR("%s pr error %d\n", __func__, ret);
792 ret = opae_bridge_reset(br);
794 IFPGA_RAWDEV_PMD_ERR("%s reset port:%d error %d\n",
795 __func__, port_id, ret);
803 rte_fpga_do_pr(struct rte_rawdev *rawdev, int port_id,
804 const char *file_name)
806 struct stat file_stat;
810 void *buffer, *buf_to_free;
816 file_fd = open(file_name, O_RDONLY);
818 IFPGA_RAWDEV_PMD_ERR("%s: open file error: %s\n",
819 __func__, file_name);
820 IFPGA_RAWDEV_PMD_ERR("Message : %s\n", strerror(errno));
823 ret = stat(file_name, &file_stat);
825 IFPGA_RAWDEV_PMD_ERR("stat on bitstream file failed: %s\n",
830 buffer_size = file_stat.st_size;
831 if (buffer_size <= 0) {
836 IFPGA_RAWDEV_PMD_INFO("bitstream file size: %zu\n", buffer_size);
837 buffer = rte_malloc(NULL, buffer_size, 0);
842 buf_to_free = buffer;
844 /*read the raw data*/
845 if (buffer_size != read(file_fd, (void *)buffer, buffer_size)) {
851 ret = fpga_pr(rawdev, port_id, buffer, buffer_size, &pr_error);
852 IFPGA_RAWDEV_PMD_INFO("downloading to device port %d....%s.\n", port_id,
853 ret ? "failed" : "success");
860 rte_free(buf_to_free);
868 ifpga_rawdev_pr(struct rte_rawdev *dev,
869 rte_rawdev_obj_t pr_conf)
871 struct opae_adapter *adapter;
872 struct opae_manager *mgr;
873 struct opae_board_info *info;
874 struct rte_afu_pr_conf *afu_pr_conf;
877 struct opae_accelerator *acc;
879 IFPGA_RAWDEV_PMD_FUNC_TRACE();
881 adapter = ifpga_rawdev_get_priv(dev);
888 afu_pr_conf = pr_conf;
890 if (afu_pr_conf->pr_enable) {
891 ret = rte_fpga_do_pr(dev,
892 afu_pr_conf->afu_id.port,
893 afu_pr_conf->bs_path);
895 IFPGA_RAWDEV_PMD_ERR("do pr error %d\n", ret);
900 mgr = opae_adapter_get_mgr(adapter);
902 IFPGA_RAWDEV_PMD_ERR("opae_manager of opae_adapter is NULL");
906 if (ifpga_mgr_ops.get_board_info(mgr, &info)) {
907 IFPGA_RAWDEV_PMD_ERR("ifpga manager get_board_info fail!");
911 if (info->lightweight) {
912 /* set uuid to all 0, when fpga is lightweight image */
913 memset(&afu_pr_conf->afu_id.uuid.uuid_low, 0, sizeof(u64));
914 memset(&afu_pr_conf->afu_id.uuid.uuid_high, 0, sizeof(u64));
916 acc = opae_adapter_get_acc(adapter, afu_pr_conf->afu_id.port);
920 ret = opae_acc_get_uuid(acc, &uuid);
924 rte_memcpy(&afu_pr_conf->afu_id.uuid.uuid_low, uuid.b,
926 rte_memcpy(&afu_pr_conf->afu_id.uuid.uuid_high, uuid.b + 8,
929 IFPGA_RAWDEV_PMD_INFO("%s: uuid_l=0x%lx, uuid_h=0x%lx\n",
931 (unsigned long)afu_pr_conf->afu_id.uuid.uuid_low,
932 (unsigned long)afu_pr_conf->afu_id.uuid.uuid_high);
938 ifpga_rawdev_get_attr(struct rte_rawdev *dev,
939 const char *attr_name, uint64_t *attr_value)
941 struct opae_adapter *adapter;
942 struct opae_manager *mgr;
943 struct opae_retimer_info opae_rtm_info;
944 struct opae_retimer_status opae_rtm_status;
945 struct opae_eth_group_info opae_eth_grp_info;
946 struct opae_eth_group_region_info opae_eth_grp_reg_info;
947 int eth_group_num = 0;
948 uint64_t port_link_bitmap = 0, port_link_bit;
951 #define MAX_PORT_PER_RETIMER 4
953 IFPGA_RAWDEV_PMD_FUNC_TRACE();
955 if (!dev || !attr_name || !attr_value) {
956 IFPGA_RAWDEV_PMD_ERR("Invalid arguments for getting attributes");
960 adapter = ifpga_rawdev_get_priv(dev);
962 IFPGA_RAWDEV_PMD_ERR("Adapter of dev %s is NULL", dev->name);
966 mgr = opae_adapter_get_mgr(adapter);
968 IFPGA_RAWDEV_PMD_ERR("opae_manager of opae_adapter is NULL");
972 /* currently, eth_group_num is always 2 */
973 eth_group_num = opae_manager_get_eth_group_nums(mgr);
974 if (eth_group_num < 0)
977 if (!strcmp(attr_name, "LineSideBaseMAC")) {
978 /* Currently FPGA not implement, so just set all zeros*/
979 *attr_value = (uint64_t)0;
982 if (!strcmp(attr_name, "LineSideMACType")) {
983 /* eth_group 0 on FPGA connect to LineSide */
984 if (opae_manager_get_eth_group_info(mgr, 0,
987 switch (opae_eth_grp_info.speed) {
990 (uint64_t)(IFPGA_RAWDEV_RETIMER_MAC_TYPE_10GE_XFI);
994 (uint64_t)(IFPGA_RAWDEV_RETIMER_MAC_TYPE_25GE_25GAUI);
998 (uint64_t)(IFPGA_RAWDEV_RETIMER_MAC_TYPE_UNKNOWN);
1003 if (!strcmp(attr_name, "LineSideLinkSpeed")) {
1004 if (opae_manager_get_retimer_status(mgr, &opae_rtm_status))
1006 switch (opae_rtm_status.speed) {
1009 (uint64_t)(IFPGA_RAWDEV_LINK_SPEED_UNKNOWN);
1013 (uint64_t)(IFPGA_RAWDEV_LINK_SPEED_UNKNOWN);
1017 (uint64_t)(IFPGA_RAWDEV_LINK_SPEED_UNKNOWN);
1021 (uint64_t)(IFPGA_RAWDEV_LINK_SPEED_10GB);
1025 (uint64_t)(IFPGA_RAWDEV_LINK_SPEED_25GB);
1029 (uint64_t)(IFPGA_RAWDEV_LINK_SPEED_40GB);
1033 (uint64_t)(IFPGA_RAWDEV_LINK_SPEED_UNKNOWN);
1035 case MXD_SPEED_UNKNOWN:
1037 (uint64_t)(IFPGA_RAWDEV_LINK_SPEED_UNKNOWN);
1041 (uint64_t)(IFPGA_RAWDEV_LINK_SPEED_UNKNOWN);
1046 if (!strcmp(attr_name, "LineSideLinkRetimerNum")) {
1047 if (opae_manager_get_retimer_info(mgr, &opae_rtm_info))
1049 *attr_value = (uint64_t)(opae_rtm_info.nums_retimer);
1052 if (!strcmp(attr_name, "LineSideLinkPortNum")) {
1053 if (opae_manager_get_retimer_info(mgr, &opae_rtm_info))
1055 uint64_t tmp = (uint64_t)opae_rtm_info.ports_per_retimer *
1056 (uint64_t)opae_rtm_info.nums_retimer;
1060 if (!strcmp(attr_name, "LineSideLinkStatus")) {
1061 if (opae_manager_get_retimer_info(mgr, &opae_rtm_info))
1063 if (opae_manager_get_retimer_status(mgr, &opae_rtm_status))
1067 port_link_bitmap = (uint64_t)(opae_rtm_status.line_link_bitmap);
1068 for (i = 0; i < opae_rtm_info.nums_retimer; i++) {
1069 p = i * MAX_PORT_PER_RETIMER;
1070 for (j = 0; j < opae_rtm_info.ports_per_retimer; j++) {
1072 IFPGA_BIT_SET(port_link_bit, (p+j));
1073 port_link_bit &= port_link_bitmap;
1075 IFPGA_BIT_SET((*attr_value), q);
1081 if (!strcmp(attr_name, "LineSideBARIndex")) {
1082 /* eth_group 0 on FPGA connect to LineSide */
1083 if (opae_manager_get_eth_group_region_info(mgr, 0,
1084 &opae_eth_grp_reg_info))
1086 *attr_value = (uint64_t)opae_eth_grp_reg_info.mem_idx;
1089 if (!strcmp(attr_name, "NICSideMACType")) {
1090 /* eth_group 1 on FPGA connect to NicSide */
1091 if (opae_manager_get_eth_group_info(mgr, 1,
1092 &opae_eth_grp_info))
1094 *attr_value = (uint64_t)(opae_eth_grp_info.speed);
1097 if (!strcmp(attr_name, "NICSideLinkSpeed")) {
1098 /* eth_group 1 on FPGA connect to NicSide */
1099 if (opae_manager_get_eth_group_info(mgr, 1,
1100 &opae_eth_grp_info))
1102 *attr_value = (uint64_t)(opae_eth_grp_info.speed);
1105 if (!strcmp(attr_name, "NICSideLinkPortNum")) {
1106 if (opae_manager_get_retimer_info(mgr, &opae_rtm_info))
1108 uint64_t tmp = (uint64_t)opae_rtm_info.nums_fvl *
1109 (uint64_t)opae_rtm_info.ports_per_fvl;
1113 if (!strcmp(attr_name, "NICSideLinkStatus"))
1115 if (!strcmp(attr_name, "NICSideBARIndex")) {
1116 /* eth_group 1 on FPGA connect to NicSide */
1117 if (opae_manager_get_eth_group_region_info(mgr, 1,
1118 &opae_eth_grp_reg_info))
1120 *attr_value = (uint64_t)opae_eth_grp_reg_info.mem_idx;
1124 IFPGA_RAWDEV_PMD_ERR("%s not support", attr_name);
1128 static const struct rte_rawdev_ops ifpga_rawdev_ops = {
1129 .dev_info_get = ifpga_rawdev_info_get,
1130 .dev_configure = ifpga_rawdev_configure,
1131 .dev_start = ifpga_rawdev_start,
1132 .dev_stop = ifpga_rawdev_stop,
1133 .dev_close = ifpga_rawdev_close,
1134 .dev_reset = ifpga_rawdev_reset,
1136 .queue_def_conf = NULL,
1137 .queue_setup = NULL,
1138 .queue_release = NULL,
1140 .attr_get = ifpga_rawdev_get_attr,
1143 .enqueue_bufs = NULL,
1144 .dequeue_bufs = NULL,
1149 .xstats_get_names = NULL,
1150 .xstats_get_by_name = NULL,
1151 .xstats_reset = NULL,
1153 .firmware_status_get = NULL,
1154 .firmware_version_get = NULL,
1155 .firmware_load = ifpga_rawdev_pr,
1156 .firmware_unload = NULL,
1158 .dev_selftest = NULL,
1162 ifpga_get_fme_error_prop(struct opae_manager *mgr,
1163 u64 prop_id, u64 *val)
1165 struct feature_prop prop;
1167 prop.feature_id = IFPGA_FME_FEATURE_ID_GLOBAL_ERR;
1168 prop.prop_id = prop_id;
1170 if (opae_manager_ifpga_get_prop(mgr, &prop))
1179 ifpga_set_fme_error_prop(struct opae_manager *mgr,
1180 u64 prop_id, u64 val)
1182 struct feature_prop prop;
1184 prop.feature_id = IFPGA_FME_FEATURE_ID_GLOBAL_ERR;
1185 prop.prop_id = prop_id;
1189 if (opae_manager_ifpga_set_prop(mgr, &prop))
1196 fme_err_read_seu_emr(struct opae_manager *mgr)
1201 ret = ifpga_get_fme_error_prop(mgr, FME_ERR_PROP_SEU_EMR_LOW, &val);
1205 IFPGA_RAWDEV_PMD_INFO("seu emr low: 0x%" PRIx64 "\n", val);
1207 ret = ifpga_get_fme_error_prop(mgr, FME_ERR_PROP_SEU_EMR_HIGH, &val);
1211 IFPGA_RAWDEV_PMD_INFO("seu emr high: 0x%" PRIx64 "\n", val);
1216 static int fme_clear_warning_intr(struct opae_manager *mgr)
1220 if (ifpga_set_fme_error_prop(mgr, FME_ERR_PROP_INJECT_ERRORS, 0))
1223 if (ifpga_get_fme_error_prop(mgr, FME_ERR_PROP_NONFATAL_ERRORS, &val))
1225 if ((val & 0x40) != 0)
1226 IFPGA_RAWDEV_PMD_INFO("clean not done\n");
1231 static int fme_clean_fme_error(struct opae_manager *mgr)
1235 if (ifpga_get_fme_error_prop(mgr, FME_ERR_PROP_ERRORS, &val))
1238 IFPGA_RAWDEV_PMD_DEBUG("before clean 0x%" PRIx64 "\n", val);
1240 ifpga_set_fme_error_prop(mgr, FME_ERR_PROP_CLEAR, val);
1242 if (ifpga_get_fme_error_prop(mgr, FME_ERR_PROP_ERRORS, &val))
1245 IFPGA_RAWDEV_PMD_DEBUG("after clean 0x%" PRIx64 "\n", val);
1251 fme_err_handle_error0(struct opae_manager *mgr)
1253 struct feature_fme_error0 fme_error0;
1256 if (ifpga_get_fme_error_prop(mgr, FME_ERR_PROP_ERRORS, &val))
1259 if (fme_clean_fme_error(mgr))
1262 fme_error0.csr = val;
1264 if (fme_error0.fabric_err)
1265 IFPGA_RAWDEV_PMD_ERR("Fabric error\n");
1266 else if (fme_error0.fabfifo_overflow)
1267 IFPGA_RAWDEV_PMD_ERR("Fabric fifo under/overflow error\n");
1268 else if (fme_error0.afu_acc_mode_err)
1269 IFPGA_RAWDEV_PMD_ERR("AFU PF/VF access mismatch detected\n");
1270 else if (fme_error0.pcie0cdc_parity_err)
1271 IFPGA_RAWDEV_PMD_ERR("PCIe0 CDC Parity Error\n");
1272 else if (fme_error0.cvlcdc_parity_err)
1273 IFPGA_RAWDEV_PMD_ERR("CVL CDC Parity Error\n");
1274 else if (fme_error0.fpgaseuerr)
1275 fme_err_read_seu_emr(mgr);
1277 /* clean the errors */
1278 if (ifpga_set_fme_error_prop(mgr, FME_ERR_PROP_ERRORS, val))
1285 fme_err_handle_catfatal_error(struct opae_manager *mgr)
1287 struct feature_fme_ras_catfaterror fme_catfatal;
1290 if (ifpga_get_fme_error_prop(mgr, FME_ERR_PROP_CATFATAL_ERRORS, &val))
1293 fme_catfatal.csr = val;
1295 if (fme_catfatal.cci_fatal_err)
1296 IFPGA_RAWDEV_PMD_ERR("CCI error detected\n");
1297 else if (fme_catfatal.fabric_fatal_err)
1298 IFPGA_RAWDEV_PMD_ERR("Fabric fatal error detected\n");
1299 else if (fme_catfatal.pcie_poison_err)
1300 IFPGA_RAWDEV_PMD_ERR("Poison error from PCIe ports\n");
1301 else if (fme_catfatal.inject_fata_err)
1302 IFPGA_RAWDEV_PMD_ERR("Injected Fatal Error\n");
1303 else if (fme_catfatal.crc_catast_err)
1304 IFPGA_RAWDEV_PMD_ERR("a catastrophic EDCRC error\n");
1305 else if (fme_catfatal.injected_catast_err)
1306 IFPGA_RAWDEV_PMD_ERR("Injected Catastrophic Error\n");
1307 else if (fme_catfatal.bmc_seu_catast_err)
1308 fme_err_read_seu_emr(mgr);
1314 fme_err_handle_nonfaterror(struct opae_manager *mgr)
1316 struct feature_fme_ras_nonfaterror nonfaterr;
1319 if (ifpga_get_fme_error_prop(mgr, FME_ERR_PROP_NONFATAL_ERRORS, &val))
1322 nonfaterr.csr = val;
1324 if (nonfaterr.temp_thresh_ap1)
1325 IFPGA_RAWDEV_PMD_INFO("Temperature threshold triggered AP1\n");
1326 else if (nonfaterr.temp_thresh_ap2)
1327 IFPGA_RAWDEV_PMD_INFO("Temperature threshold triggered AP2\n");
1328 else if (nonfaterr.pcie_error)
1329 IFPGA_RAWDEV_PMD_INFO("an error has occurred in pcie\n");
1330 else if (nonfaterr.portfatal_error)
1331 IFPGA_RAWDEV_PMD_INFO("fatal error occurred in AFU port.\n");
1332 else if (nonfaterr.proc_hot)
1333 IFPGA_RAWDEV_PMD_INFO("a ProcHot event\n");
1334 else if (nonfaterr.afu_acc_mode_err)
1335 IFPGA_RAWDEV_PMD_INFO("an AFU PF/VF access mismatch\n");
1336 else if (nonfaterr.injected_nonfata_err) {
1337 IFPGA_RAWDEV_PMD_INFO("Injected Warning Error\n");
1338 fme_clear_warning_intr(mgr);
1339 } else if (nonfaterr.temp_thresh_AP6)
1340 IFPGA_RAWDEV_PMD_INFO("Temperature threshold triggered AP6\n");
1341 else if (nonfaterr.power_thresh_AP1)
1342 IFPGA_RAWDEV_PMD_INFO("Power threshold triggered AP1\n");
1343 else if (nonfaterr.power_thresh_AP2)
1344 IFPGA_RAWDEV_PMD_INFO("Power threshold triggered AP2\n");
1345 else if (nonfaterr.mbp_err)
1346 IFPGA_RAWDEV_PMD_INFO("an MBP event\n");
1352 fme_interrupt_handler(void *param)
1354 struct opae_manager *mgr = (struct opae_manager *)param;
1356 IFPGA_RAWDEV_PMD_INFO("%s interrupt occurred\n", __func__);
1358 fme_err_handle_error0(mgr);
1359 fme_err_handle_nonfaterror(mgr);
1360 fme_err_handle_catfatal_error(mgr);
1364 ifpga_unregister_msix_irq(struct ifpga_rawdev *dev, enum ifpga_irq_type type,
1365 int vec_start, rte_intr_callback_fn handler, void *arg)
1367 struct rte_intr_handle **intr_handle;
1369 int i = vec_start + 1;
1374 if (type == IFPGA_FME_IRQ)
1375 intr_handle = (struct rte_intr_handle **)&dev->intr_handle[0];
1376 else if (type == IFPGA_AFU_IRQ)
1377 intr_handle = (struct rte_intr_handle **)&dev->intr_handle[i];
1381 if ((*intr_handle) == NULL) {
1382 IFPGA_RAWDEV_PMD_ERR("%s interrupt %d not registered\n",
1383 type == IFPGA_FME_IRQ ? "FME" : "AFU",
1384 type == IFPGA_FME_IRQ ? 0 : vec_start);
1388 rte_intr_efd_disable(*intr_handle);
1390 rc = rte_intr_callback_unregister(*intr_handle, handler, arg);
1392 IFPGA_RAWDEV_PMD_ERR("Failed to unregister %s interrupt %d\n",
1393 type == IFPGA_FME_IRQ ? "FME" : "AFU",
1394 type == IFPGA_FME_IRQ ? 0 : vec_start);
1396 rte_intr_instance_free(*intr_handle);
1397 *intr_handle = NULL;
1404 ifpga_register_msix_irq(struct ifpga_rawdev *dev, int port_id,
1405 enum ifpga_irq_type type, int vec_start, int count,
1406 rte_intr_callback_fn handler, const char *name,
1410 struct rte_intr_handle **intr_handle;
1411 struct opae_adapter *adapter;
1412 struct opae_manager *mgr;
1413 struct opae_accelerator *acc;
1414 int *intr_efds = NULL, nb_intr, i;
1416 if (!dev || !dev->rawdev)
1419 adapter = ifpga_rawdev_get_priv(dev->rawdev);
1423 mgr = opae_adapter_get_mgr(adapter);
1427 if (type == IFPGA_FME_IRQ) {
1428 intr_handle = (struct rte_intr_handle **)&dev->intr_handle[0];
1430 } else if (type == IFPGA_AFU_IRQ) {
1432 intr_handle = (struct rte_intr_handle **)&dev->intr_handle[i];
1440 *intr_handle = rte_intr_instance_alloc(RTE_INTR_INSTANCE_F_PRIVATE);
1441 if (!(*intr_handle))
1444 if (rte_intr_type_set(*intr_handle, RTE_INTR_HANDLE_VFIO_MSIX))
1447 ret = rte_intr_efd_enable(*intr_handle, count);
1451 if (rte_intr_fd_set(*intr_handle,
1452 rte_intr_efds_index_get(*intr_handle, 0)))
1455 IFPGA_RAWDEV_PMD_DEBUG("register %s irq, vfio_fd=%d, fd=%d\n",
1456 name, rte_intr_dev_fd_get(*intr_handle),
1457 rte_intr_fd_get(*intr_handle));
1459 if (type == IFPGA_FME_IRQ) {
1460 struct fpga_fme_err_irq_set err_irq_set;
1461 err_irq_set.evtfd = rte_intr_efds_index_get(*intr_handle,
1464 ret = opae_manager_ifpga_set_err_irq(mgr, &err_irq_set);
1467 } else if (type == IFPGA_AFU_IRQ) {
1468 acc = opae_adapter_get_acc(adapter, port_id);
1472 nb_intr = rte_intr_nb_intr_get(*intr_handle);
1474 intr_efds = calloc(nb_intr, sizeof(int));
1478 for (i = 0; i < nb_intr; i++)
1479 intr_efds[i] = rte_intr_efds_index_get(*intr_handle, i);
1481 ret = opae_acc_set_irq(acc, vec_start, count, intr_efds);
1488 /* register interrupt handler using DPDK API */
1489 ret = rte_intr_callback_register(*intr_handle,
1490 handler, (void *)arg);
1496 IFPGA_RAWDEV_PMD_INFO("success register %s interrupt\n", name);
1503 ifpga_rawdev_create(struct rte_pci_device *pci_dev,
1507 struct rte_rawdev *rawdev = NULL;
1508 struct ifpga_rawdev *dev = NULL;
1509 struct opae_adapter *adapter = NULL;
1510 struct opae_manager *mgr = NULL;
1511 struct opae_adapter_data_pci *data = NULL;
1512 char name[RTE_RAWDEV_NAME_MAX_LEN];
1516 IFPGA_RAWDEV_PMD_ERR("Invalid pci_dev of the device!");
1521 memset(name, 0, sizeof(name));
1522 snprintf(name, RTE_RAWDEV_NAME_MAX_LEN, IFPGA_RAWDEV_NAME_FMT,
1523 pci_dev->addr.bus, pci_dev->addr.devid, pci_dev->addr.function);
1525 IFPGA_RAWDEV_PMD_INFO("Init %s on NUMA node %d", name, rte_socket_id());
1527 /* Allocate device structure */
1528 rawdev = rte_rawdev_pmd_allocate(name, sizeof(struct opae_adapter),
1530 if (rawdev == NULL) {
1531 IFPGA_RAWDEV_PMD_ERR("Unable to allocate rawdevice");
1536 ipn3ke_bridge_func.get_ifpga_rawdev = ifpga_rawdev_get;
1537 ipn3ke_bridge_func.set_i40e_sw_dev = rte_pmd_i40e_set_switch_dev;
1539 dev = ifpga_rawdev_allocate(rawdev);
1541 IFPGA_RAWDEV_PMD_ERR("Unable to allocate ifpga_rawdevice");
1545 dev->aer_enable = 0;
1547 /* alloc OPAE_FPGA_PCI data to register to OPAE hardware level API */
1548 data = opae_adapter_data_alloc(OPAE_FPGA_PCI);
1554 /* init opae_adapter_data_pci for device specific information */
1555 for (i = 0; i < PCI_MAX_RESOURCE; i++) {
1556 data->region[i].phys_addr = pci_dev->mem_resource[i].phys_addr;
1557 data->region[i].len = pci_dev->mem_resource[i].len;
1558 data->region[i].addr = pci_dev->mem_resource[i].addr;
1560 data->device_id = pci_dev->id.device_id;
1561 data->vendor_id = pci_dev->id.vendor_id;
1562 data->bus = pci_dev->addr.bus;
1563 data->devid = pci_dev->addr.devid;
1564 data->function = pci_dev->addr.function;
1565 data->vfio_dev_fd = rte_intr_dev_fd_get(pci_dev->intr_handle);
1567 adapter = rawdev->dev_private;
1568 /* create a opae_adapter based on above device data */
1569 ret = opae_adapter_init(adapter, pci_dev->device.name, data);
1572 goto free_adapter_data;
1575 rawdev->dev_ops = &ifpga_rawdev_ops;
1576 rawdev->device = &pci_dev->device;
1577 rawdev->driver_name = pci_dev->driver->driver.name;
1579 /* must enumerate the adapter before use it */
1580 ret = opae_adapter_enumerate(adapter);
1582 goto free_adapter_data;
1584 /* get opae_manager to rawdev */
1585 mgr = opae_adapter_get_mgr(adapter);
1588 IFPGA_RAWDEV_PMD_INFO("this is a PF function");
1591 ret = ifpga_register_msix_irq(dev, 0, IFPGA_FME_IRQ, 0, 0,
1592 fme_interrupt_handler, "fme_irq", mgr);
1594 goto free_adapter_data;
1596 ret = ifpga_monitor_start_func(dev);
1598 goto free_adapter_data;
1604 opae_adapter_data_free(data);
1607 rte_rawdev_pmd_release(rawdev);
1613 ifpga_rawdev_destroy(struct rte_pci_device *pci_dev)
1616 struct rte_rawdev *rawdev;
1617 char name[RTE_RAWDEV_NAME_MAX_LEN];
1618 struct opae_adapter *adapter;
1619 struct opae_manager *mgr;
1620 struct ifpga_rawdev *dev;
1623 IFPGA_RAWDEV_PMD_ERR("Invalid pci_dev of the device!");
1628 memset(name, 0, sizeof(name));
1629 snprintf(name, RTE_RAWDEV_NAME_MAX_LEN, IFPGA_RAWDEV_NAME_FMT,
1630 pci_dev->addr.bus, pci_dev->addr.devid, pci_dev->addr.function);
1632 IFPGA_RAWDEV_PMD_INFO("Closing %s on NUMA node %d",
1633 name, rte_socket_id());
1635 rawdev = rte_rawdev_pmd_get_named_dev(name);
1637 IFPGA_RAWDEV_PMD_ERR("Invalid device name (%s)", name);
1640 dev = ifpga_rawdev_get(rawdev);
1644 adapter = ifpga_rawdev_get_priv(rawdev);
1648 mgr = opae_adapter_get_mgr(adapter);
1652 if (ifpga_unregister_msix_irq(dev, IFPGA_FME_IRQ, 0,
1653 fme_interrupt_handler, mgr) < 0)
1656 /* rte_rawdev_close is called by pmd_release */
1657 ret = rte_rawdev_pmd_release(rawdev);
1659 IFPGA_RAWDEV_PMD_DEBUG("Device cleanup failed");
1665 ifpga_rawdev_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1666 struct rte_pci_device *pci_dev)
1668 IFPGA_RAWDEV_PMD_FUNC_TRACE();
1669 return ifpga_rawdev_create(pci_dev, rte_socket_id());
1673 ifpga_rawdev_pci_remove(struct rte_pci_device *pci_dev)
1675 IFPGA_RAWDEV_PMD_INFO("remove pci_dev %s", pci_dev->device.name);
1676 return ifpga_rawdev_destroy(pci_dev);
1679 static struct rte_pci_driver rte_ifpga_rawdev_pmd = {
1680 .id_table = pci_ifpga_map,
1681 .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
1682 .probe = ifpga_rawdev_pci_probe,
1683 .remove = ifpga_rawdev_pci_remove,
1686 RTE_PMD_REGISTER_PCI(ifpga_rawdev_pci_driver, rte_ifpga_rawdev_pmd);
1687 RTE_PMD_REGISTER_PCI_TABLE(ifpga_rawdev_pci_driver, rte_ifpga_rawdev_pmd);
1688 RTE_PMD_REGISTER_KMOD_DEP(ifpga_rawdev_pci_driver, "* igb_uio | uio_pci_generic | vfio-pci");
1689 RTE_LOG_REGISTER_DEFAULT(ifpga_rawdev_logtype, NOTICE);
1691 static const char * const valid_args[] = {
1692 #define IFPGA_ARG_NAME "ifpga"
1694 #define IFPGA_ARG_PORT "port"
1696 #define IFPGA_AFU_BTS "afu_bts"
1701 static int ifpga_rawdev_get_string_arg(const char *key __rte_unused,
1702 const char *value, void *extra_args)
1705 if (!value || !extra_args)
1708 size = strlen(value) + 1;
1709 *(char **)extra_args = rte_malloc(NULL, size, RTE_CACHE_LINE_SIZE);
1710 if (!*(char **)extra_args)
1713 strlcpy(*(char **)extra_args, value, size);
1718 ifpga_cfg_probe(struct rte_vdev_device *dev)
1720 struct rte_devargs *devargs;
1721 struct rte_kvargs *kvlist = NULL;
1722 struct rte_rawdev *rawdev = NULL;
1723 struct ifpga_rawdev *ifpga_dev;
1726 char dev_name[RTE_RAWDEV_NAME_MAX_LEN];
1729 devargs = dev->device.devargs;
1731 kvlist = rte_kvargs_parse(devargs->args, valid_args);
1733 IFPGA_RAWDEV_PMD_LOG(ERR, "error when parsing param");
1737 if (rte_kvargs_count(kvlist, IFPGA_ARG_NAME) == 1) {
1738 if (rte_kvargs_process(kvlist, IFPGA_ARG_NAME,
1739 &ifpga_rawdev_get_string_arg,
1741 IFPGA_RAWDEV_PMD_ERR("error to parse %s",
1746 IFPGA_RAWDEV_PMD_ERR("arg %s is mandatory for ifpga bus",
1751 if (rte_kvargs_count(kvlist, IFPGA_ARG_PORT) == 1) {
1752 if (rte_kvargs_process(kvlist,
1754 &rte_ifpga_get_integer32_arg,
1756 IFPGA_RAWDEV_PMD_ERR("error to parse %s",
1761 IFPGA_RAWDEV_PMD_ERR("arg %s is mandatory for ifpga bus",
1766 memset(dev_name, 0, sizeof(dev_name));
1767 snprintf(dev_name, RTE_RAWDEV_NAME_MAX_LEN, "IFPGA:%s", name);
1768 rawdev = rte_rawdev_pmd_get_named_dev(dev_name);
1771 ifpga_dev = ifpga_rawdev_get(rawdev);
1775 memset(dev_name, 0, sizeof(dev_name));
1776 snprintf(dev_name, RTE_RAWDEV_NAME_MAX_LEN, "%d|%s",
1779 ret = rte_eal_hotplug_add(RTE_STR(IFPGA_BUS_NAME),
1780 dev_name, devargs->args);
1782 rte_kvargs_free(kvlist);
1789 ifpga_cfg_remove(struct rte_vdev_device *vdev)
1791 IFPGA_RAWDEV_PMD_INFO("Remove ifpga_cfg %p",
1797 static struct rte_vdev_driver ifpga_cfg_driver = {
1798 .probe = ifpga_cfg_probe,
1799 .remove = ifpga_cfg_remove,
1802 RTE_PMD_REGISTER_VDEV(ifpga_rawdev_cfg, ifpga_cfg_driver);
1803 RTE_PMD_REGISTER_ALIAS(ifpga_rawdev_cfg, ifpga_cfg);
1804 RTE_PMD_REGISTER_PARAM_STRING(ifpga_rawdev_cfg,
1809 struct rte_pci_bus *ifpga_get_pci_bus(void)
1811 return rte_ifpga_rawdev_pmd.bus;
1814 int ifpga_rawdev_partial_reconfigure(struct rte_rawdev *dev, int port,
1818 IFPGA_RAWDEV_PMD_ERR("Input parameter is invalid");
1822 return rte_fpga_do_pr(dev, port, file);
1825 void ifpga_rawdev_cleanup(void)
1827 struct ifpga_rawdev *dev;
1830 for (i = 0; i < IFPGA_RAWDEV_NUM; i++) {
1831 dev = &ifpga_rawdevices[i];
1833 rte_rawdev_pmd_release(dev->rawdev);