drivers/raw/ifpga/ifpga_rawdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2010-2018 Intel Corporation
   3  */
   4
   5 #include <string.h>
   6 #include <dirent.h>
   7 #include <sys/stat.h>
   8 #include <unistd.h>
   9 #include <sys/types.h>
  10 #include <fcntl.h>
  11 #include <sys/ioctl.h>
  12 #include <sys/epoll.h>
  13 #include <rte_log.h>
  14 #include <rte_bus.h>
  15 #include <rte_malloc.h>
  16 #include <rte_devargs.h>
  17 #include <rte_memcpy.h>
  18 #include <rte_pci.h>
  19 #include <rte_bus_pci.h>
  20 #include <rte_kvargs.h>
  21 #include <rte_alarm.h>
  22 #include <rte_interrupts.h>
  23 #include <rte_errno.h>
  24 #include <rte_per_lcore.h>
  25 #include <rte_memory.h>
  26 #include <rte_memzone.h>
  27 #include <rte_eal.h>
  28 #include <rte_common.h>
  29 #include <rte_bus_vdev.h>
  30 #include <rte_string_fns.h>
  31 #include <rte_pmd_i40e.h>
  32
  33 #include "base/opae_hw_api.h"
  34 #include "base/opae_ifpga_hw_api.h"
  35 #include "base/ifpga_api.h"
  36 #include "rte_rawdev.h"
  37 #include "rte_rawdev_pmd.h"
  38 #include "rte_bus_ifpga.h"
  39 #include "ifpga_common.h"
  40 #include "ifpga_logs.h"
  41 #include "ifpga_rawdev.h"
  42 #include "ipn3ke_rawdev_api.h"
  43
  44 #define RTE_PCI_EXT_CAP_ID_ERR           0x01   /* Advanced Error Reporting */
  45 #define RTE_PCI_CFG_SPACE_SIZE           256
  46 #define RTE_PCI_CFG_SPACE_EXP_SIZE       4096
  47 #define RTE_PCI_EXT_CAP_ID(header)       (int)(header & 0x0000ffff)
  48 #define RTE_PCI_EXT_CAP_NEXT(header)     ((header >> 20) & 0xffc)
  49
  50 int ifpga_rawdev_logtype;
  51
  52 #define PCI_VENDOR_ID_INTEL          0x8086
  53 /* PCI Device ID */
  54 #define PCIE_DEVICE_ID_PF_INT_5_X    0xBCBD
  55 #define PCIE_DEVICE_ID_PF_INT_6_X    0xBCC0
  56 #define PCIE_DEVICE_ID_PF_DSC_1_X    0x09C4
  57 #define PCIE_DEVICE_ID_PAC_N3000     0x0B30
  58 /* VF Device */
  59 #define PCIE_DEVICE_ID_VF_INT_5_X    0xBCBF
  60 #define PCIE_DEVICE_ID_VF_INT_6_X    0xBCC1
  61 #define PCIE_DEVICE_ID_VF_DSC_1_X    0x09C5
  62 #define PCIE_DEVICE_ID_VF_PAC_N3000  0x0B31
  63 #define RTE_MAX_RAW_DEVICE           10
  64
  65 static const struct rte_pci_id pci_ifpga_map[] = {
  66         { RTE_PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_PF_INT_5_X) },
  67         { RTE_PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_VF_INT_5_X) },
  68         { RTE_PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_PF_INT_6_X) },
  69         { RTE_PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_VF_INT_6_X) },
  70         { RTE_PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_PF_DSC_1_X) },
  71         { RTE_PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_VF_DSC_1_X) },
  72         { RTE_PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_PAC_N3000),},
  73         { RTE_PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_VF_PAC_N3000),},
  74         { .vendor_id = 0, /* sentinel */ },
  75 };
  76
  77 static struct ifpga_rawdev ifpga_rawdevices[IFPGA_RAWDEV_NUM];
  78
  79 static int ifpga_monitor_start;
  80 static pthread_t ifpga_monitor_start_thread;
  81
  82 static struct ifpga_rawdev *
  83 ifpga_rawdev_allocate(struct rte_rawdev *rawdev);
  84 static int set_surprise_link_check_aer(
  85                 struct ifpga_rawdev *ifpga_rdev, int force_disable);
  86 static int ifpga_pci_find_next_ext_capability(unsigned int fd,
  87                 int start, int cap);
  88 static int ifpga_pci_find_ext_capability(unsigned int fd, int cap);
  89
  90 struct ifpga_rawdev *
  91 ifpga_rawdev_get(const struct rte_rawdev *rawdev)
  92 {
  93         struct ifpga_rawdev *dev;
  94         unsigned int i;
  95
  96         if (rawdev == NULL)
  97                 return NULL;
  98
  99         for (i = 0; i < IFPGA_RAWDEV_NUM; i++) {
 100                 dev = &ifpga_rawdevices[i];
 101                 if (dev->rawdev == rawdev)
 102                         return dev;
 103         }
 104
 105         return NULL;
 106 }
 107
 108 static inline uint8_t
 109 ifpga_rawdev_find_free_device_index(void)
 110 {
 111         uint16_t dev_id;
 112
 113         for (dev_id = 0; dev_id < IFPGA_RAWDEV_NUM; dev_id++) {
 114                 if (ifpga_rawdevices[dev_id].rawdev == NULL)
 115                         return dev_id;
 116         }
 117
 118         return IFPGA_RAWDEV_NUM;
 119 }
 120 static struct ifpga_rawdev *
 121 ifpga_rawdev_allocate(struct rte_rawdev *rawdev)
 122 {
 123         struct ifpga_rawdev *dev;
 124         uint16_t dev_id;
 125
 126         dev = ifpga_rawdev_get(rawdev);
 127         if (dev != NULL) {
 128                 IFPGA_RAWDEV_PMD_ERR("Event device already allocated!");
 129                 return NULL;
 130         }
 131
 132         dev_id = ifpga_rawdev_find_free_device_index();
 133         if (dev_id == IFPGA_RAWDEV_NUM) {
 134                 IFPGA_RAWDEV_PMD_ERR("Reached maximum number of raw devices");
 135                 return NULL;
 136         }
 137
 138         dev = &ifpga_rawdevices[dev_id];
 139         dev->rawdev = rawdev;
 140         dev->dev_id = dev_id;
 141
 142         return dev;
 143 }
 144
 145 static int ifpga_pci_find_next_ext_capability(unsigned int fd,
 146 int start, int cap)
 147 {
 148         uint32_t header;
 149         int ttl;
 150         int pos = RTE_PCI_CFG_SPACE_SIZE;
 151         int ret;
 152
 153         /* minimum 8 bytes per capability */
 154         ttl = (RTE_PCI_CFG_SPACE_EXP_SIZE - RTE_PCI_CFG_SPACE_SIZE) / 8;
 155
 156         if (start)
 157                 pos = start;
 158         ret = pread(fd, &header, sizeof(header), pos);
 159         if (ret == -1)
 160                 return -1;
 161
 162         /*
 163          * If we have no capabilities, this is indicated by cap ID,
 164          * cap version and next pointer all being 0.
 165          */
 166         if (header == 0)
 167                 return 0;
 168
 169         while (ttl-- > 0) {
 170                 if (RTE_PCI_EXT_CAP_ID(header) == cap && pos != start)
 171                         return pos;
 172
 173                 pos = RTE_PCI_EXT_CAP_NEXT(header);
 174                 if (pos < RTE_PCI_CFG_SPACE_SIZE)
 175                         break;
 176                 ret = pread(fd, &header, sizeof(header), pos);
 177                 if (ret == -1)
 178                         return -1;
 179         }
 180
 181         return 0;
 182 }
 183
 184 static int ifpga_pci_find_ext_capability(unsigned int fd, int cap)
 185 {
 186         return ifpga_pci_find_next_ext_capability(fd, 0, cap);
 187 }
 188
 189 static int ifpga_get_dev_vendor_id(const char *bdf,
 190         uint32_t *dev_id, uint32_t *vendor_id)
 191 {
 192         int fd;
 193         char path[1024];
 194         int ret;
 195         uint32_t header;
 196
 197         strlcpy(path, "/sys/bus/pci/devices/", sizeof(path));
 198         strlcat(path, bdf, sizeof(path));
 199         strlcat(path, "/config", sizeof(path));
 200         fd = open(path, O_RDWR);
 201         if (fd < 0)
 202                 return -1;
 203         ret = pread(fd, &header, sizeof(header), 0);
 204         if (ret == -1) {
 205                 close(fd);
 206                 return -1;
 207         }
 208         (*vendor_id) = header & 0xffff;
 209         (*dev_id) = (header >> 16) & 0xffff;
 210         close(fd);
 211
 212         return 0;
 213 }
 214 static int ifpga_rawdev_fill_info(struct ifpga_rawdev *ifpga_dev,
 215         const char *bdf)
 216 {
 217         char path[1024] = "/sys/bus/pci/devices/0000:";
 218         char link[1024], link1[1024];
 219         char dir[1024] = "/sys/devices/";
 220         char *c;
 221         int ret;
 222         char sub_brg_bdf[4][16];
 223         int point;
 224         DIR *dp = NULL;
 225         struct dirent *entry;
 226         int i, j;
 227
 228         unsigned int dom, bus, dev;
 229         int func;
 230         uint32_t dev_id, vendor_id;
 231
 232         strlcat(path, bdf, sizeof(path));
 233         memset(link, 0, sizeof(link));
 234         memset(link1, 0, sizeof(link1));
 235         ret = readlink(path, link, (sizeof(link)-1));
 236         if (ret == -1)
 237                 return -1;
 238         strlcpy(link1, link, sizeof(link1));
 239         memset(ifpga_dev->parent_bdf, 0, 16);
 240         point = strlen(link);
 241         if (point < 39)
 242                 return -1;
 243         point -= 39;
 244         link[point] = 0;
 245         if (point < 12)
 246                 return -1;
 247         point -= 12;
 248         rte_memcpy(ifpga_dev->parent_bdf, &link[point], 12);
 249
 250         point = strlen(link1);
 251         if (point < 26)
 252                 return -1;
 253         point -= 26;
 254         link1[point] = 0;
 255         if (point < 12)
 256                 return -1;
 257         point -= 12;
 258         c = strchr(link1, 'p');
 259         if (!c)
 260                 return -1;
 261         strlcat(dir, c, sizeof(dir));
 262
 263         /* scan folder */
 264         dp = opendir(dir);
 265         if (dp == NULL)
 266                 return -1;
 267         i = 0;
 268         while ((entry = readdir(dp)) != NULL) {
 269                 if (i >= 4)
 270                         break;
 271                 if (entry->d_name[0] == '.')
 272                         continue;
 273                 if (strlen(entry->d_name) > 12)
 274                         continue;
 275                 if (sscanf(entry->d_name, "%x:%x:%x.%d",
 276                         &dom, &bus, &dev, &func) < 4)
 277                         continue;
 278                 else {
 279                         strlcpy(sub_brg_bdf[i],
 280                                 entry->d_name,
 281                                 sizeof(sub_brg_bdf[i]));
 282                         i++;
 283                 }
 284         }
 285         closedir(dp);
 286
 287         /* get fpga and fvl */
 288         j = 0;
 289         for (i = 0; i < 4; i++) {
 290                 strlcpy(link, dir, sizeof(link));
 291                 strlcat(link, "/", sizeof(link));
 292                 strlcat(link, sub_brg_bdf[i], sizeof(link));
 293                 dp = opendir(link);
 294                 if (dp == NULL)
 295                         return -1;
 296                 while ((entry = readdir(dp)) != NULL) {
 297                         if (j >= 8)
 298                                 break;
 299                         if (entry->d_name[0] == '.')
 300                                 continue;
 301
 302                         if (strlen(entry->d_name) > 12)
 303                                 continue;
 304                         if (sscanf(entry->d_name, "%x:%x:%x.%d",
 305                                 &dom, &bus, &dev, &func) < 4)
 306                                 continue;
 307                         else {
 308                                 if (ifpga_get_dev_vendor_id(entry->d_name,
 309                                         &dev_id, &vendor_id))
 310                                         continue;
 311                                 if (vendor_id == 0x8086 &&
 312                                         (dev_id == 0x0CF8 ||
 313                                         dev_id == 0x0D58 ||
 314                                         dev_id == 0x1580)) {
 315                                         strlcpy(ifpga_dev->fvl_bdf[j],
 316                                                 entry->d_name,
 317                                                 sizeof(ifpga_dev->fvl_bdf[j]));
 318                                         j++;
 319                                 }
 320                         }
 321                 }
 322                 closedir(dp);
 323         }
 324
 325         return 0;
 326 }
 327
 328 #define HIGH_FATAL(_sens, value)\
 329         (((_sens)->flags & OPAE_SENSOR_HIGH_FATAL_VALID) &&\
 330          (value > (_sens)->high_fatal))
 331
 332 #define HIGH_WARN(_sens, value)\
 333         (((_sens)->flags & OPAE_SENSOR_HIGH_WARN_VALID) &&\
 334          (value > (_sens)->high_warn))
 335
 336 #define LOW_FATAL(_sens, value)\
 337         (((_sens)->flags & OPAE_SENSOR_LOW_FATAL_VALID) &&\
 338          (value > (_sens)->low_fatal))
 339
 340 #define LOW_WARN(_sens, value)\
 341         (((_sens)->flags & OPAE_SENSOR_LOW_WARN_VALID) &&\
 342          (value > (_sens)->low_warn))
 343
 344 #define AUX_VOLTAGE_WARN 11400
 345
 346 static int
 347 ifpga_monitor_sensor(struct rte_rawdev *raw_dev,
 348                bool *gsd_start)
 349 {
 350         struct opae_adapter *adapter;
 351         struct opae_manager *mgr;
 352         struct opae_sensor_info *sensor;
 353         unsigned int value;
 354         int ret;
 355
 356         adapter = ifpga_rawdev_get_priv(raw_dev);
 357         if (!adapter)
 358                 return -ENODEV;
 359
 360         mgr = opae_adapter_get_mgr(adapter);
 361         if (!mgr)
 362                 return -ENODEV;
 363
 364         opae_mgr_for_each_sensor(sensor) {
 365                 if (!(sensor->flags & OPAE_SENSOR_VALID))
 366                         goto fail;
 367
 368                 ret = opae_mgr_get_sensor_value(mgr, sensor, &value);
 369                 if (ret)
 370                         goto fail;
 371
 372                 if (value == 0xdeadbeef) {
 373                         IFPGA_RAWDEV_PMD_ERR("sensor %s is invalid value %x\n",
 374                                         sensor->name, value);
 375                         continue;
 376                 }
 377
 378                 /* monitor temperature sensors */
 379                 if (!strcmp(sensor->name, "Board Temperature") ||
 380                                 !strcmp(sensor->name, "FPGA Die Temperature")) {
 381                         IFPGA_RAWDEV_PMD_INFO("read sensor %s %d %d %d\n",
 382                                         sensor->name, value, sensor->high_warn,
 383                                         sensor->high_fatal);
 384
 385                         if (HIGH_WARN(sensor, value) ||
 386                                 LOW_WARN(sensor, value)) {
 387                                 IFPGA_RAWDEV_PMD_INFO("%s reach theshold %d\n",
 388                                         sensor->name, value);
 389                                 *gsd_start = true;
 390                                 break;
 391                         }
 392                 }
 393
 394                 /* monitor 12V AUX sensor */
 395                 if (!strcmp(sensor->name, "12V AUX Voltage")) {
 396                         if (value < AUX_VOLTAGE_WARN) {
 397                                 IFPGA_RAWDEV_PMD_INFO("%s reach theshold %d\n",
 398                                                 sensor->name, value);
 399                                 *gsd_start = true;
 400                                 break;
 401                         }
 402                 }
 403         }
 404
 405         return 0;
 406 fail:
 407         return -EFAULT;
 408 }
 409
 410 static int set_surprise_link_check_aer(
 411         struct ifpga_rawdev *ifpga_rdev, int force_disable)
 412 {
 413         struct rte_rawdev *rdev;
 414         int fd = -1;
 415         char path[1024];
 416         int pos;
 417         int ret;
 418         uint32_t data;
 419         bool enable = 0;
 420         uint32_t aer_new0, aer_new1;
 421
 422         if (!ifpga_rdev) {
 423                 printf("\n device does not exist\n");
 424                 return -EFAULT;
 425         }
 426
 427         rdev = ifpga_rdev->rawdev;
 428         if (ifpga_rdev->aer_enable)
 429                 return -EFAULT;
 430         if (ifpga_monitor_sensor(rdev, &enable))
 431                 return -EFAULT;
 432         if (enable || force_disable) {
 433                 IFPGA_RAWDEV_PMD_ERR("Set AER, pls graceful shutdown\n");
 434                 ifpga_rdev->aer_enable = 1;
 435                 /* get bridge fd */
 436                 strlcpy(path, "/sys/bus/pci/devices/", sizeof(path));
 437                 strlcat(path, ifpga_rdev->parent_bdf, sizeof(path));
 438                 strlcat(path, "/config", sizeof(path));
 439                 fd = open(path, O_RDWR);
 440                 if (fd < 0)
 441                         goto end;
 442                 pos = ifpga_pci_find_ext_capability(fd, RTE_PCI_EXT_CAP_ID_ERR);
 443                 if (!pos)
 444                         goto end;
 445                 /* save previout ECAP_AER+0x08 */
 446                 ret = pread(fd, &data, sizeof(data), pos+0x08);
 447                 if (ret == -1)
 448                         goto end;
 449                 ifpga_rdev->aer_old[0] = data;
 450                 /* save previout ECAP_AER+0x14 */
 451                 ret = pread(fd, &data, sizeof(data), pos+0x14);
 452                 if (ret == -1)
 453                         goto end;
 454                 ifpga_rdev->aer_old[1] = data;
 455
 456                 /* set ECAP_AER+0x08 to 0xFFFFFFFF */
 457                 data = 0xffffffff;
 458                 ret = pwrite(fd, &data, 4, pos+0x08);
 459                 if (ret == -1)
 460                         goto end;
 461                 /* set ECAP_AER+0x14 to 0xFFFFFFFF */
 462                 ret = pwrite(fd, &data, 4, pos+0x14);
 463                 if (ret == -1)
 464                         goto end;
 465
 466                 /* read current ECAP_AER+0x08 */
 467                 ret = pread(fd, &data, sizeof(data), pos+0x08);
 468                 if (ret == -1)
 469                         goto end;
 470                 aer_new0 = data;
 471                 /* read current ECAP_AER+0x14 */
 472                 ret = pread(fd, &data, sizeof(data), pos+0x14);
 473                 if (ret == -1)
 474                         goto end;
 475                 aer_new1 = data;
 476
 477                 if (fd != -1)
 478                         close(fd);
 479
 480                 printf(">>>>>>Set AER %x,%x %x,%x\n",
 481                         ifpga_rdev->aer_old[0], ifpga_rdev->aer_old[1],
 482                         aer_new0, aer_new1);
 483
 484                 return 1;
 485                 }
 486
 487 end:
 488         if (fd != -1)
 489                 close(fd);
 490         return -EFAULT;
 491 }
 492
 493 static void *
 494 ifpga_rawdev_gsd_handle(__rte_unused void *param)
 495 {
 496         struct ifpga_rawdev *ifpga_rdev;
 497         int i;
 498         int gsd_enable, ret;
 499 #define MS 1000
 500
 501         while (1) {
 502                 gsd_enable = 0;
 503                 for (i = 0; i < IFPGA_RAWDEV_NUM; i++) {
 504                         ifpga_rdev = &ifpga_rawdevices[i];
 505                         if (ifpga_rdev->rawdev) {
 506                                 ret = set_surprise_link_check_aer(ifpga_rdev,
 507                                         gsd_enable);
 508                                 if (ret == 1 && !gsd_enable) {
 509                                         gsd_enable = 1;
 510                                         i = -1;
 511                                 }
 512                         }
 513                 }
 514
 515                 if (gsd_enable)
 516                         printf(">>>>>>Pls Shutdown APP\n");
 517
 518                 rte_delay_us(100 * MS);
 519         }
 520
 521         return NULL;
 522 }
 523
 524 static int
 525 ifpga_monitor_start_func(void)
 526 {
 527         int ret;
 528
 529         if (ifpga_monitor_start == 0) {
 530                 ret = pthread_create(&ifpga_monitor_start_thread,
 531                         NULL,
 532                         ifpga_rawdev_gsd_handle, NULL);
 533                 if (ret) {
 534                         IFPGA_RAWDEV_PMD_ERR(
 535                                 "Fail to create ifpga nonitor thread");
 536                         return -1;
 537                 }
 538                 ifpga_monitor_start = 1;
 539         }
 540
 541         return 0;
 542 }
 543 static int
 544 ifpga_monitor_stop_func(void)
 545 {
 546         int ret;
 547
 548         if (ifpga_monitor_start == 1) {
 549                 ret = pthread_cancel(ifpga_monitor_start_thread);
 550                 if (ret)
 551                         IFPGA_RAWDEV_PMD_ERR("Can't cancel the thread");
 552
 553                 ret = pthread_join(ifpga_monitor_start_thread, NULL);
 554                 if (ret)
 555                         IFPGA_RAWDEV_PMD_ERR("Can't join the thread");
 556
 557                 ifpga_monitor_start = 0;
 558
 559                 return ret;
 560         }
 561
 562         return 0;
 563 }
 564
 565 static int
 566 ifpga_fill_afu_dev(struct opae_accelerator *acc,
 567                 struct rte_afu_device *afu_dev)
 568 {
 569         struct rte_mem_resource *res = afu_dev->mem_resource;
 570         struct opae_acc_region_info region_info;
 571         struct opae_acc_info info;
 572         unsigned long i;
 573         int ret;
 574
 575         ret = opae_acc_get_info(acc, &info);
 576         if (ret)
 577                 return ret;
 578
 579         if (info.num_regions > PCI_MAX_RESOURCE)
 580                 return -EFAULT;
 581
 582         afu_dev->num_region = info.num_regions;
 583
 584         for (i = 0; i < info.num_regions; i++) {
 585                 region_info.index = i;
 586                 ret = opae_acc_get_region_info(acc, &region_info);
 587                 if (ret)
 588                         return ret;
 589
 590                 if ((region_info.flags & ACC_REGION_MMIO) &&
 591                     (region_info.flags & ACC_REGION_READ) &&
 592                     (region_info.flags & ACC_REGION_WRITE)) {
 593                         res[i].phys_addr = region_info.phys_addr;
 594                         res[i].len = region_info.len;
 595                         res[i].addr = region_info.addr;
 596                 } else
 597                         return -EFAULT;
 598         }
 599
 600         return 0;
 601 }
 602
 603 static void
 604 ifpga_rawdev_info_get(struct rte_rawdev *dev,
 605                                      rte_rawdev_obj_t dev_info)
 606 {
 607         struct opae_adapter *adapter;
 608         struct opae_accelerator *acc;
 609         struct rte_afu_device *afu_dev;
 610         struct opae_manager *mgr = NULL;
 611         struct opae_eth_group_region_info opae_lside_eth_info;
 612         struct opae_eth_group_region_info opae_nside_eth_info;
 613         int lside_bar_idx, nside_bar_idx;
 614
 615         IFPGA_RAWDEV_PMD_FUNC_TRACE();
 616
 617         if (!dev_info) {
 618                 IFPGA_RAWDEV_PMD_ERR("Invalid request");
 619                 return;
 620         }
 621
 622         adapter = ifpga_rawdev_get_priv(dev);
 623         if (!adapter)
 624                 return;
 625
 626         afu_dev = dev_info;
 627         afu_dev->rawdev = dev;
 628
 629         /* find opae_accelerator and fill info into afu_device */
 630         opae_adapter_for_each_acc(adapter, acc) {
 631                 if (acc->index != afu_dev->id.port)
 632                         continue;
 633
 634                 if (ifpga_fill_afu_dev(acc, afu_dev)) {
 635                         IFPGA_RAWDEV_PMD_ERR("cannot get info\n");
 636                         return;
 637                 }
 638         }
 639
 640         /* get opae_manager to rawdev */
 641         mgr = opae_adapter_get_mgr(adapter);
 642         if (mgr) {
 643                 /* get LineSide BAR Index */
 644                 if (opae_manager_get_eth_group_region_info(mgr, 0,
 645                         &opae_lside_eth_info)) {
 646                         return;
 647                 }
 648                 lside_bar_idx = opae_lside_eth_info.mem_idx;
 649
 650                 /* get NICSide BAR Index */
 651                 if (opae_manager_get_eth_group_region_info(mgr, 1,
 652                         &opae_nside_eth_info)) {
 653                         return;
 654                 }
 655                 nside_bar_idx = opae_nside_eth_info.mem_idx;
 656
 657                 if (lside_bar_idx >= PCI_MAX_RESOURCE ||
 658                         nside_bar_idx >= PCI_MAX_RESOURCE ||
 659                         lside_bar_idx == nside_bar_idx)
 660                         return;
 661
 662                 /* fill LineSide BAR Index */
 663                 afu_dev->mem_resource[lside_bar_idx].phys_addr =
 664                         opae_lside_eth_info.phys_addr;
 665                 afu_dev->mem_resource[lside_bar_idx].len =
 666                         opae_lside_eth_info.len;
 667                 afu_dev->mem_resource[lside_bar_idx].addr =
 668                         opae_lside_eth_info.addr;
 669
 670                 /* fill NICSide BAR Index */
 671                 afu_dev->mem_resource[nside_bar_idx].phys_addr =
 672                         opae_nside_eth_info.phys_addr;
 673                 afu_dev->mem_resource[nside_bar_idx].len =
 674                         opae_nside_eth_info.len;
 675                 afu_dev->mem_resource[nside_bar_idx].addr =
 676                         opae_nside_eth_info.addr;
 677         }
 678 }
 679
 680 static int
 681 ifpga_rawdev_configure(const struct rte_rawdev *dev,
 682                 rte_rawdev_obj_t config)
 683 {
 684         IFPGA_RAWDEV_PMD_FUNC_TRACE();
 685
 686         RTE_FUNC_PTR_OR_ERR_RET(dev, -EINVAL);
 687
 688         return config ? 0 : 1;
 689 }
 690
 691 static int
 692 ifpga_rawdev_start(struct rte_rawdev *dev)
 693 {
 694         int ret = 0;
 695         struct opae_adapter *adapter;
 696
 697         IFPGA_RAWDEV_PMD_FUNC_TRACE();
 698
 699         RTE_FUNC_PTR_OR_ERR_RET(dev, -EINVAL);
 700
 701         adapter = ifpga_rawdev_get_priv(dev);
 702         if (!adapter)
 703                 return -ENODEV;
 704
 705         return ret;
 706 }
 707
 708 static void
 709 ifpga_rawdev_stop(struct rte_rawdev *dev)
 710 {
 711         dev->started = 0;
 712 }
 713
 714 static int
 715 ifpga_rawdev_close(struct rte_rawdev *dev)
 716 {
 717         return dev ? 0:1;
 718 }
 719
 720 static int
 721 ifpga_rawdev_reset(struct rte_rawdev *dev)
 722 {
 723         return dev ? 0:1;
 724 }
 725
 726 static int
 727 fpga_pr(struct rte_rawdev *raw_dev, u32 port_id, const char *buffer, u32 size,
 728                         u64 *status)
 729 {
 730
 731         struct opae_adapter *adapter;
 732         struct opae_manager *mgr;
 733         struct opae_accelerator *acc;
 734         struct opae_bridge *br;
 735         int ret;
 736
 737         adapter = ifpga_rawdev_get_priv(raw_dev);
 738         if (!adapter)
 739                 return -ENODEV;
 740
 741         mgr = opae_adapter_get_mgr(adapter);
 742         if (!mgr)
 743                 return -ENODEV;
 744
 745         acc = opae_adapter_get_acc(adapter, port_id);
 746         if (!acc)
 747                 return -ENODEV;
 748
 749         br = opae_acc_get_br(acc);
 750         if (!br)
 751                 return -ENODEV;
 752
 753         ret = opae_manager_flash(mgr, port_id, buffer, size, status);
 754         if (ret) {
 755                 IFPGA_RAWDEV_PMD_ERR("%s pr error %d\n", __func__, ret);
 756                 return ret;
 757         }
 758
 759         ret = opae_bridge_reset(br);
 760         if (ret) {
 761                 IFPGA_RAWDEV_PMD_ERR("%s reset port:%d error %d\n",
 762                                 __func__, port_id, ret);
 763                 return ret;
 764         }
 765
 766         return ret;
 767 }
 768
 769 static int
 770 rte_fpga_do_pr(struct rte_rawdev *rawdev, int port_id,
 771                 const char *file_name)
 772 {
 773         struct stat file_stat;
 774         int file_fd;
 775         int ret = 0;
 776         ssize_t buffer_size;
 777         void *buffer;
 778         u64 pr_error;
 779
 780         if (!file_name)
 781                 return -EINVAL;
 782
 783         file_fd = open(file_name, O_RDONLY);
 784         if (file_fd < 0) {
 785                 IFPGA_RAWDEV_PMD_ERR("%s: open file error: %s\n",
 786                                 __func__, file_name);
 787                 IFPGA_RAWDEV_PMD_ERR("Message : %s\n", strerror(errno));
 788                 return -EINVAL;
 789         }
 790         ret = stat(file_name, &file_stat);
 791         if (ret) {
 792                 IFPGA_RAWDEV_PMD_ERR("stat on bitstream file failed: %s\n",
 793                                 file_name);
 794                 ret = -EINVAL;
 795                 goto close_fd;
 796         }
 797         buffer_size = file_stat.st_size;
 798         if (buffer_size <= 0) {
 799                 ret = -EINVAL;
 800                 goto close_fd;
 801         }
 802
 803         IFPGA_RAWDEV_PMD_INFO("bitstream file size: %zu\n", buffer_size);
 804         buffer = rte_malloc(NULL, buffer_size, 0);
 805         if (!buffer) {
 806                 ret = -ENOMEM;
 807                 goto close_fd;
 808         }
 809
 810         /*read the raw data*/
 811         if (buffer_size != read(file_fd, (void *)buffer, buffer_size)) {
 812                 ret = -EINVAL;
 813                 goto free_buffer;
 814         }
 815
 816         /*do PR now*/
 817         ret = fpga_pr(rawdev, port_id, buffer, buffer_size, &pr_error);
 818         IFPGA_RAWDEV_PMD_INFO("downloading to device port %d....%s.\n", port_id,
 819                 ret ? "failed" : "success");
 820         if (ret) {
 821                 ret = -EINVAL;
 822                 goto free_buffer;
 823         }
 824
 825 free_buffer:
 826         if (buffer)
 827                 rte_free(buffer);
 828 close_fd:
 829         close(file_fd);
 830         file_fd = 0;
 831         return ret;
 832 }
 833
 834 static int
 835 ifpga_rawdev_pr(struct rte_rawdev *dev,
 836         rte_rawdev_obj_t pr_conf)
 837 {
 838         struct opae_adapter *adapter;
 839         struct rte_afu_pr_conf *afu_pr_conf;
 840         int ret;
 841         struct uuid uuid;
 842         struct opae_accelerator *acc;
 843
 844         IFPGA_RAWDEV_PMD_FUNC_TRACE();
 845
 846         adapter = ifpga_rawdev_get_priv(dev);
 847         if (!adapter)
 848                 return -ENODEV;
 849
 850         if (!pr_conf)
 851                 return -EINVAL;
 852
 853         afu_pr_conf = pr_conf;
 854
 855         if (afu_pr_conf->pr_enable) {
 856                 ret = rte_fpga_do_pr(dev,
 857                                 afu_pr_conf->afu_id.port,
 858                                 afu_pr_conf->bs_path);
 859                 if (ret) {
 860                         IFPGA_RAWDEV_PMD_ERR("do pr error %d\n", ret);
 861                         return ret;
 862                 }
 863         }
 864
 865         acc = opae_adapter_get_acc(adapter, afu_pr_conf->afu_id.port);
 866         if (!acc)
 867                 return -ENODEV;
 868
 869         ret = opae_acc_get_uuid(acc, &uuid);
 870         if (ret)
 871                 return ret;
 872
 873         rte_memcpy(&afu_pr_conf->afu_id.uuid.uuid_low, uuid.b, sizeof(u64));
 874         rte_memcpy(&afu_pr_conf->afu_id.uuid.uuid_high,
 875                 uuid.b + 8, sizeof(u64));
 876
 877         IFPGA_RAWDEV_PMD_INFO("%s: uuid_l=0x%lx, uuid_h=0x%lx\n", __func__,
 878                 (unsigned long)afu_pr_conf->afu_id.uuid.uuid_low,
 879                 (unsigned long)afu_pr_conf->afu_id.uuid.uuid_high);
 880
 881         return 0;
 882 }
 883
 884 static int
 885 ifpga_rawdev_get_attr(struct rte_rawdev *dev,
 886         const char *attr_name, uint64_t *attr_value)
 887 {
 888         struct opae_adapter *adapter;
 889         struct opae_manager *mgr;
 890         struct opae_retimer_info opae_rtm_info;
 891         struct opae_retimer_status opae_rtm_status;
 892         struct opae_eth_group_info opae_eth_grp_info;
 893         struct opae_eth_group_region_info opae_eth_grp_reg_info;
 894         int eth_group_num = 0;
 895         uint64_t port_link_bitmap = 0, port_link_bit;
 896         uint32_t i, j, p, q;
 897
 898 #define MAX_PORT_PER_RETIMER    4
 899
 900         IFPGA_RAWDEV_PMD_FUNC_TRACE();
 901
 902         if (!dev || !attr_name || !attr_value) {
 903                 IFPGA_RAWDEV_PMD_ERR("Invalid arguments for getting attributes");
 904                 return -1;
 905         }
 906
 907         adapter = ifpga_rawdev_get_priv(dev);
 908         if (!adapter) {
 909                 IFPGA_RAWDEV_PMD_ERR("Adapter of dev %s is NULL", dev->name);
 910                 return -1;
 911         }
 912
 913         mgr = opae_adapter_get_mgr(adapter);
 914         if (!mgr) {
 915                 IFPGA_RAWDEV_PMD_ERR("opae_manager of opae_adapter is NULL");
 916                 return -1;
 917         }
 918
 919         /* currently, eth_group_num is always 2 */
 920         eth_group_num = opae_manager_get_eth_group_nums(mgr);
 921         if (eth_group_num < 0)
 922                 return -1;
 923
 924         if (!strcmp(attr_name, "LineSideBaseMAC")) {
 925                 /* Currently FPGA not implement, so just set all zeros*/
 926                 *attr_value = (uint64_t)0;
 927                 return 0;
 928         }
 929         if (!strcmp(attr_name, "LineSideMACType")) {
 930                 /* eth_group 0 on FPGA connect to LineSide */
 931                 if (opae_manager_get_eth_group_info(mgr, 0,
 932                         &opae_eth_grp_info))
 933                         return -1;
 934                 switch (opae_eth_grp_info.speed) {
 935                 case ETH_SPEED_10G:
 936                         *attr_value =
 937                         (uint64_t)(IFPGA_RAWDEV_RETIMER_MAC_TYPE_10GE_XFI);
 938                         break;
 939                 case ETH_SPEED_25G:
 940                         *attr_value =
 941                         (uint64_t)(IFPGA_RAWDEV_RETIMER_MAC_TYPE_25GE_25GAUI);
 942                         break;
 943                 default:
 944                         *attr_value =
 945                         (uint64_t)(IFPGA_RAWDEV_RETIMER_MAC_TYPE_UNKNOWN);
 946                         break;
 947                 }
 948                 return 0;
 949         }
 950         if (!strcmp(attr_name, "LineSideLinkSpeed")) {
 951                 if (opae_manager_get_retimer_status(mgr, &opae_rtm_status))
 952                         return -1;
 953                 switch (opae_rtm_status.speed) {
 954                 case MXD_1GB:
 955                         *attr_value =
 956                                 (uint64_t)(IFPGA_RAWDEV_LINK_SPEED_UNKNOWN);
 957                         break;
 958                 case MXD_2_5GB:
 959                         *attr_value =
 960                                 (uint64_t)(IFPGA_RAWDEV_LINK_SPEED_UNKNOWN);
 961                         break;
 962                 case MXD_5GB:
 963                         *attr_value =
 964                                 (uint64_t)(IFPGA_RAWDEV_LINK_SPEED_UNKNOWN);
 965                         break;
 966                 case MXD_10GB:
 967                         *attr_value =
 968                                 (uint64_t)(IFPGA_RAWDEV_LINK_SPEED_10GB);
 969                         break;
 970                 case MXD_25GB:
 971                         *attr_value =
 972                                 (uint64_t)(IFPGA_RAWDEV_LINK_SPEED_25GB);
 973                         break;
 974                 case MXD_40GB:
 975                         *attr_value =
 976                                 (uint64_t)(IFPGA_RAWDEV_LINK_SPEED_40GB);
 977                         break;
 978                 case MXD_100GB:
 979                         *attr_value =
 980                                 (uint64_t)(IFPGA_RAWDEV_LINK_SPEED_UNKNOWN);
 981                         break;
 982                 case MXD_SPEED_UNKNOWN:
 983                         *attr_value =
 984                                 (uint64_t)(IFPGA_RAWDEV_LINK_SPEED_UNKNOWN);
 985                         break;
 986                 default:
 987                         *attr_value =
 988                                 (uint64_t)(IFPGA_RAWDEV_LINK_SPEED_UNKNOWN);
 989                         break;
 990                 }
 991                 return 0;
 992         }
 993         if (!strcmp(attr_name, "LineSideLinkRetimerNum")) {
 994                 if (opae_manager_get_retimer_info(mgr, &opae_rtm_info))
 995                         return -1;
 996                 *attr_value = (uint64_t)(opae_rtm_info.nums_retimer);
 997                 return 0;
 998         }
 999         if (!strcmp(attr_name, "LineSideLinkPortNum")) {
1000                 if (opae_manager_get_retimer_info(mgr, &opae_rtm_info))
1001                         return -1;
1002                 uint64_t tmp = (uint64_t)opae_rtm_info.ports_per_retimer *
1003                                         (uint64_t)opae_rtm_info.nums_retimer;
1004                 *attr_value = tmp;
1005                 return 0;
1006         }
1007         if (!strcmp(attr_name, "LineSideLinkStatus")) {
1008                 if (opae_manager_get_retimer_info(mgr, &opae_rtm_info))
1009                         return -1;
1010                 if (opae_manager_get_retimer_status(mgr, &opae_rtm_status))
1011                         return -1;
1012                 (*attr_value) = 0;
1013                 q = 0;
1014                 port_link_bitmap = (uint64_t)(opae_rtm_status.line_link_bitmap);
1015                 for (i = 0; i < opae_rtm_info.nums_retimer; i++) {
1016                         p = i * MAX_PORT_PER_RETIMER;
1017                         for (j = 0; j < opae_rtm_info.ports_per_retimer; j++) {
1018                                 port_link_bit = 0;
1019                                 IFPGA_BIT_SET(port_link_bit, (p+j));
1020                                 port_link_bit &= port_link_bitmap;
1021                                 if (port_link_bit)
1022                                         IFPGA_BIT_SET((*attr_value), q);
1023                                 q++;
1024                         }
1025                 }
1026                 return 0;
1027         }
1028         if (!strcmp(attr_name, "LineSideBARIndex")) {
1029                 /* eth_group 0 on FPGA connect to LineSide */
1030                 if (opae_manager_get_eth_group_region_info(mgr, 0,
1031                         &opae_eth_grp_reg_info))
1032                         return -1;
1033                 *attr_value = (uint64_t)opae_eth_grp_reg_info.mem_idx;
1034                 return 0;
1035         }
1036         if (!strcmp(attr_name, "NICSideMACType")) {
1037                 /* eth_group 1 on FPGA connect to NicSide */
1038                 if (opae_manager_get_eth_group_info(mgr, 1,
1039                         &opae_eth_grp_info))
1040                         return -1;
1041                 *attr_value = (uint64_t)(opae_eth_grp_info.speed);
1042                 return 0;
1043         }
1044         if (!strcmp(attr_name, "NICSideLinkSpeed")) {
1045                 /* eth_group 1 on FPGA connect to NicSide */
1046                 if (opae_manager_get_eth_group_info(mgr, 1,
1047                         &opae_eth_grp_info))
1048                         return -1;
1049                 *attr_value = (uint64_t)(opae_eth_grp_info.speed);
1050                 return 0;
1051         }
1052         if (!strcmp(attr_name, "NICSideLinkPortNum")) {
1053                 if (opae_manager_get_retimer_info(mgr, &opae_rtm_info))
1054                         return -1;
1055                 uint64_t tmp = (uint64_t)opae_rtm_info.nums_fvl *
1056                                         (uint64_t)opae_rtm_info.ports_per_fvl;
1057                 *attr_value = tmp;
1058                 return 0;
1059         }
1060         if (!strcmp(attr_name, "NICSideLinkStatus"))
1061                 return 0;
1062         if (!strcmp(attr_name, "NICSideBARIndex")) {
1063                 /* eth_group 1 on FPGA connect to NicSide */
1064                 if (opae_manager_get_eth_group_region_info(mgr, 1,
1065                         &opae_eth_grp_reg_info))
1066                         return -1;
1067                 *attr_value = (uint64_t)opae_eth_grp_reg_info.mem_idx;
1068                 return 0;
1069         }
1070
1071         IFPGA_RAWDEV_PMD_ERR("%s not support", attr_name);
1072         return -1;
1073 }
1074
1075 static const struct rte_rawdev_ops ifpga_rawdev_ops = {
1076         .dev_info_get = ifpga_rawdev_info_get,
1077         .dev_configure = ifpga_rawdev_configure,
1078         .dev_start = ifpga_rawdev_start,
1079         .dev_stop = ifpga_rawdev_stop,
1080         .dev_close = ifpga_rawdev_close,
1081         .dev_reset = ifpga_rawdev_reset,
1082
1083         .queue_def_conf = NULL,
1084         .queue_setup = NULL,
1085         .queue_release = NULL,
1086
1087         .attr_get = ifpga_rawdev_get_attr,
1088         .attr_set = NULL,
1089
1090         .enqueue_bufs = NULL,
1091         .dequeue_bufs = NULL,
1092
1093         .dump = NULL,
1094
1095         .xstats_get = NULL,
1096         .xstats_get_names = NULL,
1097         .xstats_get_by_name = NULL,
1098         .xstats_reset = NULL,
1099
1100         .firmware_status_get = NULL,
1101         .firmware_version_get = NULL,
1102         .firmware_load = ifpga_rawdev_pr,
1103         .firmware_unload = NULL,
1104
1105         .dev_selftest = NULL,
1106 };
1107
1108 static int
1109 ifpga_get_fme_error_prop(struct opae_manager *mgr,
1110                 u64 prop_id, u64 *val)
1111 {
1112         struct feature_prop prop;
1113
1114         prop.feature_id = IFPGA_FME_FEATURE_ID_GLOBAL_ERR;
1115         prop.prop_id = prop_id;
1116
1117         if (opae_manager_ifpga_get_prop(mgr, &prop))
1118                 return -EINVAL;
1119
1120         *val = prop.data;
1121
1122         return 0;
1123 }
1124
1125 static int
1126 ifpga_set_fme_error_prop(struct opae_manager *mgr,
1127                 u64 prop_id, u64 val)
1128 {
1129         struct feature_prop prop;
1130
1131         prop.feature_id = IFPGA_FME_FEATURE_ID_GLOBAL_ERR;
1132         prop.prop_id = prop_id;
1133
1134         prop.data = val;
1135
1136         if (opae_manager_ifpga_set_prop(mgr, &prop))
1137                 return -EINVAL;
1138
1139         return 0;
1140 }
1141
1142 static int
1143 fme_err_read_seu_emr(struct opae_manager *mgr)
1144 {
1145         u64 val;
1146         int ret;
1147
1148         ret = ifpga_get_fme_error_prop(mgr, FME_ERR_PROP_SEU_EMR_LOW, &val);
1149         if (ret)
1150                 return -EINVAL;
1151
1152         IFPGA_RAWDEV_PMD_INFO("seu emr low: 0x%" PRIx64 "\n", val);
1153
1154         ret = ifpga_get_fme_error_prop(mgr, FME_ERR_PROP_SEU_EMR_HIGH, &val);
1155         if (ret)
1156                 return -EINVAL;
1157
1158         IFPGA_RAWDEV_PMD_INFO("seu emr high: 0x%" PRIx64 "\n", val);
1159
1160         return 0;
1161 }
1162
1163 static int fme_clear_warning_intr(struct opae_manager *mgr)
1164 {
1165         u64 val;
1166
1167         if (ifpga_set_fme_error_prop(mgr, FME_ERR_PROP_INJECT_ERRORS, 0))
1168                 return -EINVAL;
1169
1170         if (ifpga_get_fme_error_prop(mgr, FME_ERR_PROP_NONFATAL_ERRORS, &val))
1171                 return -EINVAL;
1172         if ((val & 0x40) != 0)
1173                 IFPGA_RAWDEV_PMD_INFO("clean not done\n");
1174
1175         return 0;
1176 }
1177
1178 static int
1179 fme_err_handle_error0(struct opae_manager *mgr)
1180 {
1181         struct feature_fme_error0 fme_error0;
1182         u64 val;
1183
1184         if (ifpga_get_fme_error_prop(mgr, FME_ERR_PROP_ERRORS, &val))
1185                 return -EINVAL;
1186
1187         fme_error0.csr = val;
1188
1189         if (fme_error0.fabric_err)
1190                 IFPGA_RAWDEV_PMD_ERR("Fabric error\n");
1191         else if (fme_error0.fabfifo_overflow)
1192                 IFPGA_RAWDEV_PMD_ERR("Fabric fifo under/overflow error\n");
1193         else if (fme_error0.afu_acc_mode_err)
1194                 IFPGA_RAWDEV_PMD_ERR("AFU PF/VF access mismatch detected\n");
1195         else if (fme_error0.pcie0cdc_parity_err)
1196                 IFPGA_RAWDEV_PMD_ERR("PCIe0 CDC Parity Error\n");
1197         else if (fme_error0.cvlcdc_parity_err)
1198                 IFPGA_RAWDEV_PMD_ERR("CVL CDC Parity Error\n");
1199         else if (fme_error0.fpgaseuerr)
1200                 fme_err_read_seu_emr(mgr);
1201
1202         /* clean the errors */
1203         if (ifpga_set_fme_error_prop(mgr, FME_ERR_PROP_ERRORS, val))
1204                 return -EINVAL;
1205
1206         return 0;
1207 }
1208
1209 static int
1210 fme_err_handle_catfatal_error(struct opae_manager *mgr)
1211 {
1212         struct feature_fme_ras_catfaterror fme_catfatal;
1213         u64 val;
1214
1215         if (ifpga_get_fme_error_prop(mgr, FME_ERR_PROP_CATFATAL_ERRORS, &val))
1216                 return -EINVAL;
1217
1218         fme_catfatal.csr = val;
1219
1220         if (fme_catfatal.cci_fatal_err)
1221                 IFPGA_RAWDEV_PMD_ERR("CCI error detected\n");
1222         else if (fme_catfatal.fabric_fatal_err)
1223                 IFPGA_RAWDEV_PMD_ERR("Fabric fatal error detected\n");
1224         else if (fme_catfatal.pcie_poison_err)
1225                 IFPGA_RAWDEV_PMD_ERR("Poison error from PCIe ports\n");
1226         else if (fme_catfatal.inject_fata_err)
1227                 IFPGA_RAWDEV_PMD_ERR("Injected Fatal Error\n");
1228         else if (fme_catfatal.crc_catast_err)
1229                 IFPGA_RAWDEV_PMD_ERR("a catastrophic EDCRC error\n");
1230         else if (fme_catfatal.injected_catast_err)
1231                 IFPGA_RAWDEV_PMD_ERR("Injected Catastrophic Error\n");
1232         else if (fme_catfatal.bmc_seu_catast_err)
1233                 fme_err_read_seu_emr(mgr);
1234
1235         return 0;
1236 }
1237
1238 static int
1239 fme_err_handle_nonfaterror(struct opae_manager *mgr)
1240 {
1241         struct feature_fme_ras_nonfaterror nonfaterr;
1242         u64 val;
1243
1244         if (ifpga_get_fme_error_prop(mgr, FME_ERR_PROP_NONFATAL_ERRORS, &val))
1245                 return -EINVAL;
1246
1247         nonfaterr.csr = val;
1248
1249         if (nonfaterr.temp_thresh_ap1)
1250                 IFPGA_RAWDEV_PMD_INFO("Temperature threshold triggered AP1\n");
1251         else if (nonfaterr.temp_thresh_ap2)
1252                 IFPGA_RAWDEV_PMD_INFO("Temperature threshold triggered AP2\n");
1253         else if (nonfaterr.pcie_error)
1254                 IFPGA_RAWDEV_PMD_INFO("an error has occurred in pcie\n");
1255         else if (nonfaterr.portfatal_error)
1256                 IFPGA_RAWDEV_PMD_INFO("fatal error occurred in AFU port.\n");
1257         else if (nonfaterr.proc_hot)
1258                 IFPGA_RAWDEV_PMD_INFO("a ProcHot event\n");
1259         else if (nonfaterr.afu_acc_mode_err)
1260                 IFPGA_RAWDEV_PMD_INFO("an AFU PF/VF access mismatch\n");
1261         else if (nonfaterr.injected_nonfata_err) {
1262                 IFPGA_RAWDEV_PMD_INFO("Injected Warning Error\n");
1263                 fme_clear_warning_intr(mgr);
1264         } else if (nonfaterr.temp_thresh_AP6)
1265                 IFPGA_RAWDEV_PMD_INFO("Temperature threshold triggered AP6\n");
1266         else if (nonfaterr.power_thresh_AP1)
1267                 IFPGA_RAWDEV_PMD_INFO("Power threshold triggered AP1\n");
1268         else if (nonfaterr.power_thresh_AP2)
1269                 IFPGA_RAWDEV_PMD_INFO("Power threshold triggered AP2\n");
1270         else if (nonfaterr.mbp_err)
1271                 IFPGA_RAWDEV_PMD_INFO("an MBP event\n");
1272
1273         return 0;
1274 }
1275
1276 static void
1277 fme_interrupt_handler(void *param)
1278 {
1279         struct opae_manager *mgr = (struct opae_manager *)param;
1280
1281         IFPGA_RAWDEV_PMD_INFO("%s interrupt occurred\n", __func__);
1282
1283         fme_err_handle_error0(mgr);
1284         fme_err_handle_nonfaterror(mgr);
1285         fme_err_handle_catfatal_error(mgr);
1286 }
1287
1288 static struct rte_intr_handle fme_intr_handle;
1289
1290 static int ifpga_register_fme_interrupt(struct opae_manager *mgr)
1291 {
1292         int ret;
1293         struct fpga_fme_err_irq_set err_irq_set;
1294
1295         fme_intr_handle.type = RTE_INTR_HANDLE_VFIO_MSIX;
1296
1297         ret = rte_intr_efd_enable(&fme_intr_handle, 1);
1298         if (ret)
1299                 return -EINVAL;
1300
1301         fme_intr_handle.fd = fme_intr_handle.efds[0];
1302
1303         IFPGA_RAWDEV_PMD_DEBUG("vfio_dev_fd=%d, efd=%d, fd=%d\n",
1304                         fme_intr_handle.vfio_dev_fd,
1305                         fme_intr_handle.efds[0], fme_intr_handle.fd);
1306
1307         err_irq_set.evtfd = fme_intr_handle.efds[0];
1308         ret = opae_manager_ifpga_set_err_irq(mgr, &err_irq_set);
1309         if (ret)
1310                 return -EINVAL;
1311
1312         /* register FME interrupt using DPDK API */
1313         ret = rte_intr_callback_register(&fme_intr_handle,
1314                         fme_interrupt_handler,
1315                         (void *)mgr);
1316         if (ret)
1317                 return -EINVAL;
1318
1319         IFPGA_RAWDEV_PMD_INFO("success register fme interrupt\n");
1320
1321         return 0;
1322 }
1323
1324 static int
1325 ifpga_unregister_fme_interrupt(struct opae_manager *mgr)
1326 {
1327         rte_intr_efd_disable(&fme_intr_handle);
1328
1329         return rte_intr_callback_unregister(&fme_intr_handle,
1330                         fme_interrupt_handler,
1331                         (void *)mgr);
1332 }
1333
1334 static int
1335 ifpga_rawdev_create(struct rte_pci_device *pci_dev,
1336                         int socket_id)
1337 {
1338         int ret = 0;
1339         struct rte_rawdev *rawdev = NULL;
1340         struct ifpga_rawdev *dev = NULL;
1341         struct opae_adapter *adapter = NULL;
1342         struct opae_manager *mgr = NULL;
1343         struct opae_adapter_data_pci *data = NULL;
1344         char name[RTE_RAWDEV_NAME_MAX_LEN];
1345         int i;
1346
1347         if (!pci_dev) {
1348                 IFPGA_RAWDEV_PMD_ERR("Invalid pci_dev of the device!");
1349                 ret = -EINVAL;
1350                 goto cleanup;
1351         }
1352
1353         memset(name, 0, sizeof(name));
1354         snprintf(name, RTE_RAWDEV_NAME_MAX_LEN, "IFPGA:%02x:%02x.%x",
1355                 pci_dev->addr.bus, pci_dev->addr.devid, pci_dev->addr.function);
1356
1357         IFPGA_RAWDEV_PMD_INFO("Init %s on NUMA node %d", name, rte_socket_id());
1358
1359         /* Allocate device structure */
1360         rawdev = rte_rawdev_pmd_allocate(name, sizeof(struct opae_adapter),
1361                                          socket_id);
1362         if (rawdev == NULL) {
1363                 IFPGA_RAWDEV_PMD_ERR("Unable to allocate rawdevice");
1364                 ret = -EINVAL;
1365                 goto cleanup;
1366         }
1367
1368         ipn3ke_bridge_func.get_ifpga_rawdev = ifpga_rawdev_get;
1369         ipn3ke_bridge_func.set_i40e_sw_dev = rte_pmd_i40e_set_switch_dev;
1370
1371         dev = ifpga_rawdev_allocate(rawdev);
1372         if (dev == NULL) {
1373                 IFPGA_RAWDEV_PMD_ERR("Unable to allocate ifpga_rawdevice");
1374                 ret = -EINVAL;
1375                 goto cleanup;
1376         }
1377         dev->aer_enable = 0;
1378
1379         /* alloc OPAE_FPGA_PCI data to register to OPAE hardware level API */
1380         data = opae_adapter_data_alloc(OPAE_FPGA_PCI);
1381         if (!data) {
1382                 ret = -ENOMEM;
1383                 goto cleanup;
1384         }
1385
1386         /* init opae_adapter_data_pci for device specific information */
1387         for (i = 0; i < PCI_MAX_RESOURCE; i++) {
1388                 data->region[i].phys_addr = pci_dev->mem_resource[i].phys_addr;
1389                 data->region[i].len = pci_dev->mem_resource[i].len;
1390                 data->region[i].addr = pci_dev->mem_resource[i].addr;
1391         }
1392         data->device_id = pci_dev->id.device_id;
1393         data->vendor_id = pci_dev->id.vendor_id;
1394         data->vfio_dev_fd = pci_dev->intr_handle.vfio_dev_fd;
1395
1396         adapter = rawdev->dev_private;
1397         /* create a opae_adapter based on above device data */
1398         ret = opae_adapter_init(adapter, pci_dev->device.name, data);
1399         if (ret) {
1400                 ret = -ENOMEM;
1401                 goto free_adapter_data;
1402         }
1403
1404         rawdev->dev_ops = &ifpga_rawdev_ops;
1405         rawdev->device = &pci_dev->device;
1406         rawdev->driver_name = pci_dev->driver->driver.name;
1407
1408         /* must enumerate the adapter before use it */
1409         ret = opae_adapter_enumerate(adapter);
1410         if (ret)
1411                 goto free_adapter_data;
1412
1413         /* get opae_manager to rawdev */
1414         mgr = opae_adapter_get_mgr(adapter);
1415         if (mgr) {
1416                 /* PF function */
1417                 IFPGA_RAWDEV_PMD_INFO("this is a PF function");
1418         }
1419
1420         ret = ifpga_register_fme_interrupt(mgr);
1421         if (ret)
1422                 goto free_adapter_data;
1423
1424         return ret;
1425
1426 free_adapter_data:
1427         if (data)
1428                 opae_adapter_data_free(data);
1429 cleanup:
1430         if (rawdev)
1431                 rte_rawdev_pmd_release(rawdev);
1432
1433         return ret;
1434 }
1435
1436 static int
1437 ifpga_rawdev_destroy(struct rte_pci_device *pci_dev)
1438 {
1439         int ret;
1440         struct rte_rawdev *rawdev;
1441         char name[RTE_RAWDEV_NAME_MAX_LEN];
1442         struct opae_adapter *adapter;
1443         struct opae_manager *mgr;
1444
1445         if (!pci_dev) {
1446                 IFPGA_RAWDEV_PMD_ERR("Invalid pci_dev of the device!");
1447                 ret = -EINVAL;
1448                 return ret;
1449         }
1450
1451         memset(name, 0, sizeof(name));
1452         snprintf(name, RTE_RAWDEV_NAME_MAX_LEN, "IFPGA:%x:%02x.%x",
1453                 pci_dev->addr.bus, pci_dev->addr.devid, pci_dev->addr.function);
1454
1455         IFPGA_RAWDEV_PMD_INFO("Closing %s on NUMA node %d",
1456                 name, rte_socket_id());
1457
1458         rawdev = rte_rawdev_pmd_get_named_dev(name);
1459         if (!rawdev) {
1460                 IFPGA_RAWDEV_PMD_ERR("Invalid device name (%s)", name);
1461                 return -EINVAL;
1462         }
1463
1464         adapter = ifpga_rawdev_get_priv(rawdev);
1465         if (!adapter)
1466                 return -ENODEV;
1467
1468         mgr = opae_adapter_get_mgr(adapter);
1469         if (!mgr)
1470                 return -ENODEV;
1471
1472         if (ifpga_unregister_fme_interrupt(mgr))
1473                 return -EINVAL;
1474
1475         opae_adapter_data_free(adapter->data);
1476         opae_adapter_free(adapter);
1477
1478         /* rte_rawdev_close is called by pmd_release */
1479         ret = rte_rawdev_pmd_release(rawdev);
1480         if (ret)
1481                 IFPGA_RAWDEV_PMD_DEBUG("Device cleanup failed");
1482
1483         return ret;
1484 }
1485
1486 static int
1487 ifpga_rawdev_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1488         struct rte_pci_device *pci_dev)
1489 {
1490         IFPGA_RAWDEV_PMD_FUNC_TRACE();
1491         return ifpga_rawdev_create(pci_dev, rte_socket_id());
1492 }
1493
1494 static int
1495 ifpga_rawdev_pci_remove(struct rte_pci_device *pci_dev)
1496 {
1497         ifpga_monitor_stop_func();
1498         return ifpga_rawdev_destroy(pci_dev);
1499 }
1500
1501 static struct rte_pci_driver rte_ifpga_rawdev_pmd = {
1502         .id_table  = pci_ifpga_map,
1503         .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
1504         .probe     = ifpga_rawdev_pci_probe,
1505         .remove    = ifpga_rawdev_pci_remove,
1506 };
1507
1508 RTE_PMD_REGISTER_PCI(ifpga_rawdev_pci_driver, rte_ifpga_rawdev_pmd);
1509 RTE_PMD_REGISTER_PCI_TABLE(ifpga_rawdev_pci_driver, rte_ifpga_rawdev_pmd);
1510 RTE_PMD_REGISTER_KMOD_DEP(ifpga_rawdev_pci_driver, "* igb_uio | uio_pci_generic | vfio-pci");
1511
1512 RTE_INIT(ifpga_rawdev_init_log)
1513 {
1514         ifpga_rawdev_logtype = rte_log_register("driver.raw.init");
1515         if (ifpga_rawdev_logtype >= 0)
1516                 rte_log_set_level(ifpga_rawdev_logtype, RTE_LOG_NOTICE);
1517 }
1518
1519 static const char * const valid_args[] = {
1520 #define IFPGA_ARG_NAME         "ifpga"
1521         IFPGA_ARG_NAME,
1522 #define IFPGA_ARG_PORT         "port"
1523         IFPGA_ARG_PORT,
1524 #define IFPGA_AFU_BTS          "afu_bts"
1525         IFPGA_AFU_BTS,
1526         NULL
1527 };
1528
1529 static int ifpga_rawdev_get_string_arg(const char *key __rte_unused,
1530         const char *value, void *extra_args)
1531 {
1532         int size;
1533         if (!value || !extra_args)
1534                 return -EINVAL;
1535
1536         size = strlen(value) + 1;
1537         *(char **)extra_args = rte_malloc(NULL, size, RTE_CACHE_LINE_SIZE);
1538         if (!*(char **)extra_args)
1539                 return -ENOMEM;
1540
1541         strlcpy(*(char **)extra_args, value, size);
1542
1543         return 0;
1544 }
1545 static int
1546 ifpga_cfg_probe(struct rte_vdev_device *dev)
1547 {
1548         struct rte_devargs *devargs;
1549         struct rte_kvargs *kvlist = NULL;
1550         struct rte_rawdev *rawdev = NULL;
1551         struct ifpga_rawdev *ifpga_dev;
1552         int port;
1553         char *name = NULL;
1554         const char *bdf;
1555         char dev_name[RTE_RAWDEV_NAME_MAX_LEN];
1556         int ret = -1;
1557
1558         devargs = dev->device.devargs;
1559
1560         kvlist = rte_kvargs_parse(devargs->args, valid_args);
1561         if (!kvlist) {
1562                 IFPGA_RAWDEV_PMD_LOG(ERR, "error when parsing param");
1563                 goto end;
1564         }
1565
1566         if (rte_kvargs_count(kvlist, IFPGA_ARG_NAME) == 1) {
1567                 if (rte_kvargs_process(kvlist, IFPGA_ARG_NAME,
1568                                        &ifpga_rawdev_get_string_arg,
1569                                        &name) < 0) {
1570                         IFPGA_RAWDEV_PMD_ERR("error to parse %s",
1571                                      IFPGA_ARG_NAME);
1572                         goto end;
1573                 }
1574         } else {
1575                 IFPGA_RAWDEV_PMD_ERR("arg %s is mandatory for ifpga bus",
1576                           IFPGA_ARG_NAME);
1577                 goto end;
1578         }
1579
1580         if (rte_kvargs_count(kvlist, IFPGA_ARG_PORT) == 1) {
1581                 if (rte_kvargs_process(kvlist,
1582                         IFPGA_ARG_PORT,
1583                         &rte_ifpga_get_integer32_arg,
1584                         &port) < 0) {
1585                         IFPGA_RAWDEV_PMD_ERR("error to parse %s",
1586                                 IFPGA_ARG_PORT);
1587                         goto end;
1588                 }
1589         } else {
1590                 IFPGA_RAWDEV_PMD_ERR("arg %s is mandatory for ifpga bus",
1591                           IFPGA_ARG_PORT);
1592                 goto end;
1593         }
1594
1595         memset(dev_name, 0, sizeof(dev_name));
1596         snprintf(dev_name, RTE_RAWDEV_NAME_MAX_LEN, "IFPGA:%s", name);
1597         rawdev = rte_rawdev_pmd_get_named_dev(dev_name);
1598         if (!rawdev)
1599                 goto end;
1600         ifpga_dev = ifpga_rawdev_get(rawdev);
1601         if (!ifpga_dev)
1602                 goto end;
1603         bdf = name;
1604         ifpga_rawdev_fill_info(ifpga_dev, bdf);
1605
1606         ifpga_monitor_start_func();
1607
1608         memset(dev_name, 0, sizeof(dev_name));
1609         snprintf(dev_name, RTE_RAWDEV_NAME_MAX_LEN, "%d|%s",
1610         port, name);
1611
1612         ret = rte_eal_hotplug_add(RTE_STR(IFPGA_BUS_NAME),
1613                         dev_name, devargs->args);
1614 end:
1615         if (kvlist)
1616                 rte_kvargs_free(kvlist);
1617         if (name)
1618                 free(name);
1619
1620         return ret;
1621 }
1622
1623 static int
1624 ifpga_cfg_remove(struct rte_vdev_device *vdev)
1625 {
1626         IFPGA_RAWDEV_PMD_INFO("Remove ifpga_cfg %p",
1627                 vdev);
1628
1629         return 0;
1630 }
1631
1632 static struct rte_vdev_driver ifpga_cfg_driver = {
1633         .probe = ifpga_cfg_probe,
1634         .remove = ifpga_cfg_remove,
1635 };
1636
1637 RTE_PMD_REGISTER_VDEV(ifpga_rawdev_cfg, ifpga_cfg_driver);
1638 RTE_PMD_REGISTER_ALIAS(ifpga_rawdev_cfg, ifpga_cfg);
1639 RTE_PMD_REGISTER_PARAM_STRING(ifpga_rawdev_cfg,
1640         "ifpga=<string> "
1641         "port=<int> "
1642         "afu_bts=<path>");