1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2010-2018 Intel Corporation
11 #include <sys/ioctl.h>
12 #include <sys/epoll.h>
15 #include <rte_malloc.h>
16 #include <rte_devargs.h>
17 #include <rte_memcpy.h>
19 #include <rte_bus_pci.h>
20 #include <rte_kvargs.h>
21 #include <rte_alarm.h>
22 #include <rte_interrupts.h>
23 #include <rte_errno.h>
24 #include <rte_per_lcore.h>
25 #include <rte_memory.h>
26 #include <rte_memzone.h>
28 #include <rte_common.h>
29 #include <rte_bus_vdev.h>
30 #include <rte_string_fns.h>
31 #include <rte_pmd_i40e.h>
33 #include "base/opae_hw_api.h"
34 #include "base/opae_ifpga_hw_api.h"
35 #include "base/ifpga_api.h"
36 #include "rte_rawdev.h"
37 #include "rte_rawdev_pmd.h"
38 #include "rte_bus_ifpga.h"
39 #include "ifpga_common.h"
40 #include "ifpga_logs.h"
41 #include "ifpga_rawdev.h"
42 #include "ipn3ke_rawdev_api.h"
44 #define PCI_VENDOR_ID_INTEL 0x8086
46 #define PCIE_DEVICE_ID_PF_INT_5_X 0xBCBD
47 #define PCIE_DEVICE_ID_PF_INT_6_X 0xBCC0
48 #define PCIE_DEVICE_ID_PF_DSC_1_X 0x09C4
49 #define PCIE_DEVICE_ID_PAC_N3000 0x0B30
51 #define PCIE_DEVICE_ID_VF_INT_5_X 0xBCBF
52 #define PCIE_DEVICE_ID_VF_INT_6_X 0xBCC1
53 #define PCIE_DEVICE_ID_VF_DSC_1_X 0x09C5
54 #define PCIE_DEVICE_ID_VF_PAC_N3000 0x0B31
55 #define RTE_MAX_RAW_DEVICE 10
57 static const struct rte_pci_id pci_ifpga_map[] = {
58 { RTE_PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_PF_INT_5_X) },
59 { RTE_PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_VF_INT_5_X) },
60 { RTE_PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_PF_INT_6_X) },
61 { RTE_PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_VF_INT_6_X) },
62 { RTE_PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_PF_DSC_1_X) },
63 { RTE_PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_VF_DSC_1_X) },
64 { RTE_PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_PAC_N3000),},
65 { RTE_PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_VF_PAC_N3000),},
66 { .vendor_id = 0, /* sentinel */ },
69 static struct ifpga_rawdev ifpga_rawdevices[IFPGA_RAWDEV_NUM];
71 static int ifpga_monitor_start;
72 static pthread_t ifpga_monitor_start_thread;
74 #define IFPGA_MAX_IRQ 12
75 /* 0 for FME interrupt, others are reserved for AFU irq */
76 static struct rte_intr_handle ifpga_irq_handle[IFPGA_MAX_IRQ];
78 static struct ifpga_rawdev *
79 ifpga_rawdev_allocate(struct rte_rawdev *rawdev);
80 static int set_surprise_link_check_aer(
81 struct ifpga_rawdev *ifpga_rdev, int force_disable);
82 static int ifpga_pci_find_next_ext_capability(unsigned int fd,
83 int start, uint32_t cap);
84 static int ifpga_pci_find_ext_capability(unsigned int fd, uint32_t cap);
87 ifpga_rawdev_get(const struct rte_rawdev *rawdev)
89 struct ifpga_rawdev *dev;
95 for (i = 0; i < IFPGA_RAWDEV_NUM; i++) {
96 dev = &ifpga_rawdevices[i];
97 if (dev->rawdev == rawdev)
104 static inline uint8_t
105 ifpga_rawdev_find_free_device_index(void)
109 for (dev_id = 0; dev_id < IFPGA_RAWDEV_NUM; dev_id++) {
110 if (ifpga_rawdevices[dev_id].rawdev == NULL)
114 return IFPGA_RAWDEV_NUM;
116 static struct ifpga_rawdev *
117 ifpga_rawdev_allocate(struct rte_rawdev *rawdev)
119 struct ifpga_rawdev *dev;
122 dev = ifpga_rawdev_get(rawdev);
124 IFPGA_RAWDEV_PMD_ERR("Event device already allocated!");
128 dev_id = ifpga_rawdev_find_free_device_index();
129 if (dev_id == IFPGA_RAWDEV_NUM) {
130 IFPGA_RAWDEV_PMD_ERR("Reached maximum number of raw devices");
134 dev = &ifpga_rawdevices[dev_id];
135 dev->rawdev = rawdev;
136 dev->dev_id = dev_id;
142 ifpga_pci_find_next_ext_capability(unsigned int fd, int start, uint32_t cap)
146 int pos = RTE_PCI_CFG_SPACE_SIZE;
149 /* minimum 8 bytes per capability */
150 ttl = (RTE_PCI_CFG_SPACE_EXP_SIZE - RTE_PCI_CFG_SPACE_SIZE) / 8;
154 ret = pread(fd, &header, sizeof(header), pos);
159 * If we have no capabilities, this is indicated by cap ID,
160 * cap version and next pointer all being 0.
166 if (RTE_PCI_EXT_CAP_ID(header) == cap && pos != start)
169 pos = RTE_PCI_EXT_CAP_NEXT(header);
170 if (pos < RTE_PCI_CFG_SPACE_SIZE)
172 ret = pread(fd, &header, sizeof(header), pos);
181 ifpga_pci_find_ext_capability(unsigned int fd, uint32_t cap)
183 return ifpga_pci_find_next_ext_capability(fd, 0, cap);
186 static int ifpga_get_dev_vendor_id(const char *bdf,
187 uint32_t *dev_id, uint32_t *vendor_id)
194 strlcpy(path, "/sys/bus/pci/devices/", sizeof(path));
195 strlcat(path, bdf, sizeof(path));
196 strlcat(path, "/config", sizeof(path));
197 fd = open(path, O_RDWR);
200 ret = pread(fd, &header, sizeof(header), 0);
205 (*vendor_id) = header & 0xffff;
206 (*dev_id) = (header >> 16) & 0xffff;
211 static int ifpga_rawdev_fill_info(struct ifpga_rawdev *ifpga_dev,
214 char path[1024] = "/sys/bus/pci/devices/0000:";
215 char link[1024], link1[1024];
216 char dir[1024] = "/sys/devices/";
219 char sub_brg_bdf[4][16];
222 struct dirent *entry;
225 unsigned int dom, bus, dev;
227 uint32_t dev_id, vendor_id;
229 strlcat(path, bdf, sizeof(path));
230 memset(link, 0, sizeof(link));
231 memset(link1, 0, sizeof(link1));
232 ret = readlink(path, link, (sizeof(link)-1));
235 strlcpy(link1, link, sizeof(link1));
236 memset(ifpga_dev->parent_bdf, 0, 16);
237 point = strlen(link);
245 rte_memcpy(ifpga_dev->parent_bdf, &link[point], 12);
247 point = strlen(link1);
255 c = strchr(link1, 'p');
258 strlcat(dir, c, sizeof(dir));
265 while ((entry = readdir(dp)) != NULL) {
268 if (entry->d_name[0] == '.')
270 if (strlen(entry->d_name) > 12)
272 if (sscanf(entry->d_name, "%x:%x:%x.%d",
273 &dom, &bus, &dev, &func) < 4)
276 strlcpy(sub_brg_bdf[i],
278 sizeof(sub_brg_bdf[i]));
284 /* get fpga and fvl */
286 for (i = 0; i < 4; i++) {
287 strlcpy(link, dir, sizeof(link));
288 strlcat(link, "/", sizeof(link));
289 strlcat(link, sub_brg_bdf[i], sizeof(link));
293 while ((entry = readdir(dp)) != NULL) {
296 if (entry->d_name[0] == '.')
299 if (strlen(entry->d_name) > 12)
301 if (sscanf(entry->d_name, "%x:%x:%x.%d",
302 &dom, &bus, &dev, &func) < 4)
305 if (ifpga_get_dev_vendor_id(entry->d_name,
306 &dev_id, &vendor_id))
308 if (vendor_id == 0x8086 &&
312 strlcpy(ifpga_dev->fvl_bdf[j],
314 sizeof(ifpga_dev->fvl_bdf[j]));
325 #define HIGH_FATAL(_sens, value)\
326 (((_sens)->flags & OPAE_SENSOR_HIGH_FATAL_VALID) &&\
327 (value > (_sens)->high_fatal))
329 #define HIGH_WARN(_sens, value)\
330 (((_sens)->flags & OPAE_SENSOR_HIGH_WARN_VALID) &&\
331 (value > (_sens)->high_warn))
333 #define LOW_FATAL(_sens, value)\
334 (((_sens)->flags & OPAE_SENSOR_LOW_FATAL_VALID) &&\
335 (value > (_sens)->low_fatal))
337 #define LOW_WARN(_sens, value)\
338 (((_sens)->flags & OPAE_SENSOR_LOW_WARN_VALID) &&\
339 (value > (_sens)->low_warn))
341 #define AUX_VOLTAGE_WARN 11400
344 ifpga_monitor_sensor(struct rte_rawdev *raw_dev,
347 struct opae_adapter *adapter;
348 struct opae_manager *mgr;
349 struct opae_sensor_info *sensor;
353 adapter = ifpga_rawdev_get_priv(raw_dev);
357 mgr = opae_adapter_get_mgr(adapter);
361 opae_mgr_for_each_sensor(mgr, sensor) {
362 if (!(sensor->flags & OPAE_SENSOR_VALID))
365 ret = opae_mgr_get_sensor_value(mgr, sensor, &value);
369 if (value == 0xdeadbeef) {
370 IFPGA_RAWDEV_PMD_ERR("dev_id %d sensor %s value %x\n",
371 raw_dev->dev_id, sensor->name, value);
375 /* monitor temperature sensors */
376 if (!strcmp(sensor->name, "Board Temperature") ||
377 !strcmp(sensor->name, "FPGA Die Temperature")) {
378 IFPGA_RAWDEV_PMD_INFO("read sensor %s %d %d %d\n",
379 sensor->name, value, sensor->high_warn,
382 if (HIGH_WARN(sensor, value) ||
383 LOW_WARN(sensor, value)) {
384 IFPGA_RAWDEV_PMD_INFO("%s reach theshold %d\n",
385 sensor->name, value);
391 /* monitor 12V AUX sensor */
392 if (!strcmp(sensor->name, "12V AUX Voltage")) {
393 if (value < AUX_VOLTAGE_WARN) {
394 IFPGA_RAWDEV_PMD_INFO(
395 "%s reach theshold %d mV\n",
396 sensor->name, value);
408 static int set_surprise_link_check_aer(
409 struct ifpga_rawdev *ifpga_rdev, int force_disable)
411 struct rte_rawdev *rdev;
418 uint32_t aer_new0, aer_new1;
421 printf("\n device does not exist\n");
425 rdev = ifpga_rdev->rawdev;
426 if (ifpga_rdev->aer_enable)
428 if (ifpga_monitor_sensor(rdev, &enable))
430 if (enable || force_disable) {
431 IFPGA_RAWDEV_PMD_ERR("Set AER, pls graceful shutdown\n");
432 ifpga_rdev->aer_enable = 1;
434 strlcpy(path, "/sys/bus/pci/devices/", sizeof(path));
435 strlcat(path, ifpga_rdev->parent_bdf, sizeof(path));
436 strlcat(path, "/config", sizeof(path));
437 fd = open(path, O_RDWR);
440 pos = ifpga_pci_find_ext_capability(fd, RTE_PCI_EXT_CAP_ID_ERR);
443 /* save previout ECAP_AER+0x08 */
444 ret = pread(fd, &data, sizeof(data), pos+0x08);
447 ifpga_rdev->aer_old[0] = data;
448 /* save previout ECAP_AER+0x14 */
449 ret = pread(fd, &data, sizeof(data), pos+0x14);
452 ifpga_rdev->aer_old[1] = data;
454 /* set ECAP_AER+0x08 to 0xFFFFFFFF */
456 ret = pwrite(fd, &data, 4, pos+0x08);
459 /* set ECAP_AER+0x14 to 0xFFFFFFFF */
460 ret = pwrite(fd, &data, 4, pos+0x14);
464 /* read current ECAP_AER+0x08 */
465 ret = pread(fd, &data, sizeof(data), pos+0x08);
469 /* read current ECAP_AER+0x14 */
470 ret = pread(fd, &data, sizeof(data), pos+0x14);
478 printf(">>>>>>Set AER %x,%x %x,%x\n",
479 ifpga_rdev->aer_old[0], ifpga_rdev->aer_old[1],
492 ifpga_rawdev_gsd_handle(__rte_unused void *param)
494 struct ifpga_rawdev *ifpga_rdev;
501 for (i = 0; i < IFPGA_RAWDEV_NUM; i++) {
502 ifpga_rdev = &ifpga_rawdevices[i];
503 if (ifpga_rdev->rawdev) {
504 ret = set_surprise_link_check_aer(ifpga_rdev,
506 if (ret == 1 && !gsd_enable) {
514 printf(">>>>>>Pls Shutdown APP\n");
516 rte_delay_us(100 * MS);
523 ifpga_monitor_start_func(void)
527 if (ifpga_monitor_start == 0) {
528 ret = pthread_create(&ifpga_monitor_start_thread,
530 ifpga_rawdev_gsd_handle, NULL);
532 IFPGA_RAWDEV_PMD_ERR(
533 "Fail to create ifpga nonitor thread");
536 ifpga_monitor_start = 1;
542 ifpga_monitor_stop_func(void)
546 if (ifpga_monitor_start == 1) {
547 ret = pthread_cancel(ifpga_monitor_start_thread);
549 IFPGA_RAWDEV_PMD_ERR("Can't cancel the thread");
551 ret = pthread_join(ifpga_monitor_start_thread, NULL);
553 IFPGA_RAWDEV_PMD_ERR("Can't join the thread");
555 ifpga_monitor_start = 0;
564 ifpga_fill_afu_dev(struct opae_accelerator *acc,
565 struct rte_afu_device *afu_dev)
567 struct rte_mem_resource *res = afu_dev->mem_resource;
568 struct opae_acc_region_info region_info;
569 struct opae_acc_info info;
573 ret = opae_acc_get_info(acc, &info);
577 if (info.num_regions > PCI_MAX_RESOURCE)
580 afu_dev->num_region = info.num_regions;
582 for (i = 0; i < info.num_regions; i++) {
583 region_info.index = i;
584 ret = opae_acc_get_region_info(acc, ®ion_info);
588 if ((region_info.flags & ACC_REGION_MMIO) &&
589 (region_info.flags & ACC_REGION_READ) &&
590 (region_info.flags & ACC_REGION_WRITE)) {
591 res[i].phys_addr = region_info.phys_addr;
592 res[i].len = region_info.len;
593 res[i].addr = region_info.addr;
602 ifpga_rawdev_info_get(struct rte_rawdev *dev,
603 rte_rawdev_obj_t dev_info,
604 size_t dev_info_size)
606 struct opae_adapter *adapter;
607 struct opae_accelerator *acc;
608 struct rte_afu_device *afu_dev;
609 struct opae_manager *mgr = NULL;
610 struct opae_eth_group_region_info opae_lside_eth_info;
611 struct opae_eth_group_region_info opae_nside_eth_info;
612 int lside_bar_idx, nside_bar_idx;
614 IFPGA_RAWDEV_PMD_FUNC_TRACE();
616 if (!dev_info || dev_info_size != sizeof(*afu_dev)) {
617 IFPGA_RAWDEV_PMD_ERR("Invalid request");
621 adapter = ifpga_rawdev_get_priv(dev);
626 afu_dev->rawdev = dev;
628 /* find opae_accelerator and fill info into afu_device */
629 opae_adapter_for_each_acc(adapter, acc) {
630 if (acc->index != afu_dev->id.port)
633 if (ifpga_fill_afu_dev(acc, afu_dev)) {
634 IFPGA_RAWDEV_PMD_ERR("cannot get info\n");
639 /* get opae_manager to rawdev */
640 mgr = opae_adapter_get_mgr(adapter);
642 /* get LineSide BAR Index */
643 if (opae_manager_get_eth_group_region_info(mgr, 0,
644 &opae_lside_eth_info)) {
647 lside_bar_idx = opae_lside_eth_info.mem_idx;
649 /* get NICSide BAR Index */
650 if (opae_manager_get_eth_group_region_info(mgr, 1,
651 &opae_nside_eth_info)) {
654 nside_bar_idx = opae_nside_eth_info.mem_idx;
656 if (lside_bar_idx >= PCI_MAX_RESOURCE ||
657 nside_bar_idx >= PCI_MAX_RESOURCE ||
658 lside_bar_idx == nside_bar_idx)
661 /* fill LineSide BAR Index */
662 afu_dev->mem_resource[lside_bar_idx].phys_addr =
663 opae_lside_eth_info.phys_addr;
664 afu_dev->mem_resource[lside_bar_idx].len =
665 opae_lside_eth_info.len;
666 afu_dev->mem_resource[lside_bar_idx].addr =
667 opae_lside_eth_info.addr;
669 /* fill NICSide BAR Index */
670 afu_dev->mem_resource[nside_bar_idx].phys_addr =
671 opae_nside_eth_info.phys_addr;
672 afu_dev->mem_resource[nside_bar_idx].len =
673 opae_nside_eth_info.len;
674 afu_dev->mem_resource[nside_bar_idx].addr =
675 opae_nside_eth_info.addr;
681 ifpga_rawdev_configure(const struct rte_rawdev *dev,
682 rte_rawdev_obj_t config,
683 size_t config_size __rte_unused)
685 IFPGA_RAWDEV_PMD_FUNC_TRACE();
687 RTE_FUNC_PTR_OR_ERR_RET(dev, -EINVAL);
689 return config ? 0 : 1;
693 ifpga_rawdev_start(struct rte_rawdev *dev)
696 struct opae_adapter *adapter;
698 IFPGA_RAWDEV_PMD_FUNC_TRACE();
700 RTE_FUNC_PTR_OR_ERR_RET(dev, -EINVAL);
702 adapter = ifpga_rawdev_get_priv(dev);
710 ifpga_rawdev_stop(struct rte_rawdev *dev)
716 ifpga_rawdev_close(struct rte_rawdev *dev)
722 ifpga_rawdev_reset(struct rte_rawdev *dev)
728 fpga_pr(struct rte_rawdev *raw_dev, u32 port_id, const char *buffer, u32 size,
732 struct opae_adapter *adapter;
733 struct opae_manager *mgr;
734 struct opae_accelerator *acc;
735 struct opae_bridge *br;
738 adapter = ifpga_rawdev_get_priv(raw_dev);
742 mgr = opae_adapter_get_mgr(adapter);
746 acc = opae_adapter_get_acc(adapter, port_id);
750 br = opae_acc_get_br(acc);
754 ret = opae_manager_flash(mgr, port_id, buffer, size, status);
756 IFPGA_RAWDEV_PMD_ERR("%s pr error %d\n", __func__, ret);
760 ret = opae_bridge_reset(br);
762 IFPGA_RAWDEV_PMD_ERR("%s reset port:%d error %d\n",
763 __func__, port_id, ret);
771 rte_fpga_do_pr(struct rte_rawdev *rawdev, int port_id,
772 const char *file_name)
774 struct stat file_stat;
784 file_fd = open(file_name, O_RDONLY);
786 IFPGA_RAWDEV_PMD_ERR("%s: open file error: %s\n",
787 __func__, file_name);
788 IFPGA_RAWDEV_PMD_ERR("Message : %s\n", strerror(errno));
791 ret = stat(file_name, &file_stat);
793 IFPGA_RAWDEV_PMD_ERR("stat on bitstream file failed: %s\n",
798 buffer_size = file_stat.st_size;
799 if (buffer_size <= 0) {
804 IFPGA_RAWDEV_PMD_INFO("bitstream file size: %zu\n", buffer_size);
805 buffer = rte_malloc(NULL, buffer_size, 0);
811 /*read the raw data*/
812 if (buffer_size != read(file_fd, (void *)buffer, buffer_size)) {
818 ret = fpga_pr(rawdev, port_id, buffer, buffer_size, &pr_error);
819 IFPGA_RAWDEV_PMD_INFO("downloading to device port %d....%s.\n", port_id,
820 ret ? "failed" : "success");
836 ifpga_rawdev_pr(struct rte_rawdev *dev,
837 rte_rawdev_obj_t pr_conf)
839 struct opae_adapter *adapter;
840 struct opae_manager *mgr;
841 struct opae_board_info *info;
842 struct rte_afu_pr_conf *afu_pr_conf;
845 struct opae_accelerator *acc;
847 IFPGA_RAWDEV_PMD_FUNC_TRACE();
849 adapter = ifpga_rawdev_get_priv(dev);
856 afu_pr_conf = pr_conf;
858 if (afu_pr_conf->pr_enable) {
859 ret = rte_fpga_do_pr(dev,
860 afu_pr_conf->afu_id.port,
861 afu_pr_conf->bs_path);
863 IFPGA_RAWDEV_PMD_ERR("do pr error %d\n", ret);
868 mgr = opae_adapter_get_mgr(adapter);
870 IFPGA_RAWDEV_PMD_ERR("opae_manager of opae_adapter is NULL");
874 if (ifpga_mgr_ops.get_board_info(mgr, &info)) {
875 IFPGA_RAWDEV_PMD_ERR("ifpga manager get_board_info fail!");
879 if (info->lightweight) {
880 /* set uuid to all 0, when fpga is lightweight image */
881 memset(&afu_pr_conf->afu_id.uuid.uuid_low, 0, sizeof(u64));
882 memset(&afu_pr_conf->afu_id.uuid.uuid_high, 0, sizeof(u64));
884 acc = opae_adapter_get_acc(adapter, afu_pr_conf->afu_id.port);
888 ret = opae_acc_get_uuid(acc, &uuid);
892 rte_memcpy(&afu_pr_conf->afu_id.uuid.uuid_low, uuid.b,
894 rte_memcpy(&afu_pr_conf->afu_id.uuid.uuid_high, uuid.b + 8,
897 IFPGA_RAWDEV_PMD_INFO("%s: uuid_l=0x%lx, uuid_h=0x%lx\n",
899 (unsigned long)afu_pr_conf->afu_id.uuid.uuid_low,
900 (unsigned long)afu_pr_conf->afu_id.uuid.uuid_high);
906 ifpga_rawdev_get_attr(struct rte_rawdev *dev,
907 const char *attr_name, uint64_t *attr_value)
909 struct opae_adapter *adapter;
910 struct opae_manager *mgr;
911 struct opae_retimer_info opae_rtm_info;
912 struct opae_retimer_status opae_rtm_status;
913 struct opae_eth_group_info opae_eth_grp_info;
914 struct opae_eth_group_region_info opae_eth_grp_reg_info;
915 int eth_group_num = 0;
916 uint64_t port_link_bitmap = 0, port_link_bit;
919 #define MAX_PORT_PER_RETIMER 4
921 IFPGA_RAWDEV_PMD_FUNC_TRACE();
923 if (!dev || !attr_name || !attr_value) {
924 IFPGA_RAWDEV_PMD_ERR("Invalid arguments for getting attributes");
928 adapter = ifpga_rawdev_get_priv(dev);
930 IFPGA_RAWDEV_PMD_ERR("Adapter of dev %s is NULL", dev->name);
934 mgr = opae_adapter_get_mgr(adapter);
936 IFPGA_RAWDEV_PMD_ERR("opae_manager of opae_adapter is NULL");
940 /* currently, eth_group_num is always 2 */
941 eth_group_num = opae_manager_get_eth_group_nums(mgr);
942 if (eth_group_num < 0)
945 if (!strcmp(attr_name, "LineSideBaseMAC")) {
946 /* Currently FPGA not implement, so just set all zeros*/
947 *attr_value = (uint64_t)0;
950 if (!strcmp(attr_name, "LineSideMACType")) {
951 /* eth_group 0 on FPGA connect to LineSide */
952 if (opae_manager_get_eth_group_info(mgr, 0,
955 switch (opae_eth_grp_info.speed) {
958 (uint64_t)(IFPGA_RAWDEV_RETIMER_MAC_TYPE_10GE_XFI);
962 (uint64_t)(IFPGA_RAWDEV_RETIMER_MAC_TYPE_25GE_25GAUI);
966 (uint64_t)(IFPGA_RAWDEV_RETIMER_MAC_TYPE_UNKNOWN);
971 if (!strcmp(attr_name, "LineSideLinkSpeed")) {
972 if (opae_manager_get_retimer_status(mgr, &opae_rtm_status))
974 switch (opae_rtm_status.speed) {
977 (uint64_t)(IFPGA_RAWDEV_LINK_SPEED_UNKNOWN);
981 (uint64_t)(IFPGA_RAWDEV_LINK_SPEED_UNKNOWN);
985 (uint64_t)(IFPGA_RAWDEV_LINK_SPEED_UNKNOWN);
989 (uint64_t)(IFPGA_RAWDEV_LINK_SPEED_10GB);
993 (uint64_t)(IFPGA_RAWDEV_LINK_SPEED_25GB);
997 (uint64_t)(IFPGA_RAWDEV_LINK_SPEED_40GB);
1001 (uint64_t)(IFPGA_RAWDEV_LINK_SPEED_UNKNOWN);
1003 case MXD_SPEED_UNKNOWN:
1005 (uint64_t)(IFPGA_RAWDEV_LINK_SPEED_UNKNOWN);
1009 (uint64_t)(IFPGA_RAWDEV_LINK_SPEED_UNKNOWN);
1014 if (!strcmp(attr_name, "LineSideLinkRetimerNum")) {
1015 if (opae_manager_get_retimer_info(mgr, &opae_rtm_info))
1017 *attr_value = (uint64_t)(opae_rtm_info.nums_retimer);
1020 if (!strcmp(attr_name, "LineSideLinkPortNum")) {
1021 if (opae_manager_get_retimer_info(mgr, &opae_rtm_info))
1023 uint64_t tmp = (uint64_t)opae_rtm_info.ports_per_retimer *
1024 (uint64_t)opae_rtm_info.nums_retimer;
1028 if (!strcmp(attr_name, "LineSideLinkStatus")) {
1029 if (opae_manager_get_retimer_info(mgr, &opae_rtm_info))
1031 if (opae_manager_get_retimer_status(mgr, &opae_rtm_status))
1035 port_link_bitmap = (uint64_t)(opae_rtm_status.line_link_bitmap);
1036 for (i = 0; i < opae_rtm_info.nums_retimer; i++) {
1037 p = i * MAX_PORT_PER_RETIMER;
1038 for (j = 0; j < opae_rtm_info.ports_per_retimer; j++) {
1040 IFPGA_BIT_SET(port_link_bit, (p+j));
1041 port_link_bit &= port_link_bitmap;
1043 IFPGA_BIT_SET((*attr_value), q);
1049 if (!strcmp(attr_name, "LineSideBARIndex")) {
1050 /* eth_group 0 on FPGA connect to LineSide */
1051 if (opae_manager_get_eth_group_region_info(mgr, 0,
1052 &opae_eth_grp_reg_info))
1054 *attr_value = (uint64_t)opae_eth_grp_reg_info.mem_idx;
1057 if (!strcmp(attr_name, "NICSideMACType")) {
1058 /* eth_group 1 on FPGA connect to NicSide */
1059 if (opae_manager_get_eth_group_info(mgr, 1,
1060 &opae_eth_grp_info))
1062 *attr_value = (uint64_t)(opae_eth_grp_info.speed);
1065 if (!strcmp(attr_name, "NICSideLinkSpeed")) {
1066 /* eth_group 1 on FPGA connect to NicSide */
1067 if (opae_manager_get_eth_group_info(mgr, 1,
1068 &opae_eth_grp_info))
1070 *attr_value = (uint64_t)(opae_eth_grp_info.speed);
1073 if (!strcmp(attr_name, "NICSideLinkPortNum")) {
1074 if (opae_manager_get_retimer_info(mgr, &opae_rtm_info))
1076 uint64_t tmp = (uint64_t)opae_rtm_info.nums_fvl *
1077 (uint64_t)opae_rtm_info.ports_per_fvl;
1081 if (!strcmp(attr_name, "NICSideLinkStatus"))
1083 if (!strcmp(attr_name, "NICSideBARIndex")) {
1084 /* eth_group 1 on FPGA connect to NicSide */
1085 if (opae_manager_get_eth_group_region_info(mgr, 1,
1086 &opae_eth_grp_reg_info))
1088 *attr_value = (uint64_t)opae_eth_grp_reg_info.mem_idx;
1092 IFPGA_RAWDEV_PMD_ERR("%s not support", attr_name);
1096 static const struct rte_rawdev_ops ifpga_rawdev_ops = {
1097 .dev_info_get = ifpga_rawdev_info_get,
1098 .dev_configure = ifpga_rawdev_configure,
1099 .dev_start = ifpga_rawdev_start,
1100 .dev_stop = ifpga_rawdev_stop,
1101 .dev_close = ifpga_rawdev_close,
1102 .dev_reset = ifpga_rawdev_reset,
1104 .queue_def_conf = NULL,
1105 .queue_setup = NULL,
1106 .queue_release = NULL,
1108 .attr_get = ifpga_rawdev_get_attr,
1111 .enqueue_bufs = NULL,
1112 .dequeue_bufs = NULL,
1117 .xstats_get_names = NULL,
1118 .xstats_get_by_name = NULL,
1119 .xstats_reset = NULL,
1121 .firmware_status_get = NULL,
1122 .firmware_version_get = NULL,
1123 .firmware_load = ifpga_rawdev_pr,
1124 .firmware_unload = NULL,
1126 .dev_selftest = NULL,
1130 ifpga_get_fme_error_prop(struct opae_manager *mgr,
1131 u64 prop_id, u64 *val)
1133 struct feature_prop prop;
1135 prop.feature_id = IFPGA_FME_FEATURE_ID_GLOBAL_ERR;
1136 prop.prop_id = prop_id;
1138 if (opae_manager_ifpga_get_prop(mgr, &prop))
1147 ifpga_set_fme_error_prop(struct opae_manager *mgr,
1148 u64 prop_id, u64 val)
1150 struct feature_prop prop;
1152 prop.feature_id = IFPGA_FME_FEATURE_ID_GLOBAL_ERR;
1153 prop.prop_id = prop_id;
1157 if (opae_manager_ifpga_set_prop(mgr, &prop))
1164 fme_err_read_seu_emr(struct opae_manager *mgr)
1169 ret = ifpga_get_fme_error_prop(mgr, FME_ERR_PROP_SEU_EMR_LOW, &val);
1173 IFPGA_RAWDEV_PMD_INFO("seu emr low: 0x%" PRIx64 "\n", val);
1175 ret = ifpga_get_fme_error_prop(mgr, FME_ERR_PROP_SEU_EMR_HIGH, &val);
1179 IFPGA_RAWDEV_PMD_INFO("seu emr high: 0x%" PRIx64 "\n", val);
1184 static int fme_clear_warning_intr(struct opae_manager *mgr)
1188 if (ifpga_set_fme_error_prop(mgr, FME_ERR_PROP_INJECT_ERRORS, 0))
1191 if (ifpga_get_fme_error_prop(mgr, FME_ERR_PROP_NONFATAL_ERRORS, &val))
1193 if ((val & 0x40) != 0)
1194 IFPGA_RAWDEV_PMD_INFO("clean not done\n");
1199 static int fme_clean_fme_error(struct opae_manager *mgr)
1203 if (ifpga_get_fme_error_prop(mgr, FME_ERR_PROP_ERRORS, &val))
1206 IFPGA_RAWDEV_PMD_DEBUG("before clean 0x%" PRIx64 "\n", val);
1208 ifpga_set_fme_error_prop(mgr, FME_ERR_PROP_CLEAR, val);
1210 if (ifpga_get_fme_error_prop(mgr, FME_ERR_PROP_ERRORS, &val))
1213 IFPGA_RAWDEV_PMD_DEBUG("after clean 0x%" PRIx64 "\n", val);
1219 fme_err_handle_error0(struct opae_manager *mgr)
1221 struct feature_fme_error0 fme_error0;
1224 if (ifpga_get_fme_error_prop(mgr, FME_ERR_PROP_ERRORS, &val))
1227 if (fme_clean_fme_error(mgr))
1230 fme_error0.csr = val;
1232 if (fme_error0.fabric_err)
1233 IFPGA_RAWDEV_PMD_ERR("Fabric error\n");
1234 else if (fme_error0.fabfifo_overflow)
1235 IFPGA_RAWDEV_PMD_ERR("Fabric fifo under/overflow error\n");
1236 else if (fme_error0.afu_acc_mode_err)
1237 IFPGA_RAWDEV_PMD_ERR("AFU PF/VF access mismatch detected\n");
1238 else if (fme_error0.pcie0cdc_parity_err)
1239 IFPGA_RAWDEV_PMD_ERR("PCIe0 CDC Parity Error\n");
1240 else if (fme_error0.cvlcdc_parity_err)
1241 IFPGA_RAWDEV_PMD_ERR("CVL CDC Parity Error\n");
1242 else if (fme_error0.fpgaseuerr)
1243 fme_err_read_seu_emr(mgr);
1245 /* clean the errors */
1246 if (ifpga_set_fme_error_prop(mgr, FME_ERR_PROP_ERRORS, val))
1253 fme_err_handle_catfatal_error(struct opae_manager *mgr)
1255 struct feature_fme_ras_catfaterror fme_catfatal;
1258 if (ifpga_get_fme_error_prop(mgr, FME_ERR_PROP_CATFATAL_ERRORS, &val))
1261 fme_catfatal.csr = val;
1263 if (fme_catfatal.cci_fatal_err)
1264 IFPGA_RAWDEV_PMD_ERR("CCI error detected\n");
1265 else if (fme_catfatal.fabric_fatal_err)
1266 IFPGA_RAWDEV_PMD_ERR("Fabric fatal error detected\n");
1267 else if (fme_catfatal.pcie_poison_err)
1268 IFPGA_RAWDEV_PMD_ERR("Poison error from PCIe ports\n");
1269 else if (fme_catfatal.inject_fata_err)
1270 IFPGA_RAWDEV_PMD_ERR("Injected Fatal Error\n");
1271 else if (fme_catfatal.crc_catast_err)
1272 IFPGA_RAWDEV_PMD_ERR("a catastrophic EDCRC error\n");
1273 else if (fme_catfatal.injected_catast_err)
1274 IFPGA_RAWDEV_PMD_ERR("Injected Catastrophic Error\n");
1275 else if (fme_catfatal.bmc_seu_catast_err)
1276 fme_err_read_seu_emr(mgr);
1282 fme_err_handle_nonfaterror(struct opae_manager *mgr)
1284 struct feature_fme_ras_nonfaterror nonfaterr;
1287 if (ifpga_get_fme_error_prop(mgr, FME_ERR_PROP_NONFATAL_ERRORS, &val))
1290 nonfaterr.csr = val;
1292 if (nonfaterr.temp_thresh_ap1)
1293 IFPGA_RAWDEV_PMD_INFO("Temperature threshold triggered AP1\n");
1294 else if (nonfaterr.temp_thresh_ap2)
1295 IFPGA_RAWDEV_PMD_INFO("Temperature threshold triggered AP2\n");
1296 else if (nonfaterr.pcie_error)
1297 IFPGA_RAWDEV_PMD_INFO("an error has occurred in pcie\n");
1298 else if (nonfaterr.portfatal_error)
1299 IFPGA_RAWDEV_PMD_INFO("fatal error occurred in AFU port.\n");
1300 else if (nonfaterr.proc_hot)
1301 IFPGA_RAWDEV_PMD_INFO("a ProcHot event\n");
1302 else if (nonfaterr.afu_acc_mode_err)
1303 IFPGA_RAWDEV_PMD_INFO("an AFU PF/VF access mismatch\n");
1304 else if (nonfaterr.injected_nonfata_err) {
1305 IFPGA_RAWDEV_PMD_INFO("Injected Warning Error\n");
1306 fme_clear_warning_intr(mgr);
1307 } else if (nonfaterr.temp_thresh_AP6)
1308 IFPGA_RAWDEV_PMD_INFO("Temperature threshold triggered AP6\n");
1309 else if (nonfaterr.power_thresh_AP1)
1310 IFPGA_RAWDEV_PMD_INFO("Power threshold triggered AP1\n");
1311 else if (nonfaterr.power_thresh_AP2)
1312 IFPGA_RAWDEV_PMD_INFO("Power threshold triggered AP2\n");
1313 else if (nonfaterr.mbp_err)
1314 IFPGA_RAWDEV_PMD_INFO("an MBP event\n");
1320 fme_interrupt_handler(void *param)
1322 struct opae_manager *mgr = (struct opae_manager *)param;
1324 IFPGA_RAWDEV_PMD_INFO("%s interrupt occurred\n", __func__);
1326 fme_err_handle_error0(mgr);
1327 fme_err_handle_nonfaterror(mgr);
1328 fme_err_handle_catfatal_error(mgr);
1332 ifpga_unregister_msix_irq(enum ifpga_irq_type type,
1333 int vec_start, rte_intr_callback_fn handler, void *arg)
1335 struct rte_intr_handle intr_handle;
1337 if (type == IFPGA_FME_IRQ)
1338 intr_handle = ifpga_irq_handle[0];
1339 else if (type == IFPGA_AFU_IRQ)
1340 intr_handle = ifpga_irq_handle[vec_start + 1];
1342 rte_intr_efd_disable(&intr_handle);
1344 return rte_intr_callback_unregister(&intr_handle,
1349 ifpga_register_msix_irq(struct rte_rawdev *dev, int port_id,
1350 enum ifpga_irq_type type, int vec_start, int count,
1351 rte_intr_callback_fn handler, const char *name,
1355 struct rte_intr_handle intr_handle;
1356 struct opae_adapter *adapter;
1357 struct opae_manager *mgr;
1358 struct opae_accelerator *acc;
1360 adapter = ifpga_rawdev_get_priv(dev);
1364 mgr = opae_adapter_get_mgr(adapter);
1368 if (type == IFPGA_FME_IRQ) {
1369 intr_handle = ifpga_irq_handle[0];
1371 } else if (type == IFPGA_AFU_IRQ)
1372 intr_handle = ifpga_irq_handle[vec_start + 1];
1374 intr_handle.type = RTE_INTR_HANDLE_VFIO_MSIX;
1376 ret = rte_intr_efd_enable(&intr_handle, count);
1380 intr_handle.fd = intr_handle.efds[0];
1382 IFPGA_RAWDEV_PMD_DEBUG("register %s irq, vfio_fd=%d, fd=%d\n",
1383 name, intr_handle.vfio_dev_fd,
1386 if (type == IFPGA_FME_IRQ) {
1387 struct fpga_fme_err_irq_set err_irq_set;
1388 err_irq_set.evtfd = intr_handle.efds[0];
1390 ret = opae_manager_ifpga_set_err_irq(mgr, &err_irq_set);
1393 } else if (type == IFPGA_AFU_IRQ) {
1394 acc = opae_adapter_get_acc(adapter, port_id);
1398 ret = opae_acc_set_irq(acc, vec_start, count, intr_handle.efds);
1403 /* register interrupt handler using DPDK API */
1404 ret = rte_intr_callback_register(&intr_handle,
1405 handler, (void *)arg);
1409 IFPGA_RAWDEV_PMD_INFO("success register %s interrupt\n", name);
1415 ifpga_rawdev_create(struct rte_pci_device *pci_dev,
1419 struct rte_rawdev *rawdev = NULL;
1420 struct ifpga_rawdev *dev = NULL;
1421 struct opae_adapter *adapter = NULL;
1422 struct opae_manager *mgr = NULL;
1423 struct opae_adapter_data_pci *data = NULL;
1424 char name[RTE_RAWDEV_NAME_MAX_LEN];
1428 IFPGA_RAWDEV_PMD_ERR("Invalid pci_dev of the device!");
1433 memset(name, 0, sizeof(name));
1434 snprintf(name, RTE_RAWDEV_NAME_MAX_LEN, "IFPGA:%02x:%02x.%x",
1435 pci_dev->addr.bus, pci_dev->addr.devid, pci_dev->addr.function);
1437 IFPGA_RAWDEV_PMD_INFO("Init %s on NUMA node %d", name, rte_socket_id());
1439 /* Allocate device structure */
1440 rawdev = rte_rawdev_pmd_allocate(name, sizeof(struct opae_adapter),
1442 if (rawdev == NULL) {
1443 IFPGA_RAWDEV_PMD_ERR("Unable to allocate rawdevice");
1448 ipn3ke_bridge_func.get_ifpga_rawdev = ifpga_rawdev_get;
1449 ipn3ke_bridge_func.set_i40e_sw_dev = rte_pmd_i40e_set_switch_dev;
1451 dev = ifpga_rawdev_allocate(rawdev);
1453 IFPGA_RAWDEV_PMD_ERR("Unable to allocate ifpga_rawdevice");
1457 dev->aer_enable = 0;
1459 /* alloc OPAE_FPGA_PCI data to register to OPAE hardware level API */
1460 data = opae_adapter_data_alloc(OPAE_FPGA_PCI);
1466 /* init opae_adapter_data_pci for device specific information */
1467 for (i = 0; i < PCI_MAX_RESOURCE; i++) {
1468 data->region[i].phys_addr = pci_dev->mem_resource[i].phys_addr;
1469 data->region[i].len = pci_dev->mem_resource[i].len;
1470 data->region[i].addr = pci_dev->mem_resource[i].addr;
1472 data->device_id = pci_dev->id.device_id;
1473 data->vendor_id = pci_dev->id.vendor_id;
1474 data->bus = pci_dev->addr.bus;
1475 data->devid = pci_dev->addr.devid;
1476 data->function = pci_dev->addr.function;
1477 data->vfio_dev_fd = pci_dev->intr_handle.vfio_dev_fd;
1479 adapter = rawdev->dev_private;
1480 /* create a opae_adapter based on above device data */
1481 ret = opae_adapter_init(adapter, pci_dev->device.name, data);
1484 goto free_adapter_data;
1487 rawdev->dev_ops = &ifpga_rawdev_ops;
1488 rawdev->device = &pci_dev->device;
1489 rawdev->driver_name = pci_dev->driver->driver.name;
1491 /* must enumerate the adapter before use it */
1492 ret = opae_adapter_enumerate(adapter);
1494 goto free_adapter_data;
1496 /* get opae_manager to rawdev */
1497 mgr = opae_adapter_get_mgr(adapter);
1500 IFPGA_RAWDEV_PMD_INFO("this is a PF function");
1503 ret = ifpga_register_msix_irq(rawdev, 0, IFPGA_FME_IRQ, 0, 0,
1504 fme_interrupt_handler, "fme_irq", mgr);
1506 goto free_adapter_data;
1512 opae_adapter_data_free(data);
1515 rte_rawdev_pmd_release(rawdev);
1521 ifpga_rawdev_destroy(struct rte_pci_device *pci_dev)
1524 struct rte_rawdev *rawdev;
1525 char name[RTE_RAWDEV_NAME_MAX_LEN];
1526 struct opae_adapter *adapter;
1527 struct opae_manager *mgr;
1530 IFPGA_RAWDEV_PMD_ERR("Invalid pci_dev of the device!");
1535 memset(name, 0, sizeof(name));
1536 snprintf(name, RTE_RAWDEV_NAME_MAX_LEN, "IFPGA:%x:%02x.%x",
1537 pci_dev->addr.bus, pci_dev->addr.devid, pci_dev->addr.function);
1539 IFPGA_RAWDEV_PMD_INFO("Closing %s on NUMA node %d",
1540 name, rte_socket_id());
1542 rawdev = rte_rawdev_pmd_get_named_dev(name);
1544 IFPGA_RAWDEV_PMD_ERR("Invalid device name (%s)", name);
1548 adapter = ifpga_rawdev_get_priv(rawdev);
1552 mgr = opae_adapter_get_mgr(adapter);
1556 if (ifpga_unregister_msix_irq(IFPGA_FME_IRQ, 0,
1557 fme_interrupt_handler, mgr))
1560 opae_adapter_data_free(adapter->data);
1561 opae_adapter_free(adapter);
1563 /* rte_rawdev_close is called by pmd_release */
1564 ret = rte_rawdev_pmd_release(rawdev);
1566 IFPGA_RAWDEV_PMD_DEBUG("Device cleanup failed");
1572 ifpga_rawdev_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1573 struct rte_pci_device *pci_dev)
1575 IFPGA_RAWDEV_PMD_FUNC_TRACE();
1576 return ifpga_rawdev_create(pci_dev, rte_socket_id());
1580 ifpga_rawdev_pci_remove(struct rte_pci_device *pci_dev)
1582 ifpga_monitor_stop_func();
1583 return ifpga_rawdev_destroy(pci_dev);
1586 static struct rte_pci_driver rte_ifpga_rawdev_pmd = {
1587 .id_table = pci_ifpga_map,
1588 .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
1589 .probe = ifpga_rawdev_pci_probe,
1590 .remove = ifpga_rawdev_pci_remove,
1593 RTE_PMD_REGISTER_PCI(ifpga_rawdev_pci_driver, rte_ifpga_rawdev_pmd);
1594 RTE_PMD_REGISTER_PCI_TABLE(ifpga_rawdev_pci_driver, rte_ifpga_rawdev_pmd);
1595 RTE_PMD_REGISTER_KMOD_DEP(ifpga_rawdev_pci_driver, "* igb_uio | uio_pci_generic | vfio-pci");
1596 RTE_LOG_REGISTER(ifpga_rawdev_logtype, driver.raw.init, NOTICE);
1598 static const char * const valid_args[] = {
1599 #define IFPGA_ARG_NAME "ifpga"
1601 #define IFPGA_ARG_PORT "port"
1603 #define IFPGA_AFU_BTS "afu_bts"
1608 static int ifpga_rawdev_get_string_arg(const char *key __rte_unused,
1609 const char *value, void *extra_args)
1612 if (!value || !extra_args)
1615 size = strlen(value) + 1;
1616 *(char **)extra_args = rte_malloc(NULL, size, RTE_CACHE_LINE_SIZE);
1617 if (!*(char **)extra_args)
1620 strlcpy(*(char **)extra_args, value, size);
1625 ifpga_cfg_probe(struct rte_vdev_device *dev)
1627 struct rte_devargs *devargs;
1628 struct rte_kvargs *kvlist = NULL;
1629 struct rte_rawdev *rawdev = NULL;
1630 struct ifpga_rawdev *ifpga_dev;
1634 char dev_name[RTE_RAWDEV_NAME_MAX_LEN];
1637 devargs = dev->device.devargs;
1639 kvlist = rte_kvargs_parse(devargs->args, valid_args);
1641 IFPGA_RAWDEV_PMD_LOG(ERR, "error when parsing param");
1645 if (rte_kvargs_count(kvlist, IFPGA_ARG_NAME) == 1) {
1646 if (rte_kvargs_process(kvlist, IFPGA_ARG_NAME,
1647 &ifpga_rawdev_get_string_arg,
1649 IFPGA_RAWDEV_PMD_ERR("error to parse %s",
1654 IFPGA_RAWDEV_PMD_ERR("arg %s is mandatory for ifpga bus",
1659 if (rte_kvargs_count(kvlist, IFPGA_ARG_PORT) == 1) {
1660 if (rte_kvargs_process(kvlist,
1662 &rte_ifpga_get_integer32_arg,
1664 IFPGA_RAWDEV_PMD_ERR("error to parse %s",
1669 IFPGA_RAWDEV_PMD_ERR("arg %s is mandatory for ifpga bus",
1674 memset(dev_name, 0, sizeof(dev_name));
1675 snprintf(dev_name, RTE_RAWDEV_NAME_MAX_LEN, "IFPGA:%s", name);
1676 rawdev = rte_rawdev_pmd_get_named_dev(dev_name);
1679 ifpga_dev = ifpga_rawdev_get(rawdev);
1683 ifpga_rawdev_fill_info(ifpga_dev, bdf);
1685 ifpga_monitor_start_func();
1687 memset(dev_name, 0, sizeof(dev_name));
1688 snprintf(dev_name, RTE_RAWDEV_NAME_MAX_LEN, "%d|%s",
1691 ret = rte_eal_hotplug_add(RTE_STR(IFPGA_BUS_NAME),
1692 dev_name, devargs->args);
1695 rte_kvargs_free(kvlist);
1703 ifpga_cfg_remove(struct rte_vdev_device *vdev)
1705 IFPGA_RAWDEV_PMD_INFO("Remove ifpga_cfg %p",
1711 static struct rte_vdev_driver ifpga_cfg_driver = {
1712 .probe = ifpga_cfg_probe,
1713 .remove = ifpga_cfg_remove,
1716 RTE_PMD_REGISTER_VDEV(ifpga_rawdev_cfg, ifpga_cfg_driver);
1717 RTE_PMD_REGISTER_ALIAS(ifpga_rawdev_cfg, ifpga_cfg);
1718 RTE_PMD_REGISTER_PARAM_STRING(ifpga_rawdev_cfg,